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@ -416,6 +416,39 @@ struct iomuxc { |
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}; |
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#endif |
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#define IOMUXC_GPR2_BITMAP_SPWG 0 |
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#define IOMUXC_GPR2_BITMAP_JEIDA 1 |
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#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 |
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#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) |
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#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \ |
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IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) |
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#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \ |
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IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) |
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#define IOMUXC_GPR2_DATA_WIDTH_18 0 |
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#define IOMUXC_GPR2_DATA_WIDTH_24 1 |
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#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 |
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#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) |
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#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \ |
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IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) |
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#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \ |
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IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) |
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#define IOMUXC_GPR2_MODE_DISABLED 0 |
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#define IOMUXC_GPR2_MODE_ENABLED_DI0 1 |
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#define IOMUXC_GPR2_MODE_ENABLED_DI1 3 |
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#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 |
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#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) |
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#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \ |
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IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) |
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#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \ |
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IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) |
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#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \ |
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IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) |
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/* System Reset Controller (SRC) */ |
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struct src { |
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u32 scr; |
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