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@ -22,6 +22,8 @@ |
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#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask]) |
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#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num]) |
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#define TIMES_9_TREFI_CYCLES 0x8 |
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u32 window_mem_addr = 0; |
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u32 phy_reg0_val = 0; |
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u32 phy_reg1_val = 8; |
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@ -315,6 +317,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ |
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enum hws_access_type access_type = ACCESS_TYPE_UNICAST; |
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u32 data_read[MAX_INTERFACE_NUM]; |
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struct hws_topology_map *tm = ddr3_get_topology_map(); |
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u32 odt_config = g_odt_config_2cs; |
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DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, |
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("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n", |
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@ -507,7 +510,9 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ |
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DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, |
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("cl_value 0x%x cwl_val 0x%x\n", |
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cl_value, cwl_val)); |
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t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index, |
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SPEED_BIN_TWR), |
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t_ckclk); |
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data_value = |
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((cl_mask_table[cl_value] & 0x1) << 2) | |
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((cl_mask_table[cl_value] & 0xe) << 3); |
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@ -517,8 +522,9 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ |
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(0x7 << 4) | (1 << 2))); |
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CHECK_STATUS(ddr3_tip_if_write |
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(dev_num, access_type, if_id, |
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MR0_REG, twr_mask_table[t_wr + 1], |
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0xe00)); |
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MR0_REG, twr_mask_table[t_wr + 1] << 9, |
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(0x7 << 9))); |
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/*
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* MR1: Set RTT and DIC Design GL values |
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@ -570,6 +576,9 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ |
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DUNIT_CONTROL_HIGH_REG, |
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(init_cntr_prm->msys_init << 7), (1 << 7))); |
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/* calculate number of CS (per interface) */ |
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CHECK_STATUS(calc_cs_num |
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(dev_num, if_id, &cs_num)); |
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timing = tm->interface_params[if_id].timing; |
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if (mode2_t != 0xff) { |
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@ -578,9 +587,6 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ |
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/* Board topology map is forcing timing */ |
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t2t = (timing == HWS_TIM_2T) ? 1 : 0; |
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} else { |
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/* calculate number of CS (per interface) */ |
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CHECK_STATUS(calc_cs_num |
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(dev_num, if_id, &cs_num)); |
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t2t = (cs_num == 1) ? 0 : 1; |
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} |
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@ -589,16 +595,15 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ |
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DDR_CONTROL_LOW_REG, t2t << 3, |
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0x3 << 3)); |
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/* move the block to ddr3_tip_set_timing - start */ |
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t_pd = GET_MAX_VALUE(t_ckclk * 3, |
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speed_bin_table(speed_bin_index, |
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SPEED_BIN_TPD)); |
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t_pd = TIME_2_CLOCK_CYCLES(t_pd, t_ckclk); |
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txpdll = GET_MAX_VALUE(t_ckclk * 10, 24); |
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t_pd = TIMES_9_TREFI_CYCLES; |
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txpdll = GET_MAX_VALUE(t_ckclk * 10, |
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speed_bin_table(speed_bin_index, |
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SPEED_BIN_TXPDLL)); |
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txpdll = CEIL_DIVIDE((txpdll - 1), t_ckclk); |
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CHECK_STATUS(ddr3_tip_if_write |
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(dev_num, access_type, if_id, |
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DDR_TIMING_REG, txpdll << 4, |
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0x1f << 4)); |
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DDR_TIMING_REG, txpdll << 4 | t_pd, |
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0x1f << 4 | 0xf)); |
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CHECK_STATUS(ddr3_tip_if_write |
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(dev_num, access_type, if_id, |
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DDR_TIMING_REG, 0x28 << 9, 0x3f << 9)); |
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@ -623,9 +628,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ |
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(1 << 11))); |
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/* Set Active control for ODT write transactions */ |
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if (cs_num == 1) |
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odt_config = g_odt_config_1cs; |
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CHECK_STATUS(ddr3_tip_if_write |
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(dev_num, ACCESS_TYPE_MULTICAST, |
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PARAM_NOT_CARE, 0x1494, g_odt_config, |
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PARAM_NOT_CARE, 0x1494, odt_config, |
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MASK_ALL_BITS)); |
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} |
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} else { |
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@ -1224,6 +1231,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, |
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u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0, |
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bus_cnt = 0, t_hclk = 0, t_wr = 0, |
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refresh_interval_cnt = 0, cnt_id; |
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u32 t_ckclk; |
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u32 t_refi = 0, end_if, start_if; |
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u32 bus_index = 0; |
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int is_dll_off = 0; |
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@ -1372,7 +1380,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, |
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/* adjust t_refi to new frequency */ |
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t_refi = (tm->interface_params[if_id].interface_temp == |
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HWS_TEMP_HIGH) ? TREFI_LOW : TREFI_HIGH; |
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HWS_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW; |
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t_refi *= 1000; /*psec */ |
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/* HCLK in[ps] */ |
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@ -1390,8 +1398,12 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, |
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CHECK_STATUS(ddr3_tip_if_write |
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(dev_num, access_type, if_id, DFS_REG, |
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(cwl_mask_table[cwl_value] << 12), 0x7000)); |
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t_wr = speed_bin_table(speed_bin_index, SPEED_BIN_TWR); |
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t_wr = (t_wr / 1000); |
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t_ckclk = MEGA / freq_val[frequency]; |
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t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index, |
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SPEED_BIN_TWR), |
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t_ckclk); |
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CHECK_STATUS(ddr3_tip_if_write |
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(dev_num, access_type, if_id, DFS_REG, |
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(twr_mask_table[t_wr + 1] << 16), 0x70000)); |
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@ -1539,7 +1551,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, |
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, |
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if_id, ODT_TIMING_LOW, |
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val, 0xffff0)); |
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val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); |
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val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); |
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, |
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if_id, ODT_TIMING_HI_REG, |
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val, 0xffff)); |
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@ -1591,7 +1603,7 @@ static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type, |
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, |
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ODT_TIMING_LOW, val, 0xffff0)); |
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val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); |
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val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); |
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, |
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ODT_TIMING_HI_REG, val, 0xffff)); |
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if (odt_additional == 1) { |
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