Add support for TQM5200 board * Patch by Martin Krause, 29 Jun 2004: Add loopw command: infinite write loop on address rangemaster
parent
857cad37a4
commit
56523f1283
@ -0,0 +1,46 @@ |
||||
#
|
||||
# (C) Copyright 2003-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := $(BOARD).o flash.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,41 @@ |
||||
#
|
||||
# (C) Copyright 2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# TQM5200 board:
|
||||
#
|
||||
# Valid values for TEXT_BASE are:
|
||||
#
|
||||
# 0xFC000000 boot low (standard configuration with room for max 64 MByte
|
||||
# Flash ROM)
|
||||
# 0x00100000 boot from RAM (for testing only)
|
||||
#
|
||||
|
||||
ifndef TEXT_BASE |
||||
## Standard: boot low
|
||||
TEXT_BASE = 0xFC000000
|
||||
## For testing: boot from RAM
|
||||
# TEXT_BASE = 0x00100000
|
||||
endif |
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
|
@ -0,0 +1,497 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/*
|
||||
* CPU to flash interface is 32-bit, so make declaration accordingly |
||||
*/ |
||||
typedef unsigned long FLASH_PORT_WIDTH; |
||||
typedef volatile unsigned long FLASH_PORT_WIDTHV; |
||||
|
||||
#define FPW FLASH_PORT_WIDTH |
||||
#define FPWV FLASH_PORT_WIDTHV |
||||
|
||||
#define FLASH_CYCLE1 0x0555 |
||||
#define FLASH_CYCLE2 0x02aa |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size(FPWV *addr, flash_info_t *info); |
||||
static void flash_reset(flash_info_t *info); |
||||
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); |
||||
static flash_info_t *flash_get_info(ulong base); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* flash_init() |
||||
* |
||||
* sets up flash_info and returns size of FLASH (bytes) |
||||
*/ |
||||
unsigned long flash_init (void) |
||||
{ |
||||
unsigned long size = 0; |
||||
extern void flash_preinit(void); |
||||
ulong flashbase = CFG_FLASH_BASE; |
||||
|
||||
flash_preinit(); |
||||
|
||||
/* Init: no FLASHes known */ |
||||
memset(&flash_info[0], 0, sizeof(flash_info_t)); |
||||
|
||||
flash_info[0].size = |
||||
flash_get_size((FPW *)flashbase, &flash_info[0]); |
||||
|
||||
size = flash_info[0].size; |
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
||||
/* monitor protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE+monitor_flash_len-1, |
||||
flash_get_info(CFG_MONITOR_BASE)); |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* ENV protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR+CFG_ENV_SIZE-1, |
||||
flash_get_info(CFG_ENV_ADDR)); |
||||
#endif |
||||
|
||||
return size ? size : 1; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_reset(flash_info_t *info) |
||||
{ |
||||
FPWV *base = (FPWV *)(info->start[0]); |
||||
|
||||
/* Put FLASH back in read mode */ |
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) |
||||
*base = (FPW)0x00FF00FF; /* Intel Read Mode */ |
||||
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) |
||||
*base = (FPW)0x00F000F0; /* AMD Read Mode */ |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
static flash_info_t *flash_get_info(ulong base) |
||||
{ |
||||
int i; |
||||
flash_info_t * info; |
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { |
||||
info = & flash_info[i]; |
||||
if (info->size && info->start[0] <= base && |
||||
base <= info->start[0] + info->size - 1) |
||||
break; |
||||
} |
||||
|
||||
return i == CFG_MAX_FLASH_BANKS ? 0 : info; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
void flash_print_info (flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: printf ("AMD "); break; |
||||
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; |
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
||||
case FLASH_MAN_SST: printf ("SST "); break; |
||||
case FLASH_MAN_STM: printf ("STM "); break; |
||||
case FLASH_MAN_INTEL: printf ("INTEL "); break; |
||||
default: printf ("Unknown Vendor "); break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_AMLV128U: |
||||
printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); |
||||
break; |
||||
case FLASH_AM160B: |
||||
printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
default: |
||||
printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, |
||||
info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
|
||||
for (i=0; i<info->sector_count; ++i) { |
||||
if ((i % 5) == 0) { |
||||
printf ("\n "); |
||||
} |
||||
printf (" %08lX%s", |
||||
info->start[i], |
||||
info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
printf ("\n"); |
||||
return; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
|
||||
ulong flash_get_size (FPWV *addr, flash_info_t *info) |
||||
{ |
||||
int i; |
||||
ulong base = (ulong)addr; |
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
/* Write auto select command sequence and test FLASH answer */ |
||||
addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ |
||||
addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ |
||||
addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ |
||||
|
||||
/* The manufacturer codes are only 1 byte, so just use 1 byte.
|
||||
* This works for any bus width and any FLASH device width. |
||||
*/ |
||||
udelay(100); |
||||
switch (addr[0] & 0xff) { |
||||
|
||||
case (uchar)AMD_MANUFACT: |
||||
debug ("Manufacturer: AMD (Spansion)\n"); |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
|
||||
case (uchar)INTEL_MANUFACT: |
||||
debug ("Manufacturer: Intel (not supported yet)\n"); |
||||
info->flash_id = FLASH_MAN_INTEL; |
||||
break; |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
break; |
||||
} |
||||
|
||||
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ |
||||
if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { |
||||
|
||||
case (FPW)AMD_ID_LV160B: |
||||
debug ("Chip: AM29LV160MB\n"); |
||||
info->flash_id += FLASH_AM160B; |
||||
info->sector_count = 35; |
||||
info->size = 0x00400000; |
||||
/*
|
||||
* The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all |
||||
* the other ones are 64 kB |
||||
*/ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00008000; |
||||
info->start[2] = base + 0x0000C000; |
||||
info->start[3] = base + 0x00010000; |
||||
for( i = 4; i < info->sector_count; i++ ) |
||||
info->start[i] = |
||||
base + (i * 2 * (64 << 10)) - 0x00060000; |
||||
break; /* => 4 MB */ |
||||
|
||||
case AMD_ID_MIRROR: |
||||
debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", |
||||
addr[14], addr[15]); |
||||
|
||||
switch(addr[14]) { |
||||
case AMD_ID_LV128U_2: |
||||
if (addr[15] != AMD_ID_LV128U_3) { |
||||
debug ("Chip: AM29LVxxxM -> unknown\n"); |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
} else { |
||||
debug ("Chip: AM29LV128M\n"); |
||||
info->flash_id += FLASH_AMLV128U; |
||||
info->sector_count = 256; |
||||
info->size = 0x02000000; |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
info->start[i] = base; |
||||
base += 0x20000; |
||||
} |
||||
} |
||||
break; /* => 32 MB */ |
||||
default: |
||||
debug ("Chip: *** unknown ***\n"); |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
break; |
||||
} |
||||
break; |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
} |
||||
|
||||
/* Put FLASH back in read mode */ |
||||
flash_reset(info); |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
vu_long *addr = (vu_long*)(info->start[0]); |
||||
int flag, prot, sect, l_sect; |
||||
ulong start, now, last; |
||||
|
||||
debug ("flash_erase: first: %d last: %d\n", s_first, s_last); |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) || |
||||
(info->flash_id > FLASH_AMD_COMP)) { |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0x00AA00AA; |
||||
addr[0x02AA] = 0x00550055; |
||||
addr[0x0555] = 0x00800080; |
||||
addr[0x0555] = 0x00AA00AA; |
||||
addr[0x02AA] = 0x00550055; |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr = (vu_long*)(info->start[sect]); |
||||
addr[0] = 0x00300030; |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
addr = (vu_long*)(info->start[l_sect]); |
||||
while ((addr[0] & 0x00800080) != 0x00800080) { |
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
DONE: |
||||
/* reset to read mode */ |
||||
addr = (volatile unsigned long *)info->start[0]; |
||||
addr[0] = 0x00F000F0; /* reset bank */ |
||||
|
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
/*
|
||||
* Get lower word aligned address. Assumes 32 bit flash bus width. |
||||
*/ |
||||
wp = (addr & ~3); |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word_amd(info, (FPW *)wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for AMD FLASH |
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank |
||||
* (not an individual chip) is. |
||||
* |
||||
* returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) |
||||
{ |
||||
ulong start; |
||||
int flag; |
||||
FPWV *base; /* first address in flash bank */ |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*dest & data) != data) { |
||||
return (2); |
||||
} |
||||
|
||||
base = (FPWV *)(info->start[0]); |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ |
||||
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ |
||||
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ |
||||
|
||||
*dest = data; /* start programming the data */ |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
start = get_timer (0); |
||||
|
||||
/* data polling for D7 */ |
||||
while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
*dest = (FPW)0x00F000F0; /* reset bank */ |
||||
return (1); |
||||
} |
||||
} |
||||
return (0); |
||||
} |
@ -0,0 +1,47 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#define SDRAM_DDR 0 /* is SDR */ |
||||
|
||||
#if defined(CONFIG_MPC5200) |
||||
/* Settings for XLB = 132 MHz */ |
||||
#define SDRAM_MODE 0x00CD0000 |
||||
/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ |
||||
#define SDRAM_CONTROL 0x504F0000 |
||||
#define SDRAM_CONFIG1 0xD2322800 |
||||
/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ |
||||
/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ |
||||
#define SDRAM_CONFIG2 0x8AD70000 |
||||
/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ |
||||
|
||||
#elif defined(CONFIG_MGT5100) |
||||
/* Settings for XLB = 66 MHz */ |
||||
#define SDRAM_MODE 0x008D0000 |
||||
#define SDRAM_CONTROL 0x504F0000 |
||||
#define SDRAM_CONFIG1 0xC2222600 |
||||
#define SDRAM_CONFIG2 0x88B70004 |
||||
#define SDRAM_ADDRSEL 0x02000000 |
||||
|
||||
#else |
||||
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined |
||||
#endif |
@ -0,0 +1,387 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc5xxx.h> |
||||
#include <pci.h> |
||||
|
||||
#if defined(CONFIG_MPC5200_DDR) |
||||
#include "mt46v16m16-75.h" |
||||
#else |
||||
#include "mt48lc16m16a2-75.h" |
||||
#endif |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
static void sdram_start (int hi_addr) |
||||
{ |
||||
long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
||||
|
||||
/* unlock mode register */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | |
||||
hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* precharge all banks */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | |
||||
hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
#if SDRAM_DDR |
||||
/* set mode register: extended mode */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register: reset DLL */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
||||
__asm__ volatile ("sync"); |
||||
#endif |
||||
|
||||
/* precharge all banks */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | |
||||
hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* auto refresh */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | |
||||
hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* normal operation */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* ATTENTION: Although partially referenced initdram does NOT make real use |
||||
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE |
||||
* is something else than 0x00000000. |
||||
*/ |
||||
|
||||
#if defined(CONFIG_MPC5200) |
||||
long int initdram (int board_type) |
||||
{ |
||||
ulong dramsize = 0; |
||||
ulong dramsize2 = 0; |
||||
#ifndef CFG_RAMBOOT |
||||
ulong test1, test2; |
||||
|
||||
/* setup SDRAM chip selects */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* setup config registers */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
#if SDRAM_DDR |
||||
/* set tap delay */ |
||||
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
||||
__asm__ volatile ("sync"); |
||||
#endif |
||||
|
||||
/* find RAM size using SDRAM CS0 only */ |
||||
sdram_start(0); |
||||
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); |
||||
sdram_start(1); |
||||
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); |
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize = test1; |
||||
} else { |
||||
dramsize = test2; |
||||
} |
||||
|
||||
/* memory smaller than 1MB is impossible */ |
||||
if (dramsize < (1 << 20)) { |
||||
dramsize = 0; |
||||
} |
||||
|
||||
/* set SDRAM CS0 size according to the amount of RAM found */ |
||||
if (dramsize > 0) { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + |
||||
__builtin_ffs(dramsize >> 20) - 1; |
||||
} else { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
||||
} |
||||
|
||||
/* let SDRAM CS1 start right after CS0 */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ |
||||
|
||||
/* find RAM size using SDRAM CS1 only */ |
||||
sdram_start(0); |
||||
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000); |
||||
sdram_start(1); |
||||
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000); |
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize2 = test1; |
||||
} else { |
||||
dramsize2 = test2; |
||||
} |
||||
|
||||
/* memory smaller than 1MB is impossible */ |
||||
if (dramsize2 < (1 << 20)) { |
||||
dramsize2 = 0; |
||||
} |
||||
|
||||
/* set SDRAM CS1 size according to the amount of RAM found */ |
||||
if (dramsize2 > 0) { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize |
||||
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); |
||||
} else { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
||||
} |
||||
|
||||
#else /* CFG_RAMBOOT */ |
||||
|
||||
/* retrieve size of memory connected to SDRAM CS0 */ |
||||
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
||||
if (dramsize >= 0x13) { |
||||
dramsize = (1 << (dramsize - 0x13)) << 20; |
||||
} else { |
||||
dramsize = 0; |
||||
} |
||||
|
||||
/* retrieve size of memory connected to SDRAM CS1 */ |
||||
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; |
||||
if (dramsize2 >= 0x13) { |
||||
dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
||||
} else { |
||||
dramsize2 = 0; |
||||
} |
||||
|
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
/* return dramsize + dramsize2; */ |
||||
return dramsize; |
||||
} |
||||
|
||||
#elif defined(CONFIG_MGT5100) |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
ulong dramsize = 0; |
||||
#ifndef CFG_RAMBOOT |
||||
ulong test1, test2; |
||||
|
||||
/* setup and enable SDRAM chip selects */ |
||||
*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; |
||||
*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ |
||||
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* setup config registers */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
||||
|
||||
/* address select register */ |
||||
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* find RAM size */ |
||||
sdram_start(0); |
||||
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); |
||||
sdram_start(1); |
||||
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); |
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize = test1; |
||||
} else { |
||||
dramsize = test2; |
||||
} |
||||
|
||||
/* set SDRAM end address according to size */ |
||||
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); |
||||
|
||||
#else /* CFG_RAMBOOT */ |
||||
|
||||
/* Retrieve amount of SDRAM available */ |
||||
dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); |
||||
|
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
return dramsize; |
||||
} |
||||
|
||||
#else |
||||
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined |
||||
#endif |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
#if defined (CONFIG_TQM5200_AA) |
||||
puts ("Board: TQM5200-AA (TQ-Systems GmbH)\n"); |
||||
#endif |
||||
#if defined (CONFIG_TQM5200_AB) |
||||
puts ("Board: TQM5200-AB (TQ-Systems GmbH)\n"); |
||||
#endif |
||||
#if defined (CONFIG_TQM5200_AC) |
||||
puts ("Board: TQM5200-AC (TQ-Systems GmbH)\n"); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
void flash_preinit(void) |
||||
{ |
||||
/*
|
||||
* Now, when we are in RAM, enable flash write |
||||
* access for detection process. |
||||
* Note that CS_BOOT cannot be cleared when |
||||
* executing in flash. |
||||
*/ |
||||
#if defined(CONFIG_MGT5100) |
||||
*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ |
||||
*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ |
||||
#endif |
||||
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
||||
} |
||||
|
||||
|
||||
#ifdef CONFIG_PCI |
||||
static struct pci_controller hose; |
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *); |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
pci_mpc5xxx_init(&hose); |
||||
} |
||||
#endif |
||||
|
||||
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) |
||||
|
||||
#if defined (CONFIG_MINIFAP) |
||||
#define SM501_POWER_MODE0_GATE 0x00000040UL |
||||
#define SM501_POWER_MODE1_GATE 0x00000048UL |
||||
#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL |
||||
#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL |
||||
#define SM501_GPIO_DATA_HIGH 0x00010004UL |
||||
#define SM501_GPIO_51 0x00080000UL |
||||
#else |
||||
#define GPIO_PSC1_4 0x01000000UL |
||||
#endif |
||||
|
||||
void init_ide_reset (void) |
||||
{ |
||||
debug ("init_ide_reset\n"); |
||||
|
||||
#if defined (CONFIG_MINIFAP) |
||||
/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */ |
||||
|
||||
/* enable GPIO control (in both power modes) */ |
||||
*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= |
||||
POWER_MODE_GATE_GPIO_PWM_I2C; |
||||
*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= |
||||
POWER_MODE_GATE_GPIO_PWM_I2C; |
||||
/* configure GPIO51 as output */ |
||||
*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= |
||||
SM501_GPIO_51; |
||||
#else |
||||
/* Configure PSC1_4 as GPIO output for ATA reset */ |
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; |
||||
#endif |
||||
} |
||||
|
||||
void ide_set_reset (int idereset) |
||||
{ |
||||
debug ("ide_reset(%d)\n", idereset); |
||||
|
||||
#if defined (CONFIG_MINIFAP) |
||||
if (idereset) { |
||||
*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= |
||||
~SM501_GPIO_51; |
||||
} else { |
||||
*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= |
||||
SM501_GPIO_51; |
||||
} |
||||
#else |
||||
if (idereset) { |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; |
||||
} else { |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; |
||||
} |
||||
#endif |
||||
} |
||||
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ |
||||
|
||||
#ifdef CONFIG_POST |
||||
/*
|
||||
* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 |
||||
* is left open, no keypress is detected. |
||||
*/ |
||||
int post_hotkeys_pressed(void) |
||||
{ |
||||
struct mpc5xxx_gpio *gpio; |
||||
|
||||
gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; |
||||
|
||||
/*
|
||||
* Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in |
||||
* CODEC or UART mode. Consumer IrDA should still be possible. |
||||
*/ |
||||
gpio->port_config &= ~(0x07000000); |
||||
gpio->port_config |= 0x03000000; |
||||
|
||||
/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ |
||||
gpio->simple_gpioe |= 0x20000000; |
||||
|
||||
/* Configure GPIO_IRDA_1 as input */ |
||||
gpio->simple_ddr &= ~(0x20000000); |
||||
|
||||
return ((gpio->simple_ival & 0x20000000) ? 0 : 1); |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) |
||||
|
||||
void post_word_store (ulong a) |
||||
{ |
||||
volatile ulong *save_addr = |
||||
(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); |
||||
|
||||
*save_addr = a; |
||||
} |
||||
|
||||
ulong post_word_load (void) |
||||
{ |
||||
volatile ulong *save_addr = |
||||
(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); |
||||
|
||||
return *save_addr; |
||||
} |
||||
|
||||
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ |
@ -0,0 +1,122 @@ |
||||
/* |
||||
* (C) Copyright 2003-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc5xxx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,525 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define DEBUG 1 |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
||||
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ |
||||
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ |
||||
|
||||
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Serial console configuration |
||||
*/ |
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
|
||||
#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ |
||||
/*
|
||||
* PCI Mapping: |
||||
* 0x40000000 - 0x4fffffff - PCI Memory |
||||
* 0x50000000 - 0x50ffffff - PCI IO Space |
||||
*/ |
||||
#define CONFIG_PCI 0 |
||||
#define CONFIG_PCI_PNP 1 |
||||
#define CONFIG_PCI_SCAN_SHOW 1 |
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0x40000000 |
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
||||
#define CONFIG_PCI_MEM_SIZE 0x10000000 |
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x50000000 |
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
||||
#define CONFIG_PCI_IO_SIZE 0x01000000 |
||||
|
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_EEPRO100 1 |
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
||||
#define CONFIG_NS8382X 1 |
||||
|
||||
#define ADD_PCI_CMD 0 /* CFG_CMD_PCI */ |
||||
|
||||
#else /* MPC5100 */ |
||||
|
||||
#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ |
||||
|
||||
#endif |
||||
|
||||
/* Partitions */ |
||||
#undef CONFIG_MAC_PARTITION |
||||
#if defined (CONFIG_MINIFAP) |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
/* USB */ |
||||
#if 0 |
||||
#define CONFIG_USB_OHCI |
||||
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT |
||||
#define CONFIG_USB_STORAGE |
||||
#else |
||||
#define ADD_USB_CMD 0 |
||||
#endif |
||||
|
||||
/* POST support */ |
||||
#define CONFIG_POST (CFG_POST_MEMORY | \ |
||||
CFG_POST_CPU | \
|
||||
CFG_POST_I2C) |
||||
|
||||
#ifdef CONFIG_POST |
||||
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG |
||||
/* preserve space for the post_word at end of on-chip SRAM */ |
||||
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 |
||||
#else |
||||
#define CFG_CMD_POST_DIAG 0 |
||||
#endif |
||||
|
||||
/* IDE */ |
||||
#if defined (CONFIG_MINIFAP) |
||||
#define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT |
||||
#else |
||||
#define ADD_IDE_CMD 0 |
||||
#endif |
||||
|
||||
/*
|
||||
* Supported commands |
||||
*/ |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_I2C | \
|
||||
ADD_PCI_CMD | \
|
||||
ADD_USB_CMD | \
|
||||
CFG_CMD_POST_DIAG | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING | \
|
||||
ADD_IDE_CMD) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#if (TEXT_BASE == 0xFC000000) /* Boot low */ |
||||
# define CFG_LOWBOOT 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* Autobooting |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#if defined (CONFIG_TQM5200_AA) |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
|
||||
"bootfile=uImage_tqm5200_mkr\0" \
|
||||
"load=tftp 200000 $(loadfile)\0" \
|
||||
"load133=tftp 200000 $(loadfile133)\0" \
|
||||
"loadfile=u-boot_tqm5200_aa_mkr.bin\0" \
|
||||
"loadfile133=u-boot_tqm5200_aa_133_mkr.bin\0" \
|
||||
"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
|
||||
"serverip=172.20.5.13\0" \
|
||||
"" |
||||
#else |
||||
#if defined (CONFIG_TQM5200_AB) |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
|
||||
"bootfile=uImage_tqm5200_mkr\0" \
|
||||
"load=tftp 200000 $(loadfile)\0" \
|
||||
"load133=tftp 200000 $(loadfile133)\0" \
|
||||
"loadfile=u-boot_tqm5200_ab_mkr.bin\0" \
|
||||
"loadfile133=u-boot_tqm5200_ab_133_mkr.bin\0" \
|
||||
"update=protect off 1:0-1; erase 1:0-1; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-1\0" \
|
||||
"serverip=172.20.5.13\0" \
|
||||
"" |
||||
#else |
||||
#if defined (CONFIG_TQM5200_AC) |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
|
||||
"bootfile=uImage_tqm5200_mkr\0" \
|
||||
"load=tftp 200000 $(loadfile)\0" \
|
||||
"load133=tftp 200000 $(loadfile133)\0" \
|
||||
"loadfile=u-boot_tqm5200_ac_mkr.bin\0" \
|
||||
"loadfile133=u-boot_tqm5200_ac_133_mkr.bin\0" \
|
||||
"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
|
||||
"serverip=172.20.5.13\0" \
|
||||
"" |
||||
#endif |
||||
#endif |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs" |
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration. |
||||
*/ |
||||
#define CFG_IPBSPEED_133 /* define for 133MHz speed */ |
||||
|
||||
#if defined(CFG_IPBSPEED_133) |
||||
/*
|
||||
* PCI Bus clocking configuration |
||||
* |
||||
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if |
||||
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't |
||||
* been tested with a IPB Bus Clock of 66 MHz. |
||||
*/ |
||||
#define CFG_PCISPEED_66 /* define for 66MHz speed */ |
||||
#endif |
||||
|
||||
/*
|
||||
* I2C configuration |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#if defined (CONFIG_MINIFAP) |
||||
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
||||
#else |
||||
#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ |
||||
#endif |
||||
|
||||
/*
|
||||
* I2C clock frequency |
||||
* |
||||
* Please notice, that the resulting clock frequency could differ from the |
||||
* configured value. This is because the I2C clock is derived from system |
||||
* clock over a frequency divider with only a few divider values. U-boot |
||||
* calculates the best approximation for CFG_I2C_SPEED. However the calculated |
||||
* approximation allways lies below the configured value, never above. |
||||
*/ |
||||
#define CFG_I2C_SPEED 100000 /* 100 kHz */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work |
||||
* also). For other EEPROMs configuration should be verified. On Mini-FAP the |
||||
* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the |
||||
* same configuration could be used. |
||||
*/ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 |
||||
|
||||
/*
|
||||
* HW-Monitor configuration on Mini-FAP |
||||
*/ |
||||
#if defined (CONFIG_MINIFAP) |
||||
#define CFG_I2C_HWMON_ADDR 0x2C |
||||
#endif |
||||
|
||||
/* List of I2C addresses to be verified by POST */ |
||||
#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB) |
||||
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ |
||||
CFG_I2C_SLAVE } |
||||
#elif defined (CONFIG_TQM5200_AC) |
||||
#define I2C_ADDR_LIST { CFG_I2C_SLAVE } |
||||
#endif |
||||
|
||||
#if defined (CONFIG_MINIFAP) |
||||
#undef I2C_ADDR_LIST |
||||
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ |
||||
CFG_I2C_HWMON_ADDR, \
|
||||
CFG_I2C_SLAVE } |
||||
#endif |
||||
|
||||
/*
|
||||
* Flash configuration |
||||
*/ |
||||
#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ |
||||
|
||||
#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AC) |
||||
#define CFG_FLASH_SIZE 0x00400000 /* 4 MByte */ |
||||
#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */ |
||||
#else |
||||
#ifdef CONFIG_TQM5200_AB |
||||
#define CFG_FLASH_SIZE 0x02000000 /* 32 MByte */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ |
||||
#endif |
||||
#endif |
||||
|
||||
#if !defined(CFG_LOWBOOT) |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000) |
||||
#else /* CFG_LOWBOOT */ |
||||
#if defined(CONFIG_TQM5200_AA) || defined(CONFIG_TQM5200_AB) || \ |
||||
defined (CONFIG_TQM5200_AC) |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) |
||||
#endif |
||||
#endif /* CFG_LOWBOOT */ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks |
||||
(= chip selects) */ |
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SIZE 0x10000 |
||||
#define CFG_ENV_SECT_SIZE 0x20000 |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
|
||||
/*
|
||||
* Memory map |
||||
*/ |
||||
#define CFG_MBAR 0xF0000000 |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_DEFAULT_MBAR 0x80000000 |
||||
|
||||
/* Use ON-Chip SRAM until RAM will be available */ |
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM |
||||
#ifdef CONFIG_POST |
||||
/* preserve space for the post_word at end of on-chip SRAM */ |
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE |
||||
#else |
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE |
||||
#endif |
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
# define CFG_RAMBOOT 1 |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Ethernet configuration |
||||
*/ |
||||
#define CONFIG_MPC5xxx_FEC 1 |
||||
/*
|
||||
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb |
||||
*/ |
||||
/* #define CONFIG_FEC_10MBIT 1 */ |
||||
#define CONFIG_PHY_ADDR 0x00 |
||||
|
||||
/*
|
||||
* GPIO configuration |
||||
* |
||||
* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): |
||||
* Bit 0 (mask: 0x80000000): 1 |
||||
* use ALT CAN position: Bits 2-3 (mask: 0x30000000): |
||||
* 00 -> No Alternatives, I2C1 is used for onboard EEPROM |
||||
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard |
||||
* EEPROM |
||||
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 |
||||
* use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000): |
||||
* 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible. |
||||
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST |
||||
* tests. |
||||
*/ |
||||
#if defined (CONFIG_MINIFAP) |
||||
#define CFG_GPS_PORT_CONFIG 0x93000004 |
||||
#else |
||||
#define CFG_GPS_PORT_CONFIG 0x83000004 |
||||
#endif |
||||
|
||||
/*
|
||||
* RTC configuration |
||||
*/ |
||||
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
/* Enable an alternate, more extensive memory test */ |
||||
#define CFG_ALT_MEMTEST |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*
|
||||
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, |
||||
* which is normally part of the default commands (CFV_CMD_DFL) |
||||
*/ |
||||
#define CONFIG_LOOPW |
||||
|
||||
/*
|
||||
* Various low-level settings |
||||
*/ |
||||
#if defined(CONFIG_MPC5200) |
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI |
||||
#define CFG_HID0_FINAL HID0_ICE |
||||
#else |
||||
#define CFG_HID0_INIT 0 |
||||
#define CFG_HID0_FINAL 0 |
||||
#endif |
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE |
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE |
||||
#ifdef CFG_PCISPEED_66 |
||||
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ |
||||
#else |
||||
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ |
||||
#endif |
||||
#define CFG_CS0_START CFG_FLASH_BASE |
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE |
||||
|
||||
/*
|
||||
* SRAM - Do not map below 2 GB in address space, because this area is used |
||||
* for SDRAM autosizing. |
||||
*/ |
||||
#ifdef CONFIG_TQM5200_AB |
||||
#define CFG_CS2_START 0xE5000000 |
||||
#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ |
||||
#define CFG_CS2_CFG 0x0004D930 |
||||
#endif |
||||
|
||||
/*
|
||||
* Grafic controller - Do not map below 2 GB in address space, because this |
||||
* area is used for SDRAM autosizing. |
||||
*/ |
||||
#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) |
||||
#define CFG_CS1_START 0xE0000000 |
||||
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ |
||||
#define CFG_CS1_CFG 0x0148FF70 |
||||
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 |
||||
#endif |
||||
|
||||
#define CFG_CS_BURST 0x00000000 |
||||
#define CFG_CS_DEADCYCLE 0x33333333 |
||||
|
||||
#define CFG_RESET_ADDRESS 0xff000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* USB stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_USB_CLOCK 0x0001BBBB |
||||
#define CONFIG_USB_CONFIG 0x00001000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */ |
||||
#define CONFIG_IDE_PREINIT |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (0x0060) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET (0x005C) |
||||
|
||||
/* Interval between registers */ |
||||
#define CFG_ATA_STRIDE 4 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue