Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add support for Adder boards with 16MB SDRAM;

Browse Source 
add support for second FEC on Adder87x board.
Patch by Yuli Barcohen, 05 Jun 2005
master
Wolfgang Denk 19 years ago
parent 7c54c7018e
commit 5797b821dc
3 changed files with 36 additions and 25 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 4
      CHANGELOG
  2. 24
      board/adder/adder.c
  3. 33
      include/configs/Adder.h

4
CHANGELOG
Unescape View File

@ -2,6 +2,10 @@
Changes since U-Boot 1.1.4:
======================================================================
* Add support for Adder boards with 16MB SDRAM;
add support for second FEC on Adder87x board.
Patch by Yuli Barcohen, 05 Jun 2005
* Fix conditional for including ks8695eth driver
Patch by Greg Ungerer, 04 Jun 2005

24
board/adder/adder.c
Unescape View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2004 Arabella Software Ltd.
* Copyright (C) 2004-2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Support for Analogue&Micro Adder boards family.
@ -28,7 +28,8 @@
#include <mpc8xx.h>
/*
* SDRAM is single Samsung K4S643232F-T70 chip.
* SDRAM is single Samsung K4S643232F-T70 chip (8MB)
* or single Micron MT48LC4M32B2TG-7 chip (16MB).
* Minimal CPU frequency is 40MHz.
*/
static uint sdram_table[] = {
@ -53,7 +54,7 @@ static uint sdram_table[] = {
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* Refresh (offset 0x30 in UPM RAM) */
0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
@ -63,7 +64,7 @@ static uint sdram_table[] = {
long int initdram (int board_type)
{
long int msize = CFG_SDRAM_SIZE;
long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
@ -72,11 +73,11 @@ long int initdram (int board_type)
/* Configure SDRAM refresh */
memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
memctl->memc_mamr = (94 << 24) | CFG_MAMR;
memctl->memc_mar = 0x0;
memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */
udelay(200);
/* Run precharge from location 0x15 */
memctl->memc_mar = 0x0;
memctl->memc_mcr = 0x80002115;
udelay(200);
@ -84,13 +85,18 @@ long int initdram (int board_type)
memctl->memc_mcr = 0x80002830;
udelay(200);
memctl->memc_mar = 0x88;
udelay(200);
/* Run MRS pattern from location 0x16 */
memctl->memc_mar = 0x88;
memctl->memc_mcr = 0x80002116;
udelay(200);
memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
memctl->memc_or1 |= ~(msize - 1);
return msize;
}

33
include/configs/Adder.h
Unescape View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2004 Arabella Software Ltd.
* Copyright (C) 2004-2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Support for Analogue&Micro Adder boards family.
@ -35,11 +35,13 @@
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 38400
#define CONFIG_FEC_ENET /* Ethernet is on FEC */
#ifdef CONFIG_FEC_ENET
#define CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
#define CFG_DISCOVER_PHY
#define FEC_ENET
#endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
@ -47,7 +49,7 @@
#ifdef CONFIG_MPC852T
#define CFG_8xx_CPUCLK_MAX 50000000
#else
#define CFG_8xx_CPUCLK_MAX 120000000
#define CFG_8xx_CPUCLK_MAX 133000000
#endif /* CONFIG_MPC852T */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
@ -62,7 +64,7 @@
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
@ -79,7 +81,7 @@
#define CFG_MAXARGS 16 /* Max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x100000 /* Default load address */
#define CFG_LOAD_ADDR 0x400000 /* Default load address */
#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
@ -89,24 +91,21 @@
* RAM configuration (note that CFG_SDRAM_BASE must be zero)
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2)
#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V)
#define CFG_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */
#define CFG_MAMR 0x00802114
#define CFG_MAMR 0x00002114
/*
* 2048 SDRAM rows
* 4096 Up to 4096 SDRAM rows
* 1000 factor s -> ms
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
* 32 PTP (pre-divider from MPTPR)
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
*/
#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */
#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
#define CFG_RESET_ADDRESS 0x09900000
@ -139,6 +138,8 @@
#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CONFIG_ENV_OVERWRITE
#define CFG_OR0_PRELIM 0xFF000774
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)

Write Preview
Loading…
Cancel
Save