Wolfgang Denk
16 years ago
commit
57fe30194d
@ -0,0 +1,664 @@ |
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/*
|
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* (C) Copyright 2003 |
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* Ingo Assmus <ingo.assmus@keymile.com> |
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* |
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* based on - Driver for MV64360X ethernet ports |
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* Copyright (C) 2002 rabeeh@galileo.co.il |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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* MA 02110-1301 USA |
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*/ |
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|
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#include <common.h> |
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#include <net.h> |
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#include <malloc.h> |
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#include <miiphy.h> |
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#include <asm/errno.h> |
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#include <asm/types.h> |
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#include <asm/byteorder.h> |
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#include <asm/arch/kirkwood.h> |
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#include "kirkwood_egiga.h" |
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|
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/*
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* smi_reg_read - miiphy_read callback function. |
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* |
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* Returns 16bit phy register value, or 0xffff on error |
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*/ |
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static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) |
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{ |
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struct eth_device *dev = eth_get_dev_by_name(devname); |
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struct kwgbe_device *dkwgbe = to_dkwgbe(dev); |
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struct kwgbe_registers *regs = dkwgbe->regs; |
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u32 smi_reg; |
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volatile u32 timeout; |
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|
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/* Phyadr read request */ |
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if (phy_adr == 0xEE && reg_ofs == 0xEE) { |
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/* */ |
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*data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK); |
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return 0; |
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} |
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/* check parameters */ |
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if (phy_adr > PHYADR_MASK) { |
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printf("Err..(%s) Invalid PHY address %d\n", |
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__FUNCTION__, phy_adr); |
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return -EFAULT; |
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} |
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if (reg_ofs > PHYREG_MASK) { |
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printf("Err..(%s) Invalid register offset %d\n", |
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__FUNCTION__, reg_ofs); |
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return -EFAULT; |
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} |
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timeout = KWGBE_PHY_SMI_TIMEOUT; |
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/* wait till the SMI is not busy */ |
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do { |
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/* read smi register */ |
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smi_reg = KWGBEREG_RD(regs->smi); |
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if (timeout-- == 0) { |
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printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); |
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return -EFAULT; |
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} |
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} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK); |
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|
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/* fill the phy address and regiser offset and read opcode */ |
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smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS) |
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| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS) |
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| KWGBE_PHY_SMI_OPCODE_READ; |
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/* write the smi register */ |
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KWGBEREG_WR(regs->smi, smi_reg); |
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/*wait till read value is ready */ |
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timeout = KWGBE_PHY_SMI_TIMEOUT; |
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do { |
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/* read smi register */ |
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smi_reg = KWGBEREG_RD(regs->smi); |
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if (timeout-- == 0) { |
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printf("Err..(%s) SMI read ready timeout\n", |
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__FUNCTION__); |
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return -EFAULT; |
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} |
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} while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK)); |
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|
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/* Wait for the data to update in the SMI register */ |
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for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ; |
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*data = (u16) (KWGBEREG_RD(regs->smi) & KWGBE_PHY_SMI_DATA_MASK); |
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debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr, |
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reg_ofs, *data); |
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return 0; |
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} |
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|
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/*
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* smi_reg_write - imiiphy_write callback function. |
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* |
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* Returns 0 if write succeed, -EINVAL on bad parameters |
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* -ETIME on timeout |
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*/ |
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static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data) |
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{ |
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struct eth_device *dev = eth_get_dev_by_name(devname); |
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struct kwgbe_device *dkwgbe = to_dkwgbe(dev); |
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struct kwgbe_registers *regs = dkwgbe->regs; |
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u32 smi_reg; |
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volatile u32 timeout; |
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/* Phyadr write request*/ |
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if (phy_adr == 0xEE && reg_ofs == 0xEE) { |
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KWGBEREG_WR(regs->phyadr, data); |
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return 0; |
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} |
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/* check parameters */ |
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if (phy_adr > PHYADR_MASK) { |
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printf("Err..(%s) Invalid phy address\n", __FUNCTION__); |
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return -EINVAL; |
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} |
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if (reg_ofs > PHYREG_MASK) { |
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printf("Err..(%s) Invalid register offset\n", __FUNCTION__); |
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return -EINVAL; |
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} |
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|
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/* wait till the SMI is not busy */ |
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timeout = KWGBE_PHY_SMI_TIMEOUT; |
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do { |
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/* read smi register */ |
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smi_reg = KWGBEREG_RD(regs->smi); |
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if (timeout-- == 0) { |
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printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); |
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return -ETIME; |
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} |
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} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK); |
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/* fill the phy addr and reg offset and write opcode and data */ |
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smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS); |
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smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS) |
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| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS); |
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smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ; |
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/* write the smi register */ |
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KWGBEREG_WR(regs->smi, smi_reg); |
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return 0; |
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} |
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/* Stop and checks all queues */ |
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static void stop_queue(u32 * qreg) |
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{ |
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u32 reg_data; |
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reg_data = readl(qreg); |
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if (reg_data & 0xFF) { |
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/* Issue stop command for active channels only */ |
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writel((reg_data << 8), qreg); |
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/* Wait for all queue activity to terminate. */ |
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do { |
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/*
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* Check port cause register that all queues |
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* are stopped |
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*/ |
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reg_data = readl(qreg); |
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} |
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while (reg_data & 0xFF); |
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} |
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} |
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/*
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* set_access_control - Config address decode parameters for Ethernet unit |
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* |
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* This function configures the address decode parameters for the Gigabit |
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* Ethernet Controller according the given parameters struct. |
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* |
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* @regs Register struct pointer. |
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* @param Address decode parameter struct. |
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*/ |
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static void set_access_control(struct kwgbe_registers *regs, |
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struct kwgbe_winparam *param) |
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{ |
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u32 access_prot_reg; |
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/* Set access control register */ |
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access_prot_reg = KWGBEREG_RD(regs->epap); |
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/* clear window permission */ |
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access_prot_reg &= (~(3 << (param->win * 2))); |
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access_prot_reg |= (param->access_ctrl << (param->win * 2)); |
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KWGBEREG_WR(regs->epap, access_prot_reg); |
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/* Set window Size reg (SR) */ |
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KWGBEREG_WR(regs->barsz[param->win].size, |
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(((param->size / 0x10000) - 1) << 16)); |
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/* Set window Base address reg (BA) */ |
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KWGBEREG_WR(regs->barsz[param->win].bar, |
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(param->target | param->attrib | param->base_addr)); |
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/* High address remap reg (HARR) */ |
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if (param->win < 4) |
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KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr); |
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/* Base address enable reg (BARER) */ |
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if (param->enable == 1) |
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KWGBEREG_BITS_RESET(regs->bare, (1 << param->win)); |
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else |
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KWGBEREG_BITS_SET(regs->bare, (1 << param->win)); |
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} |
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static void set_dram_access(struct kwgbe_registers *regs) |
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{ |
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struct kwgbe_winparam win_param; |
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int i; |
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
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/* Set access parameters for DRAM bank i */ |
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win_param.win = i; /* Use Ethernet window i */ |
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/* Window target - DDR */ |
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win_param.target = KWGBE_TARGET_DRAM; |
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/* Enable full access */ |
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win_param.access_ctrl = EWIN_ACCESS_FULL; |
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win_param.high_addr = 0; |
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/* Get bank base */ |
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win_param.base_addr = kw_sdram_bar(i); |
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win_param.size = kw_sdram_bs(i); /* Get bank size */ |
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if (win_param.size == 0) |
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win_param.enable = 0; |
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else |
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win_param.enable = 1; /* Enable the access */ |
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/* Enable DRAM bank */ |
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switch (i) { |
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case 0: |
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win_param.attrib = EBAR_DRAM_CS0; |
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break; |
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case 1: |
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win_param.attrib = EBAR_DRAM_CS1; |
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break; |
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case 2: |
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win_param.attrib = EBAR_DRAM_CS2; |
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break; |
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case 3: |
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win_param.attrib = EBAR_DRAM_CS3; |
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break; |
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default: |
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/* invalide bank, disable access */ |
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win_param.enable = 0; |
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win_param.attrib = 0; |
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break; |
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} |
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/* Set the access control for address window(EPAPR) RD/WR */ |
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set_access_control(regs, &win_param); |
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} |
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} |
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/*
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* port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables |
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* |
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* Go through all the DA filter tables (Unicast, Special Multicast & Other |
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* Multicast) and set each entry to 0. |
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*/ |
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static void port_init_mac_tables(struct kwgbe_registers *regs) |
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{ |
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int table_index; |
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/* Clear DA filter unicast table (Ex_dFUT) */ |
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for (table_index = 0; table_index < 4; ++table_index) |
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KWGBEREG_WR(regs->dfut[table_index], 0); |
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for (table_index = 0; table_index < 64; ++table_index) { |
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/* Clear DA filter special multicast table (Ex_dFSMT) */ |
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KWGBEREG_WR(regs->dfsmt[table_index], 0); |
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/* Clear DA filter other multicast table (Ex_dFOMT) */ |
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KWGBEREG_WR(regs->dfomt[table_index], 0); |
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} |
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} |
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/*
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* port_uc_addr - This function Set the port unicast address table |
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* |
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* This function locates the proper entry in the Unicast table for the |
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* specified MAC nibble and sets its properties according to function |
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* parameters. |
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* This function add/removes MAC addresses from the port unicast address |
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* table. |
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* |
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* @uc_nibble Unicast MAC Address last nibble. |
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* @option 0 = Add, 1 = remove address. |
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* |
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* RETURN: 1 if output succeeded. 0 if option parameter is invalid. |
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*/ |
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static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble, |
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int option) |
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{ |
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u32 unicast_reg; |
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u32 tbl_offset; |
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u32 reg_offset; |
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/* Locate the Unicast table entry */ |
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uc_nibble = (0xf & uc_nibble); |
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/* Register offset from unicast table base */ |
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tbl_offset = (uc_nibble / 4); |
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/* Entry offset within the above register */ |
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reg_offset = uc_nibble % 4; |
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switch (option) { |
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case REJECT_MAC_ADDR: |
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/*
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* Clear accepts frame bit at specified unicast |
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* DA table entry |
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*/ |
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unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]); |
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unicast_reg &= (0xFF << (8 * reg_offset)); |
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KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg); |
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break; |
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case ACCEPT_MAC_ADDR: |
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/* Set accepts frame bit at unicast DA filter table entry */ |
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unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]); |
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unicast_reg &= (0xFF << (8 * reg_offset)); |
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unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); |
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KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg); |
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break; |
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default: |
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return 0; |
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} |
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return 1; |
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} |
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/*
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* port_uc_addr_set - This function Set the port Unicast address. |
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*/ |
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static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr) |
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{ |
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u32 mac_h; |
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u32 mac_l; |
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mac_l = (p_addr[4] << 8) | (p_addr[5]); |
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mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | |
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(p_addr[3] << 0); |
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KWGBEREG_WR(regs->macal, mac_l); |
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KWGBEREG_WR(regs->macah, mac_h); |
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/* Accept frames of this address */ |
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port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); |
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} |
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/*
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* kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. |
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*/ |
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static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe) |
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{ |
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volatile struct kwgbe_rxdesc *p_rx_desc; |
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int i; |
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/* initialize the Rx descriptors ring */ |
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p_rx_desc = dkwgbe->p_rxdesc; |
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for (i = 0; i < RINGSZ; i++) { |
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p_rx_desc->cmd_sts = |
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KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT; |
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p_rx_desc->buf_size = PKTSIZE_ALIGN; |
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p_rx_desc->byte_cnt = 0; |
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p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN; |
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if (i == (RINGSZ - 1)) |
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p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc; |
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else { |
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p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *) |
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((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE); |
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p_rx_desc = p_rx_desc->nxtdesc_p; |
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} |
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} |
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dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc; |
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} |
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static int kwgbe_init(struct eth_device *dev) |
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{ |
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struct kwgbe_device *dkwgbe = to_dkwgbe(dev); |
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struct kwgbe_registers *regs = dkwgbe->regs; |
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|
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/* setup RX rings */ |
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kwgbe_init_rx_desc_ring(dkwgbe); |
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|
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/* Clear the ethernet port interrupts */ |
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KWGBEREG_WR(regs->ic, 0); |
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KWGBEREG_WR(regs->ice, 0); |
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/* Unmask RX buffer and TX end interrupt */ |
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KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); |
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/* Unmask phy and link status changes interrupts */ |
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KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); |
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|
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set_dram_access(regs); |
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port_init_mac_tables(regs); |
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port_uc_addr_set(regs, dkwgbe->dev.enetaddr); |
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|
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/* Assign port configuration and command. */ |
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KWGBEREG_WR(regs->pxc, PRT_CFG_VAL); |
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KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); |
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KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); |
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/* Disable port initially */ |
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KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN); |
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|
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/* Assign port SDMA configuration */ |
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KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); |
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KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); |
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KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); |
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/* Turn off the port/RXUQ bandwidth limitation */ |
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KWGBEREG_WR(regs->pmtu, 0); |
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|
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/* Set maximum receive buffer to 9700 bytes */ |
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KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE |
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| (KWGBEREG_RD(regs->psc0) & MRU_MASK)); |
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|
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/*
|
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* Set ethernet MTU for leaky bucket mechanism to 0 - this will |
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* disable the leaky bucket mechanism . |
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*/ |
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KWGBEREG_WR(regs->pmtu, 0); |
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|
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/* Assignment of Rx CRDB of given RXUQ */ |
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KWGBEREG_WR(regs->rxcdp[RXUQ].rxcdp, (u32) dkwgbe->p_rxdesc_curr); |
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/* Enable port Rx. */ |
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KWGBEREG_WR(regs->rqc, (1 << RXUQ)); |
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|
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#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ |
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&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) |
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u16 phyadr; |
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miiphy_read(dev->name, 0xEE, 0xEE, &phyadr); |
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if (!miiphy_link(dev->name, phyadr)) { |
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printf("%s: No link on %s\n", __FUNCTION__, dev->name); |
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return -1; |
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} |
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#endif |
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return 0; |
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} |
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|
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static int kwgbe_halt(struct eth_device *dev) |
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{ |
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struct kwgbe_device *dkwgbe = to_dkwgbe(dev); |
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struct kwgbe_registers *regs = dkwgbe->regs; |
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|
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/* Disable all gigE address decoder */ |
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KWGBEREG_WR(regs->bare, 0x3f); |
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|
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stop_queue(®s->tqc); |
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stop_queue(®s->rqc); |
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|
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/* Enable port */ |
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KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN); |
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/* Set port is not reset */ |
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KWGBEREG_BITS_RESET(regs->psc1, 1 << 4); |
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#ifdef CONFIG_SYS_MII_MODE |
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/* Set MMI interface up */ |
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KWGBEREG_BITS_RESET(regs->psc1, 1 << 3); |
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#endif |
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/* Disable & mask ethernet port interrupts */ |
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KWGBEREG_WR(regs->ic, 0); |
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KWGBEREG_WR(regs->ice, 0); |
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KWGBEREG_WR(regs->pim, 0); |
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KWGBEREG_WR(regs->peim, 0); |
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|
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return 0; |
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} |
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|
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static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, |
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int datasize) |
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{ |
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struct kwgbe_device *dkwgbe = to_dkwgbe(dev); |
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struct kwgbe_registers *regs = dkwgbe->regs; |
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struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc; |
||||
|
||||
if ((u32) dataptr & 0x07) { |
||||
printf("Err..(%s) xmit dataptr not 64bit aligned\n", |
||||
__FUNCTION__); |
||||
return -1; |
||||
} |
||||
p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC; |
||||
p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC; |
||||
p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA; |
||||
p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT; |
||||
p_txdesc->buf_ptr = (u8 *) dataptr; |
||||
p_txdesc->byte_cnt = datasize; |
||||
|
||||
/* Apply send command using zeroth RXUQ */ |
||||
KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc); |
||||
KWGBEREG_WR(regs->tqc, (1 << TXUQ)); |
||||
|
||||
/*
|
||||
* wait for packet xmit completion |
||||
*/ |
||||
while (p_txdesc->cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) { |
||||
/* return fail if error is detected */ |
||||
if (p_txdesc->cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) { |
||||
printf("Err..(%s) in xmit packet\n", __FUNCTION__); |
||||
return -1; |
||||
} |
||||
}; |
||||
return 0; |
||||
} |
||||
|
||||
static int kwgbe_recv(struct eth_device *dev) |
||||
{ |
||||
volatile struct kwgbe_device *dkwgbe = to_dkwgbe(dev); |
||||
volatile struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr; |
||||
volatile u32 timeout = 0; |
||||
|
||||
/* wait untill rx packet available or timeout */ |
||||
do { |
||||
if (timeout < KWGBE_PHY_SMI_TIMEOUT) |
||||
timeout++; |
||||
else { |
||||
debug("%s time out...\n", __FUNCTION__); |
||||
return -1; |
||||
} |
||||
} while (p_rxdesc_curr->cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA); |
||||
|
||||
if (p_rxdesc_curr->byte_cnt != 0) { |
||||
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", |
||||
__FUNCTION__, (u32) p_rxdesc_curr->byte_cnt, |
||||
(u32) p_rxdesc_curr->buf_ptr, |
||||
(u32) p_rxdesc_curr->cmd_sts); |
||||
} |
||||
|
||||
/*
|
||||
* In case received a packet without first/last bits on |
||||
* OR the error summary bit is on, |
||||
* the packets needs to be dropeed. |
||||
*/ |
||||
if ((p_rxdesc_curr->cmd_sts & |
||||
(KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) |
||||
!= (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) { |
||||
|
||||
printf("Err..(%s) Dropping packet spread on" |
||||
" multiple descriptors\n", __FUNCTION__); |
||||
|
||||
} else if (p_rxdesc_curr->cmd_sts & KWGBE_ERROR_SUMMARY) { |
||||
|
||||
printf("Err..(%s) Dropping packet with errors\n", |
||||
__FUNCTION__); |
||||
|
||||
} else { |
||||
/* !!! call higher layer processing */ |
||||
debug("%s: Sending Received packet to" |
||||
" upper layer (NetReceive)\n", __FUNCTION__); |
||||
|
||||
/* let the upper layer handle the packet */ |
||||
NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET), |
||||
(int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); |
||||
} |
||||
/*
|
||||
* free these descriptors and point next in the ring |
||||
*/ |
||||
p_rxdesc_curr->cmd_sts = |
||||
KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT; |
||||
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; |
||||
p_rxdesc_curr->byte_cnt = 0; |
||||
|
||||
dkwgbe->p_rxdesc_curr = p_rxdesc_curr->nxtdesc_p; |
||||
return 0; |
||||
} |
||||
|
||||
int kirkwood_egiga_initialize(bd_t * bis) |
||||
{ |
||||
struct kwgbe_device *dkwgbe; |
||||
struct eth_device *dev; |
||||
int devnum; |
||||
char *s, buf[NAMESIZE * 2]; |
||||
u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS; |
||||
|
||||
for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) { |
||||
/*skip if port is configured not to use */ |
||||
if (used_ports[devnum] == 0) |
||||
continue; |
||||
|
||||
if (!(dkwgbe = malloc(sizeof(struct kwgbe_device)))) |
||||
goto error1; |
||||
|
||||
memset(dkwgbe, 0, sizeof(struct kwgbe_device)); |
||||
|
||||
if (!(dkwgbe->p_rxdesc = |
||||
(struct kwgbe_rxdesc *)memalign(PKTALIGN, |
||||
KW_RXQ_DESC_ALIGNED_SIZE |
||||
* RINGSZ + 1))) |
||||
goto error2; |
||||
|
||||
if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ |
||||
* PKTSIZE_ALIGN + 1))) |
||||
goto error3; |
||||
|
||||
if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *) |
||||
memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) { |
||||
free(dkwgbe->p_rxbuf); |
||||
error3: |
||||
free(dkwgbe->p_rxdesc); |
||||
error2: |
||||
free(dkwgbe); |
||||
error1: |
||||
printf("Err.. %s Failed to allocate memory\n", |
||||
__FUNCTION__); |
||||
return -1; |
||||
} |
||||
|
||||
dev = &dkwgbe->dev; |
||||
|
||||
/* must be less than NAMESIZE (16) */ |
||||
sprintf(dev->name, "egiga%d", devnum); |
||||
|
||||
/* Extract the MAC address from the environment */ |
||||
switch (devnum) { |
||||
case 0: |
||||
dkwgbe->regs = (void *)KW_EGIGA0_BASE; |
||||
s = "ethaddr"; |
||||
break; |
||||
case 1: |
||||
dkwgbe->regs = (void *)KW_EGIGA1_BASE; |
||||
s = "eth1addr"; |
||||
break; |
||||
default: /* this should never happen */ |
||||
printf("Err..(%s) Invalid device number %d\n", |
||||
__FUNCTION__, devnum); |
||||
return -1; |
||||
} |
||||
|
||||
while (!eth_getenv_enetaddr(s, dev->enetaddr)) { |
||||
/* Generate Ramdom MAC addresses if not set */ |
||||
sprintf(buf, "00:50:43:%02x:%02x:%02x", |
||||
get_random_hex(), get_random_hex(), |
||||
get_random_hex()); |
||||
setenv(s, buf); |
||||
} |
||||
|
||||
dev->init = (void *)kwgbe_init; |
||||
dev->halt = (void *)kwgbe_halt; |
||||
dev->send = (void *)kwgbe_send; |
||||
dev->recv = (void *)kwgbe_recv; |
||||
|
||||
eth_register(dev); |
||||
|
||||
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
||||
miiphy_register(dev->name, smi_reg_read, smi_reg_write); |
||||
/* Set phy address of the port */ |
||||
miiphy_write(dev->name, 0xEE, 0xEE, PHY_BASE_ADR + devnum); |
||||
#endif |
||||
} |
||||
return 0; |
||||
@ -0,0 +1,503 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* based on - Driver for MV64360X ethernet ports |
||||
* Copyright (C) 2002 rabeeh@galileo.co.il |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#ifndef __EGIGA_H__ |
||||
#define __EGIGA_H__ |
||||
|
||||
#define MAX_KWGBE_DEVS 2 /*controller has two ports */ |
||||
|
||||
/* PHY_BASE_ADR is board specific and can be configured */ |
||||
#if defined (CONFIG_PHY_BASE_ADR) |
||||
#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR |
||||
#else |
||||
#define PHY_BASE_ADR 0x08 /* default phy base addr */ |
||||
#endif |
||||
|
||||
/* Constants */ |
||||
#define INT_CAUSE_UNMASK_ALL 0x0007ffff |
||||
#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff |
||||
#define MRU_MASK 0xfff1ffff |
||||
#define PHYADR_MASK 0x0000001f |
||||
#define PHYREG_MASK 0x0000001f |
||||
#define QTKNBKT_DEF_VAL 0x3fffffff |
||||
#define QMTBS_DEF_VAL 0x000003ff |
||||
#define QTKNRT_DEF_VAL 0x0000fcff |
||||
#define RXUQ 0 /* Used Rx queue */ |
||||
#define TXUQ 0 /* Used Rx queue */ |
||||
|
||||
#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev) |
||||
#define KWGBEREG_WR(adr, val) writel(val, &adr) |
||||
#define KWGBEREG_RD(adr) readl(&adr) |
||||
#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) |
||||
#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr) |
||||
|
||||
/* Default port configuration value */ |
||||
#define PRT_CFG_VAL ( \ |
||||
KWGBE_UCAST_MOD_NRML | \
|
||||
KWGBE_DFLT_RXQ(RXUQ) | \
|
||||
KWGBE_DFLT_RX_ARPQ(RXUQ) | \
|
||||
KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
|
||||
KWGBE_RX_BC_IF_IP | \
|
||||
KWGBE_RX_BC_IF_ARP | \
|
||||
KWGBE_CPTR_TCP_FRMS_DIS | \
|
||||
KWGBE_CPTR_UDP_FRMS_DIS | \
|
||||
KWGBE_DFLT_RX_TCPQ(RXUQ) | \
|
||||
KWGBE_DFLT_RX_UDPQ(RXUQ) | \
|
||||
KWGBE_DFLT_RX_BPDUQ(RXUQ)) |
||||
|
||||
/* Default port extend configuration value */ |
||||
#define PORT_CFG_EXTEND_VALUE \ |
||||
KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
|
||||
KWGBE_PARTITION_DIS | \
|
||||
KWGBE_TX_CRC_GENERATION_EN |
||||
|
||||
#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8) |
||||
|
||||
/* Default sdma control value */ |
||||
#define PORT_SDMA_CFG_VALUE ( \ |
||||
KWGBE_RX_BURST_SIZE_16_64BIT | \
|
||||
KWGBE_BLM_RX_NO_SWAP | \
|
||||
KWGBE_BLM_TX_NO_SWAP | \
|
||||
GT_KWGBE_IPG_INT_RX(RXUQ) | \
|
||||
KWGBE_TX_BURST_SIZE_16_64BIT) |
||||
|
||||
/* Default port serial control value */ |
||||
#define PORT_SERIAL_CONTROL_VALUE ( \ |
||||
KWGBE_FORCE_LINK_PASS | \
|
||||
KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
|
||||
KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
|
||||
KWGBE_ADV_NO_FLOW_CTRL | \
|
||||
KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
|
||||
KWGBE_FORCE_BP_MODE_NO_JAM | \
|
||||
(1 << 9) /* Reserved bit has to be 1 */ | \
|
||||
KWGBE_DO_NOT_FORCE_LINK_FAIL | \
|
||||
KWGBE_EN_AUTO_NEG_SPEED_GMII | \
|
||||
KWGBE_DTE_ADV_0 | \
|
||||
KWGBE_MIIPHY_MAC_MODE | \
|
||||
KWGBE_AUTO_NEG_NO_CHANGE | \
|
||||
KWGBE_MAX_RX_PACKET_1552BYTE | \
|
||||
KWGBE_CLR_EXT_LOOPBACK | \
|
||||
KWGBE_SET_FULL_DUPLEX_MODE | \
|
||||
KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX) |
||||
|
||||
/* Tx WRR confoguration macros */ |
||||
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ |
||||
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */ |
||||
#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */ |
||||
/* MAC accepet/reject macros */ |
||||
#define ACCEPT_MAC_ADDR 0 |
||||
#define REJECT_MAC_ADDR 1 |
||||
/* Size of a Tx/Rx descriptor used in chain list data structure */ |
||||
#define KW_RXQ_DESC_ALIGNED_SIZE \ |
||||
(((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN) |
||||
/* Buffer offset from buffer pointer */ |
||||
#define RX_BUF_OFFSET 0x2 |
||||
|
||||
/* Port serial status reg (PSR) */ |
||||
#define KWGBE_INTERFACE_GMII_MII 0 |
||||
#define KWGBE_INTERFACE_PCM 1 |
||||
#define KWGBE_LINK_IS_DOWN 0 |
||||
#define KWGBE_LINK_IS_UP (1 << 1) |
||||
#define KWGBE_PORT_AT_HALF_DUPLEX 0 |
||||
#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2) |
||||
#define KWGBE_RX_FLOW_CTRL_DISD 0 |
||||
#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3) |
||||
#define KWGBE_GMII_SPEED_100_10 0 |
||||
#define KWGBE_GMII_SPEED_1000 (1 << 4) |
||||
#define KWGBE_MII_SPEED_10 0 |
||||
#define KWGBE_MII_SPEED_100 (1 << 5) |
||||
#define KWGBE_NO_TX 0 |
||||
#define KWGBE_TX_IN_PROGRESS (1 << 7) |
||||
#define KWGBE_BYPASS_NO_ACTIVE 0 |
||||
#define KWGBE_BYPASS_ACTIVE (1 << 8) |
||||
#define KWGBE_PORT_NOT_AT_PARTN_STT 0 |
||||
#define KWGBE_PORT_AT_PARTN_STT (1 << 9) |
||||
#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0 |
||||
#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10) |
||||
|
||||
/* These macros describes the Port configuration reg (Px_cR) bits */ |
||||
#define KWGBE_UCAST_MOD_NRML 0 |
||||
#define KWGBE_UNICAST_PROMISCUOUS_MODE 1 |
||||
#define KWGBE_DFLT_RXQ(_x) (_x << 1) |
||||
#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4) |
||||
#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0 |
||||
#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) |
||||
#define KWGBE_RX_BC_IF_IP 0 |
||||
#define KWGBE_REJECT_BC_IF_IP (1 << 8) |
||||
#define KWGBE_RX_BC_IF_ARP 0 |
||||
#define KWGBE_REJECT_BC_IF_ARP (1 << 9) |
||||
#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12) |
||||
#define KWGBE_CPTR_TCP_FRMS_DIS 0 |
||||
#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14) |
||||
#define KWGBE_CPTR_UDP_FRMS_DIS 0 |
||||
#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15) |
||||
#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16) |
||||
#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19) |
||||
#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22) |
||||
#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25) |
||||
|
||||
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ |
||||
#define KWGBE_CLASSIFY_EN 1 |
||||
#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0 |
||||
#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1) |
||||
#define KWGBE_PARTITION_DIS 0 |
||||
#define KWGBE_PARTITION_EN (1 << 2) |
||||
#define KWGBE_TX_CRC_GENERATION_EN 0 |
||||
#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3) |
||||
|
||||
/* These macros describes the Port Sdma configuration reg (SDCR) bits */ |
||||
#define KWGBE_RIFB 1 |
||||
#define KWGBE_RX_BURST_SIZE_1_64BIT 0 |
||||
#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1) |
||||
#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2) |
||||
#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1)) |
||||
#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3) |
||||
#define KWGBE_BLM_RX_NO_SWAP (1 << 4) |
||||
#define KWGBE_BLM_RX_BYTE_SWAP 0 |
||||
#define KWGBE_BLM_TX_NO_SWAP (1 << 5) |
||||
#define KWGBE_BLM_TX_BYTE_SWAP 0 |
||||
#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6) |
||||
#define KWGBE_DESCRIPTORS_NO_SWAP 0 |
||||
#define KWGBE_TX_BURST_SIZE_1_64BIT 0 |
||||
#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22) |
||||
#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23) |
||||
#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22)) |
||||
#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24) |
||||
|
||||
/* These macros describes the Port serial control reg (PSCR) bits */ |
||||
#define KWGBE_SERIAL_PORT_DIS 0 |
||||
#define KWGBE_SERIAL_PORT_EN 1 |
||||
#define KWGBE_FORCE_LINK_PASS (1 << 1) |
||||
#define KWGBE_DO_NOT_FORCE_LINK_PASS 0 |
||||
#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0 |
||||
#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2) |
||||
#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0 |
||||
#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) |
||||
#define KWGBE_ADV_NO_FLOW_CTRL 0 |
||||
#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4) |
||||
#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 |
||||
#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) |
||||
#define KWGBE_FORCE_BP_MODE_NO_JAM 0 |
||||
#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7) |
||||
#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8) |
||||
#define KWGBE_FORCE_LINK_FAIL 0 |
||||
#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10) |
||||
#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13) |
||||
#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0 |
||||
#define KWGBE_DTE_ADV_0 0 |
||||
#define KWGBE_DTE_ADV_1 (1 << 14) |
||||
#define KWGBE_MIIPHY_MAC_MODE 0 |
||||
#define KWGBE_MIIPHY_PHY_MODE (1 << 15) |
||||
#define KWGBE_AUTO_NEG_NO_CHANGE 0 |
||||
#define KWGBE_RESTART_AUTO_NEG (1 << 16) |
||||
#define KWGBE_MAX_RX_PACKET_1518BYTE 0 |
||||
#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17) |
||||
#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18) |
||||
#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17)) |
||||
#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19) |
||||
#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17)) |
||||
#define KWGBE_SET_EXT_LOOPBACK (1 << 20) |
||||
#define KWGBE_CLR_EXT_LOOPBACK 0 |
||||
#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21) |
||||
#define KWGBE_SET_HALF_DUPLEX_MODE 0 |
||||
#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) |
||||
#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 |
||||
#define KWGBE_SET_GMII_SPEED_TO_10_100 0 |
||||
#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23) |
||||
#define KWGBE_SET_MII_SPEED_TO_10 0 |
||||
#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24) |
||||
|
||||
/* SMI register fields */ |
||||
#define KWGBE_PHY_SMI_TIMEOUT 10000 |
||||
#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */ |
||||
#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS) |
||||
#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ |
||||
#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS) |
||||
#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */ |
||||
#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS) |
||||
#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ |
||||
#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS) |
||||
#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS) |
||||
#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS) |
||||
#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */ |
||||
#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */ |
||||
|
||||
/* SDMA command status fields macros */ |
||||
/* Tx & Rx descriptors status */ |
||||
#define KWGBE_ERROR_SUMMARY 1 |
||||
/* Tx & Rx descriptors command */ |
||||
#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31) |
||||
/* Tx descriptors status */ |
||||
#define KWGBE_LC_ERROR 0 |
||||
#define KWGBE_UR_ERROR (1 << 1) |
||||
#define KWGBE_RL_ERROR (1 << 2) |
||||
#define KWGBE_LLC_SNAP_FORMAT (1 << 9) |
||||
|
||||
/* Rx descriptors status */ |
||||
#define KWGBE_CRC_ERROR 0 |
||||
#define KWGBE_OVERRUN_ERROR (1 << 1) |
||||
#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2) |
||||
#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1)) |
||||
#define KWGBE_VLAN_TAGGED (1 << 19) |
||||
#define KWGBE_BPDU_FRAME (1 << 20) |
||||
#define KWGBE_TCP_FRAME_OVER_IP_V_4 0 |
||||
#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21) |
||||
#define KWGBE_OTHER_FRAME_TYPE (1 << 22) |
||||
#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23) |
||||
#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24) |
||||
#define KWGBE_FRAME_HEADER_OK (1 << 25) |
||||
#define KWGBE_RX_LAST_DESC (1 << 26) |
||||
#define KWGBE_RX_FIRST_DESC (1 << 27) |
||||
#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28) |
||||
#define KWGBE_RX_EN_INTERRUPT (1 << 29) |
||||
#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30) |
||||
|
||||
/* Rx descriptors byte count */ |
||||
#define KWGBE_FRAME_FRAGMENTED (1 << 2) |
||||
|
||||
/* Tx descriptors command */ |
||||
#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10) |
||||
#define KWGBE_FRAME_SET_TO_VLAN (1 << 15) |
||||
#define KWGBE_TCP_FRAME 0 |
||||
#define KWGBE_UDP_FRAME (1 << 16) |
||||
#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17) |
||||
#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18) |
||||
#define KWGBE_ZERO_PADDING (1 << 19) |
||||
#define KWGBE_TX_LAST_DESC (1 << 20) |
||||
#define KWGBE_TX_FIRST_DESC (1 << 21) |
||||
#define KWGBE_GEN_CRC (1 << 22) |
||||
#define KWGBE_TX_EN_INTERRUPT (1 << 23) |
||||
#define KWGBE_AUTO_MODE (1 << 30) |
||||
|
||||
/* Address decode parameters */ |
||||
/* Ethernet Base Address Register bits */ |
||||
#define EBAR_TARGET_DRAM 0x00000000 |
||||
#define EBAR_TARGET_DEVICE 0x00000001 |
||||
#define EBAR_TARGET_CBS 0x00000002 |
||||
#define EBAR_TARGET_PCI0 0x00000003 |
||||
#define EBAR_TARGET_PCI1 0x00000004 |
||||
#define EBAR_TARGET_CUNIT 0x00000005 |
||||
#define EBAR_TARGET_AUNIT 0x00000006 |
||||
#define EBAR_TARGET_GUNIT 0x00000007 |
||||
|
||||
/* Window attrib */ |
||||
#define EBAR_DRAM_CS0 0x00000E00 |
||||
#define EBAR_DRAM_CS1 0x00000D00 |
||||
#define EBAR_DRAM_CS2 0x00000B00 |
||||
#define EBAR_DRAM_CS3 0x00000700 |
||||
|
||||
/* DRAM Target interface */ |
||||
#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000 |
||||
#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000 |
||||
#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000 |
||||
|
||||
/* Device Bus Target interface */ |
||||
#define EBAR_DEVICE_DEVCS0 0x00001E00 |
||||
#define EBAR_DEVICE_DEVCS1 0x00001D00 |
||||
#define EBAR_DEVICE_DEVCS2 0x00001B00 |
||||
#define EBAR_DEVICE_DEVCS3 0x00001700 |
||||
#define EBAR_DEVICE_BOOTCS3 0x00000F00 |
||||
|
||||
/* PCI Target interface */ |
||||
#define EBAR_PCI_BYTE_SWAP 0x00000000 |
||||
#define EBAR_PCI_NO_SWAP 0x00000100 |
||||
#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200 |
||||
#define EBAR_PCI_WORD_SWAP 0x00000300 |
||||
#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 |
||||
#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400 |
||||
#define EBAR_PCI_IO_SPACE 0x00000000 |
||||
#define EBAR_PCI_MEMORY_SPACE 0x00000800 |
||||
#define EBAR_PCI_REQ64_FORCE 0x00000000 |
||||
#define EBAR_PCI_REQ64_SIZE 0x00001000 |
||||
|
||||
/* Window access control */ |
||||
#define EWIN_ACCESS_NOT_ALLOWED 0 |
||||
#define EWIN_ACCESS_READ_ONLY 1 |
||||
#define EWIN_ACCESS_FULL ((1 << 1) | 1) |
||||
|
||||
/* structures represents Controller registers */ |
||||
struct kwgbe_barsz { |
||||
u32 bar; |
||||
u32 size; |
||||
}; |
||||
|
||||
struct kwgbe_rxcdp { |
||||
struct kwgbe_rxdesc *rxcdp; |
||||
u32 rxcdp_pad[3]; |
||||
}; |
||||
|
||||
struct kwgbe_tqx { |
||||
u32 qxttbc; |
||||
u32 tqxtbc; |
||||
u32 tqxac; |
||||
u32 tqxpad; |
||||
}; |
||||
|
||||
struct kwgbe_registers { |
||||
u32 phyadr; |
||||
u32 smi; |
||||
u32 euda; |
||||
u32 eudid; |
||||
u8 pad1[0x080 - 0x00c - 4]; |
||||
u32 euic; |
||||
u32 euim; |
||||
u8 pad2[0x094 - 0x084 - 4]; |
||||
u32 euea; |
||||
u32 euiae; |
||||
u8 pad3[0x0b0 - 0x098 - 4]; |
||||
u32 euc; |
||||
u8 pad3a[0x200 - 0x0b0 - 4]; |
||||
struct kwgbe_barsz barsz[6]; |
||||
u8 pad4[0x280 - 0x22c - 4]; |
||||
u32 ha_remap[4]; |
||||
u32 bare; |
||||
u32 epap; |
||||
u8 pad5[0x400 - 0x294 - 4]; |
||||
u32 pxc; |
||||
u32 pxcx; |
||||
u32 mii_ser_params; |
||||
u8 pad6[0x410 - 0x408 - 4]; |
||||
u32 evlane; |
||||
u32 macal; |
||||
u32 macah; |
||||
u32 sdc; |
||||
u32 dscp[7]; |
||||
u32 psc0; |
||||
u32 vpt2p; |
||||
u32 ps0; |
||||
u32 tqc; |
||||
u32 psc1; |
||||
u32 ps1; |
||||
u32 mrvl_header; |
||||
u8 pad7[0x460 - 0x454 - 4]; |
||||
u32 ic; |
||||
u32 ice; |
||||
u32 pim; |
||||
u32 peim; |
||||
u8 pad8[0x474 - 0x46c - 4]; |
||||
u32 pxtfut; |
||||
u32 pad9; |
||||
u32 pxmfs; |
||||
u32 pad10; |
||||
u32 pxdfc; |
||||
u32 pxofc; |
||||
u8 pad11[0x494 - 0x488 - 4]; |
||||
u32 peuiae; |
||||
u8 pad12[0x4bc - 0x494 - 4]; |
||||
u32 eth_type_prio; |
||||
u8 pad13[0x4dc - 0x4bc - 4]; |
||||
u32 tqfpc; |
||||
u32 pttbrc; |
||||
u32 tqc1; |
||||
u32 pmtu; |
||||
u32 pmtbs; |
||||
u8 pad14[0x60c - 0x4ec - 4]; |
||||
struct kwgbe_rxcdp rxcdp[7]; |
||||
u32 rxcdp7; |
||||
u32 rqc; |
||||
struct kwgbe_txdesc *tcsdp; |
||||
u8 pad15[0x6c0 - 0x684 - 4]; |
||||
struct kwgbe_txdesc *tcqdp[8]; |
||||
u8 pad16[0x700 - 0x6dc - 4]; |
||||
struct kwgbe_tqx tqx[8]; |
||||
u32 pttbc; |
||||
u8 pad17[0x7a8 - 0x780 - 4]; |
||||
u32 tqxipg0; |
||||
u32 pad18[3]; |
||||
u32 tqxipg1; |
||||
u8 pad19[0x7c0 - 0x7b8 - 4]; |
||||
u32 hitkninlopkt; |
||||
u32 hitkninasyncpkt; |
||||
u32 lotkninasyncpkt; |
||||
u32 pad20; |
||||
u32 ts; |
||||
u8 pad21[0x3000 - 0x27d0 - 4]; |
||||
u32 pad20_1[32]; /* mib counter registes */ |
||||
u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32]; |
||||
u32 dfsmt[64]; |
||||
u32 dfomt[64]; |
||||
u32 dfut[4]; |
||||
u8 pad23[0xe20c0 - 0x7360c - 4]; |
||||
u32 pmbus_top_arbiter; |
||||
}; |
||||
|
||||
/* structures/enums needed by driver */ |
||||
enum kwgbe_adrwin { |
||||
KWGBE_WIN0, |
||||
KWGBE_WIN1, |
||||
KWGBE_WIN2, |
||||
KWGBE_WIN3, |
||||
KWGBE_WIN4, |
||||
KWGBE_WIN5 |
||||
}; |
||||
|
||||
enum kwgbe_target { |
||||
KWGBE_TARGET_DRAM, |
||||
KWGBE_TARGET_DEV, |
||||
KWGBE_TARGET_CBS, |
||||
KWGBE_TARGET_PCI0, |
||||
KWGBE_TARGET_PCI1 |
||||
}; |
||||
|
||||
struct kwgbe_winparam { |
||||
enum kwgbe_adrwin win; /* Window number */ |
||||
enum kwgbe_target target; /* System targets */ |
||||
u16 attrib; /* BAR attrib. See above macros */ |
||||
u32 base_addr; /* Window base address in u32 form */ |
||||
u32 high_addr; /* Window high address in u32 form */ |
||||
u32 size; /* Size in MBytes. Must be % 64Kbyte. */ |
||||
int enable; /* Enable/disable access to the window. */ |
||||
u16 access_ctrl; /*Access ctrl register. see above macros */ |
||||
}; |
||||
|
||||
struct kwgbe_rxdesc { |
||||
u32 cmd_sts; /* Descriptor command status */ |
||||
u16 buf_size; /* Buffer size */ |
||||
u16 byte_cnt; /* Descriptor buffer byte count */ |
||||
u8 *buf_ptr; /* Descriptor buffer pointer */ |
||||
struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */ |
||||
}; |
||||
|
||||
struct kwgbe_txdesc { |
||||
u32 cmd_sts; /* Descriptor command status */ |
||||
u16 l4i_chk; /* CPU provided TCP Checksum */ |
||||
u16 byte_cnt; /* Descriptor buffer byte count */ |
||||
u8 *buf_ptr; /* Descriptor buffer ptr */ |
||||
struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */ |
||||
}; |
||||
|
||||
/* port device data struct */ |
||||
struct kwgbe_device { |
||||
struct eth_device dev; |
||||
struct kwgbe_registers *regs; |
||||
struct kwgbe_txdesc *p_txdesc; |
||||
struct kwgbe_rxdesc *p_rxdesc; |
||||
struct kwgbe_rxdesc *p_rxdesc_curr; |
||||
u8 *p_rxbuf; |
||||
}; |
||||
|
||||
#endif /* __EGIGA_H__ */ |
||||
@ -0,0 +1,413 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <netdev.h> |
||||
#include "mv88e61xx.h" |
||||
|
||||
#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE |
||||
/* Chip Address mode
|
||||
* The Switch support two modes of operation |
||||
* 1. single chip mode and |
||||
* 2. Multi-chip mode |
||||
* Refer section 9.2 &9.3 in chip datasheet-02 for more details |
||||
* |
||||
* By default single chip mode is configured |
||||
* multichip mode operation can be configured in board header |
||||
*/ |
||||
static int mv88e61xx_busychk_multic(u32 devaddr) |
||||
{ |
||||
u32 reg = 0; |
||||
u32 timeout = MV88E61XX_PHY_TIMEOUT; |
||||
|
||||
/* Poll till SMIBusy bit is clear */ |
||||
do { |
||||
miiphy_read(name, devaddr, 0x0, ®); |
||||
if (timeout-- == 0) { |
||||
printf("SMI busy timeout\n"); |
||||
return -1; |
||||
} |
||||
} while (reg & (1 << 15)); |
||||
return 0; |
||||
} |
||||
|
||||
static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) |
||||
{ |
||||
u16 reg; |
||||
u32 mii_dev_addr; |
||||
|
||||
/* command to read PHY dev address */ |
||||
if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { |
||||
printf("Error..could not read PHY dev address\n"); |
||||
return; |
||||
} |
||||
mv88e61xx_busychk_multic(mii_dev_addr); |
||||
/* Write data to Switch indirect data register */ |
||||
miiphy_write(name, mii_dev_addr, 0x1, data); |
||||
/* Write command to Switch indirect command register (write) */ |
||||
miiphy_write(name, mii_dev_addr, 0x0, |
||||
reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << |
||||
15)); |
||||
} |
||||
|
||||
static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) |
||||
{ |
||||
u16 reg; |
||||
u32 mii_dev_addr; |
||||
|
||||
/* command to read PHY dev address */ |
||||
if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { |
||||
printf("Error..could not read PHY dev address\n"); |
||||
return; |
||||
} |
||||
mv88e61xx_busychk_multic(mii_dev_addr); |
||||
/* Write command to Switch indirect command register (read) */ |
||||
miiphy_write(name, mii_dev_addr, 0x0, |
||||
reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << |
||||
15)); |
||||
mv88e61xx_busychk_multic(mii_dev_addr); |
||||
/* Read data from Switch indirect data register */ |
||||
miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); |
||||
} |
||||
#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ |
||||
|
||||
static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig, |
||||
u32 max_prtnum, u32 ports_ofs) |
||||
{ |
||||
u32 prt; |
||||
u16 reg; |
||||
char *name = swconfig->name; |
||||
u32 cpu_port = swconfig->cpuport; |
||||
u32 port_mask = swconfig->ports_enabled; |
||||
enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg; |
||||
|
||||
/* be sure all ports are disabled */ |
||||
for (prt = 0; prt < max_prtnum; prt++) { |
||||
RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, ®); |
||||
reg &= ~0x3; |
||||
WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg); |
||||
|
||||
if (!(cpu_port & (1 << prt))) |
||||
continue; |
||||
/* Set CPU port VID to 0x1 */ |
||||
RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, ®); |
||||
reg &= ~0xfff; |
||||
reg |= 0x1; |
||||
WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg); |
||||
} |
||||
|
||||
/* Setting Port default priority for all ports to zero */ |
||||
for (prt = 0; prt < max_prtnum; prt++) { |
||||
RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, ®); |
||||
reg &= ~0xc000; |
||||
WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg); |
||||
} |
||||
/* Setting VID and VID map for all ports except CPU port */ |
||||
for (prt = 0; prt < max_prtnum; prt++) { |
||||
/* only for enabled ports */ |
||||
if ((1 << prt) & port_mask) { |
||||
/* skip CPU port */ |
||||
if ((1 << prt) & cpu_port) { |
||||
/*
|
||||
* Set Vlan map table for cpu_port to see |
||||
* all ports |
||||
*/ |
||||
RD_PHY(name, (ports_ofs + prt), |
||||
MV88E61XX_PRT_VMAP_REG, ®); |
||||
reg &= ~((1 << max_prtnum) - 1); |
||||
reg |= port_mask & ~(1 << prt); |
||||
WR_PHY(name, (ports_ofs + prt), |
||||
MV88E61XX_PRT_VMAP_REG, reg); |
||||
} else { |
||||
|
||||
/*
|
||||
* set Ports VLAN Mapping. |
||||
* port prt <--> cpu_port VLAN #prt+1. |
||||
*/ |
||||
RD_PHY(name, ports_ofs + prt, |
||||
MV88E61XX_PRT_VID_REG, ®); |
||||
reg &= ~0x0fff; |
||||
reg |= (prt + 1); |
||||
WR_PHY(name, ports_ofs + prt, |
||||
MV88E61XX_PRT_VID_REG, reg); |
||||
|
||||
RD_PHY(name, ports_ofs + prt, |
||||
MV88E61XX_PRT_VMAP_REG, ®); |
||||
if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) { |
||||
/*
|
||||
* all any port can send frames to all other ports |
||||
* ref: sec 3.2.1.1 of datasheet |
||||
*/ |
||||
reg |= 0x03f; |
||||
reg &= ~(1 << prt); |
||||
} else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) { |
||||
/*
|
||||
* all other ports can send frames to CPU port only |
||||
* ref: sec 3.2.1.2 of datasheet |
||||
*/ |
||||
reg &= ~((1 << max_prtnum) - 1); |
||||
reg |= cpu_port; |
||||
} |
||||
WR_PHY(name, ports_ofs + prt, |
||||
MV88E61XX_PRT_VMAP_REG, reg); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* enable only appropriate ports to forwarding mode |
||||
* and disable the others |
||||
*/ |
||||
for (prt = 0; prt < max_prtnum; prt++) { |
||||
if ((1 << prt) & port_mask) { |
||||
RD_PHY(name, ports_ofs + prt, |
||||
MV88E61XX_PRT_CTRL_REG, ®); |
||||
reg |= 0x3; |
||||
WR_PHY(name, ports_ofs + prt, |
||||
MV88E61XX_PRT_CTRL_REG, reg); |
||||
} else { |
||||
/* Disable port */ |
||||
RD_PHY(name, ports_ofs + prt, |
||||
MV88E61XX_PRT_CTRL_REG, ®); |
||||
reg &= ~0x3; |
||||
WR_PHY(name, ports_ofs + prt, |
||||
MV88E61XX_PRT_CTRL_REG, reg); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Make sure SMIBusy bit cleared before another |
||||
* SMI operation can take place |
||||
*/ |
||||
static int mv88e61xx_busychk(char *name) |
||||
{ |
||||
u32 reg = 0; |
||||
u32 timeout = MV88E61XX_PHY_TIMEOUT; |
||||
do { |
||||
RD_PHY(name, MV88E61XX_GLB2REG_DEVADR, |
||||
MV88E61XX_PHY_CMD, (u16 *) & reg); |
||||
if (timeout-- == 0) { |
||||
printf("SMI busy timeout\n"); |
||||
return -1; |
||||
} |
||||
} while (reg & 1 << 28); /* busy mask */ |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Power up the specified port and reset PHY |
||||
*/ |
||||
static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt) |
||||
{ |
||||
char *name = swconfig->name; |
||||
|
||||
/* Write Copper Specific control reg1 (0x14) for-
|
||||
* Enable Phy power up |
||||
* Energy Detect on (sense&Xmit NLP Periodically |
||||
* reset other settings default |
||||
*/ |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360); |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, |
||||
MV88E61XX_PHY_CMD, (0x9410 | (prt << 5))); |
||||
|
||||
if (mv88e61xx_busychk(name)) |
||||
return -1; |
||||
|
||||
/* Write PHY ctrl reg (0x0) to apply
|
||||
* Phy reset (set bit 15 low) |
||||
* reset other default values |
||||
*/ |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140); |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, |
||||
MV88E61XX_PHY_CMD, (0x9400 | (prt << 5))); |
||||
|
||||
if (mv88e61xx_busychk(name)) |
||||
return -1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3) |
||||
* is set to "On-1000Mb/s Link, Off Else" |
||||
* This function sets it to "On-Link, Blink-Activity, Off-NoLink" |
||||
* |
||||
* This is optional settings may be needed on some boards |
||||
* to setup PHY LEDs default configuration to detect 10/100/1000Mb/s |
||||
* Link status |
||||
*/ |
||||
static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt) |
||||
{ |
||||
char *name = swconfig->name; |
||||
u16 reg; |
||||
|
||||
if (swconfig->led_init != MV88E61XX_LED_INIT_EN) |
||||
return 0; |
||||
|
||||
/* set page address to 3 */ |
||||
reg = 3; |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, |
||||
MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | |
||||
1 << MV88E61XX_MODE_OFST | |
||||
1 << MV88E61XX_OP_OFST | |
||||
prt << MV88E61XX_ADDR_OFST | 22)); |
||||
|
||||
if (mv88e61xx_busychk(name)) |
||||
return -1; |
||||
|
||||
/* set LED Func Ctrl reg */ |
||||
reg = 1; /* LED[0] On-Link, Blink-Activity, Off-NoLink */ |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, |
||||
MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | |
||||
1 << MV88E61XX_MODE_OFST | |
||||
1 << MV88E61XX_OP_OFST | |
||||
prt << MV88E61XX_ADDR_OFST | 16)); |
||||
|
||||
if (mv88e61xx_busychk(name)) |
||||
return -1; |
||||
|
||||
/* set page address to 0 */ |
||||
reg = 0; |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, |
||||
MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | |
||||
1 << MV88E61XX_MODE_OFST | |
||||
1 << MV88E61XX_OP_OFST | |
||||
prt << MV88E61XX_ADDR_OFST | 22)); |
||||
|
||||
if (mv88e61xx_busychk(name)) |
||||
return -1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Reverse Transmit polarity for Media Dependent Interface |
||||
* Pins (MDIP) bits in Copper Specific Control Register 3 |
||||
* (Page 0, Reg 20 for each phy (except cpu port) |
||||
* Reference: Section 1.1 Switch datasheet-3 |
||||
* |
||||
* This is optional settings may be needed on some boards |
||||
* for PHY<->magnetics h/w tuning |
||||
*/ |
||||
static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt) |
||||
{ |
||||
char *name = swconfig->name; |
||||
u16 reg; |
||||
|
||||
if (swconfig->mdip != MV88E61XX_MDIP_REVERSE) |
||||
return 0; |
||||
|
||||
reg = 0x0f; /*Reverse MDIP/N[3:0] bits */ |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); |
||||
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, |
||||
MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | |
||||
1 << MV88E61XX_MODE_OFST | |
||||
1 << MV88E61XX_OP_OFST | |
||||
prt << MV88E61XX_ADDR_OFST | 20)); |
||||
|
||||
if (mv88e61xx_busychk(name)) |
||||
return -1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Marvell 88E61XX Switch initialization |
||||
*/ |
||||
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) |
||||
{ |
||||
u32 prt; |
||||
u16 reg; |
||||
char *idstr; |
||||
char *name = swconfig->name; |
||||
|
||||
if (miiphy_set_current_dev(name)) { |
||||
printf("%s failed\n", __FUNCTION__); |
||||
return -1; |
||||
} |
||||
|
||||
if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { |
||||
swconfig->cpuport = (1 << 5); |
||||
printf("Invalid cpu port config, using default port5\n"); |
||||
} |
||||
|
||||
RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, ®); |
||||
reg &= 0xfff0; |
||||
if (reg == 0x1610) |
||||
idstr = "88E6161"; |
||||
if (reg == 0x1650) |
||||
idstr = "88E6165"; |
||||
if (reg == 0x1210) { |
||||
idstr = "88E6123"; |
||||
/* ports 2,3,4 not available */ |
||||
swconfig->ports_enabled &= 0x023; |
||||
} |
||||
|
||||
/* Port based VLANs configuration */ |
||||
if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT) |
||||
|| (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER)) |
||||
mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM, |
||||
MV88E61XX_PRT_OFST); |
||||
else { |
||||
printf("Unsupported mode %s failed\n", __FUNCTION__); |
||||
return -1; |
||||
} |
||||
|
||||
if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { |
||||
/*
|
||||
* Enable RGMII delay on Tx and Rx for CPU port |
||||
* Ref: sec 9.5 of chip datasheet-02 |
||||
*/ |
||||
WR_PHY(name, MV88E61XX_PRT_OFST + 5, |
||||
MV88E61XX_RGMII_TIMECTRL_REG, 0x18); |
||||
WR_PHY(name, MV88E61XX_PRT_OFST + 4, |
||||
MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); |
||||
} |
||||
|
||||
for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { |
||||
if (!((1 << prt) & swconfig->cpuport)) { |
||||
|
||||
if (mv88361xx_led_init(swconfig, prt)) |
||||
return -1; |
||||
if (mv88361xx_reverse_mdipn(swconfig, prt)) |
||||
return -1; |
||||
if (mv88361xx_powerup(swconfig, prt)) |
||||
return -1; |
||||
} |
||||
|
||||
/*Program port state */ |
||||
RD_PHY(name, MV88E61XX_PRT_OFST + prt, |
||||
MV88E61XX_PRT_CTRL_REG, ®); |
||||
WR_PHY(name, MV88E61XX_PRT_OFST + prt, |
||||
MV88E61XX_PRT_CTRL_REG, |
||||
reg | (swconfig->portstate & 0x03)); |
||||
} |
||||
|
||||
printf("%s Initialized on %s\n", idstr, name); |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,62 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#ifndef _MV88E61XX_H |
||||
#define _MV88E61XX_H |
||||
|
||||
#include <miiphy.h> |
||||
|
||||
#define MV88E61XX_CPU_PORT 0x5 |
||||
#define MV88E61XX_MAX_PORTS_NUM 0x6 |
||||
|
||||
#define MV88E61XX_PHY_TIMEOUT 100000 |
||||
|
||||
#define MV88E61XX_PRT_STS_REG 0x1 |
||||
#define MV88E61XX_PRT_CTRL_REG 0x4 |
||||
#define MV88E61XX_PRT_VMAP_REG 0x6 |
||||
#define MV88E61XX_PRT_VID_REG 0x7 |
||||
|
||||
#define MV88E61XX_PRT_OFST 0x10 |
||||
#define MV88E61XX_PHY_CMD 0x18 |
||||
#define MV88E61XX_PHY_DATA 0x19 |
||||
#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A |
||||
#define MV88E61XX_GLB2REG_DEVADR 0x1C |
||||
|
||||
#define MV88E61XX_BUSY_OFST 15 |
||||
#define MV88E61XX_MODE_OFST 12 |
||||
#define MV88E61XX_OP_OFST 10 |
||||
#define MV88E61XX_ADDR_OFST 5 |
||||
|
||||
#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE |
||||
static int mv88e61xx_busychk_multic(u32 devaddr); |
||||
static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data); |
||||
static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data); |
||||
#define WR_PHY mv88e61xx_wr_phy |
||||
#define RD_PHY mv88e61xx_rd_phy |
||||
#else |
||||
#define WR_PHY miiphy_write |
||||
#define RD_PHY miiphy_read |
||||
#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ |
||||
|
||||
#endif /* _MV88E61XX_H */ |
||||
Loading…
Reference in new issue