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@ -9,12 +9,15 @@ |
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#include <common.h> |
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#include <fsl_esdhc.h> |
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#include <mmc.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#include <linux/sizes.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/sys_proto.h> |
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@ -30,11 +33,28 @@ DECLARE_GLOBAL_DATA_PTR; |
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
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static iomux_v3_cfg_t const uart4_pads[] = { |
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IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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}; |
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static iomux_v3_cfg_t const enet_pads[] = { |
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IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | PAD_CTL_SRE_FAST)), |
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IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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}; |
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static iomux_v3_cfg_t const usdhc1_pads[] = { |
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IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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@ -99,6 +119,58 @@ int board_mmc_init(bd_t *bis) |
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} |
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#endif |
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#ifdef CONFIG_FEC_MXC |
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#define ENET_PHY_RST IMX_GPIO_NR(7, 12) |
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static int setup_fec(void) |
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{ |
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
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s32 timeout = 100000; |
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u32 reg = 0; |
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int ret; |
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/* Enable fec clock */ |
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setbits_le32(&ccm->CCGR1, MXC_CCM_CCGR1_ENET_MASK); |
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/* use 50MHz */ |
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ret = enable_fec_anatop_clock(0, ENET_50MHZ); |
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if (ret) |
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return ret; |
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/* Enable PLLs */ |
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reg = readl(&anatop->pll_enet); |
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reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; |
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writel(reg, &anatop->pll_enet); |
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reg = readl(&anatop->pll_enet); |
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reg |= BM_ANADIG_PLL_SYS_ENABLE; |
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while (timeout--) { |
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if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_SYS_LOCK) |
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break; |
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} |
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if (timeout <= 0) |
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return -EIO; |
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reg &= ~BM_ANADIG_PLL_SYS_BYPASS; |
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writel(reg, &anatop->pll_enet); |
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/* reset the phy */ |
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gpio_direction_output(ENET_PHY_RST, 0); |
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udelay(10000); |
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gpio_set_value(ENET_PHY_RST, 1); |
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return 0; |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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int ret; |
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SETUP_IOMUX_PADS(enet_pads); |
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setup_fec(); |
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return ret = cpu_eth_init(bis); |
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} |
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#endif |
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int board_early_init_f(void) |
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{ |
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SETUP_IOMUX_PADS(uart4_pads); |
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