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ppc4xx: Replace 4xx lowercase SPR references

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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
master
Matthias Fuchs 15 years ago committed by Stefan Roese
parent 87c0b72908
commit 58ea142fb2
15 changed files with 178 additions and 279 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      board/esd/pmc440/pmc440.c
  2. 2
      board/mpl/mip405/mip405.c
  3. 2
      board/mpl/pip405/pip405.c
  4. 8
      board/netstal/hcu5/hcu5.c
  5. 4
      board/netstal/hcu5/sdram.c
  6. 2
      board/netstal/mcu25/mcu25.c
  7. 8
      cpu/ppc4xx/cpu.c
  8. 2
      cpu/ppc4xx/cpu_init.c
  9. 18
      cpu/ppc4xx/interrupts.c
  10. 3
      cpu/ppc4xx/speed.c
  11. 206
      cpu/ppc4xx/start.S
  12. 46
      include/asm-ppc/processor.h
  13. 55
      include/ppc405.h
  14. 93
      include/ppc440.h
  15. 6
      post/cpu/ppc4xx/fpu.c

2
board/esd/pmc440/pmc440.c
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@ -142,7 +142,7 @@ int board_early_init_f(void)
reg |= CPR0_ICFG_RLI_MASK;
mtcpr(clk_icfg, reg);
mtspr(dbcr0, 0x20000000); /* do chip reset */
mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
}
/*

2
board/mpl/mip405/mip405.c
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@ -688,7 +688,7 @@ int misc_init_r (void)
start=get_timer(0);
/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
mtspr(ccr0, (mfspr(ccr0) & ~0x80));
mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);
}

2
board/mpl/pip405/pip405.c
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@ -669,7 +669,7 @@ int misc_init_r (void)
/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
mtspr(ccr0, (mfspr(ccr0) & ~0x80));
mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);
}

8
board/netstal/hcu5/hcu5.c
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@ -89,8 +89,8 @@ int board_early_init_f(void)
/*
* Initiate system reset in debug control register DBCR
*/
dbcr = mfspr(dbcr0);
mtspr(dbcr0, dbcr | CHIP_RESET);
dbcr = mfspr(SPRN_DBCR0);
mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
}
mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
#endif
@ -307,14 +307,14 @@ int misc_init_r(void)
/* We cannot easily enable trace before, as there are other
* routines messing around with sdr0_pfc1. And I do not need it.
*/
if (mfspr(dbcr0) & 0x80000000) {
if (mfspr(SPRN_DBCR0) & 0x80000000) {
/* External debugger alive
* enable trace facilty for Lauterbach
* CCR0[DTB]=0 Enable broadcast of trace information
* SDR0_PFC0[TRE] Trace signals are enabled instead of
* GPIO49-63
*/
mtspr(ccr0, mfspr(ccr0) &~ (CCR0_DTB));
mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));
mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
}
return 0;

4
board/netstal/hcu5/sdram.c
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@ -144,7 +144,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
u32 *magicPtr;
u32 magic;
if ((mfspr(dbcr0) & 0x80000000) == 0) {
if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) {
/* only if no external debugger is alive!
* Check whether vxWorks is using EDR logging, if yes zero
* also PostMortem and user reserved memory
@ -182,7 +182,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
mtspr(mcsr, mfspr(mcsr));
mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
/* Set 'int_mask' parameter to functionnal value */
mfsdram(DDR0_01, val);

2
board/netstal/mcu25/mcu25.c
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@ -77,7 +77,7 @@ int board_early_init_f (void)
out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR );
out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);
out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);
mtspr(ccr0, 0x00700000);
mtspr(SPRN_CCR0, 0x00700000);
return 0;
}

8
cpu/ppc4xx/cpu.c
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@ -272,7 +272,7 @@ static int do_chip_reset (unsigned long sys0, unsigned long sys1)
mtdcr (cpc0_sys0, sys0);
mtdcr (cpc0_sys1, sys1);
mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
mtspr (dbcr0, 0x20000000); /* Reset the chip */
mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
return 1;
}
@ -654,12 +654,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
board_reset();
#else
#if defined(CONFIG_SYS_4xx_RESET_TYPE)
mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
#else
/*
* Initiate system reset in debug control register DBCR
*/
mtspr(dbcr0, 0x30000000);
mtspr(SPRN_DBCR0, 0x30000000);
#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
#endif /* defined(CONFIG_BOARD_RESET) */
@ -697,7 +697,7 @@ void reset_4xx_watchdog(void)
/*
* Clear TSR(WIS) bit
*/
mtspr(tsr, 0x40000000);
mtspr(SPRN_TSR, 0x40000000);
}
#endif /* CONFIG_WATCHDOG */

2
cpu/ppc4xx/cpu_init.c
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@ -123,7 +123,7 @@ void reconfigure_pll(u32 new_cpu_freq)
/* Reset processor if configuration changed */
if (reset_needed) {
__asm__ __volatile__ ("sync; isync");
mtspr(dbcr0, 0x20000000);
mtspr(SPRN_DBCR0, 0x20000000);
}
#endif
}

18
cpu/ppc4xx/interrupts.c
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@ -102,15 +102,15 @@ int interrupt_init_cpu (unsigned *decrementer_count)
* Init PIT
*/
#if defined(CONFIG_440)
val = mfspr( tcr );
val = mfspr( SPRN_TCR );
val &= (~0x04400000); /* clear DIS & ARE */
mtspr( tcr, val );
mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
mtspr( decar, 0 ); /* clear reload */
mtspr( tsr, 0x08000000 ); /* clear DEC status */
mtspr( SPRN_TCR, val );
mtspr( SPRN_DEC, 0 ); /* Prevent exception after TSR clear*/
mtspr( SPRN_DECAR, 0 ); /* clear reload */
mtspr( SPRN_TSR, 0x08000000 ); /* clear DEC status */
val = gd->bd->bi_intfreq/1000; /* 1 msec */
mtspr( decar, val ); /* Set auto-reload value */
mtspr( dec, val ); /* Set inital val */
mtspr( SPRN_DECAR, val ); /* Set auto-reload value */
mtspr( SPRN_DEC, val ); /* Set inital val */
#else
set_pit(gd->bd->bi_intfreq / 1000);
#endif
@ -126,9 +126,9 @@ int interrupt_init_cpu (unsigned *decrementer_count)
/*
* Enable PIT
*/
val = mfspr(tcr);
val = mfspr(SPRN_TCR);
val |= 0x04400000;
mtspr(tcr, val);
mtspr(SPRN_TCR, val);
/*
* Set EVPR to 0

3
cpu/ppc4xx/speed.c
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@ -394,7 +394,8 @@ void get_sys_info (sys_info_t *sysInfo)
sysInfo->freqUART = sysInfo->freqPLB;
/* Figure which timer source to use */
if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */
if (mfspr(SPRN_CCR1) & 0x0080) {
/* External Clock, assume same as SYS_CLK */
temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */
if (CONFIG_SYS_CLK_FREQ > temp)
sysInfo->freqTmrClk = temp;

206
cpu/ppc4xx/start.S
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@ -297,7 +297,7 @@ _start_440:
| Core bug fix. Clear the esr
+-----------------------------------------------------------------*/
li r0,0
mtspr esr,r0
mtspr SPRN_ESR,r0
/*----------------------------------------------------------------*/
/* Clear and set up some registers. */
/*----------------------------------------------------------------*/
@ -305,16 +305,16 @@ _start_440:
dccci r0,r0 /* NOTE: operands not used for 440 */
sync
li r0,0
mtspr srr0,r0
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
mtspr SPRN_SRR0,r0
mtspr SPRN_SRR1,r0
mtspr SPRN_CSRR0,r0
mtspr SPRN_CSRR1,r0
/* NOTE: 440GX adds machine check status regs */
#if defined(CONFIG_440) && !defined(CONFIG_440GP)
mtspr mcsrr0,r0
mtspr mcsrr1,r0
mfspr r1,mcsr
mtspr mcsr,r1
mtspr SPRN_MCSRR0,r0
mtspr SPRN_MCSRR1,r0
mfspr r1,SPRN_MCSR
mtspr SPRN_MCSR,r1
#endif
/*----------------------------------------------------------------*/
@ -326,27 +326,27 @@ _start_440:
*/
lis r1,0x0030 /* store gathering & broadcast disable */
ori r1,r1,0x6000 /* cache touch */
mtspr ccr0,r1
mtspr SPRN_CCR0,r1
/*----------------------------------------------------------------*/
/* Initialize debug */
/*----------------------------------------------------------------*/
mfspr r1,dbcr0
mfspr r1,SPRN_DBCR0
andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
bne skip_debug_init /* if set, don't clear debug register */
mtspr dbcr0,r0
mtspr dbcr1,r0
mtspr dbcr2,r0
mtspr iac1,r0
mtspr iac2,r0
mtspr iac3,r0
mtspr dac1,r0
mtspr dac2,r0
mtspr dvc1,r0
mtspr dvc2,r0
mfspr r1,dbsr
mtspr dbsr,r1 /* Clear all valid bits */
mtspr SPRN_DBCR0,r0
mtspr SPRN_DBCR1,r0
mtspr SPRN_DBCR2,r0
mtspr SPRN_IAC1,r0
mtspr SPRN_IAC2,r0
mtspr SPRN_IAC3,r0
mtspr SPRN_DAC1,r0
mtspr SPRN_DAC2,r0
mtspr SPRN_DVC1,r0
mtspr SPRN_DVC2,r0
mfspr r1,SPRN_DBSR
mtspr SPRN_DBSR,r1 /* Clear all valid bits */
skip_debug_init:
#if defined (CONFIG_440SPE)
@ -364,68 +364,68 @@ skip_debug_init:
| j. TCS: Timebase increments from CPU clock.
+-----------------------------------------------------------------*/
li r0,0
mtspr ccr1, r0
mtspr SPRN_CCR1, r0
/*----------------------------------------------------------------+
| Reset the timebase.
| The previous write to CCR1 sets the timebase source.
+-----------------------------------------------------------------*/
mtspr tbl, r0
mtspr tbu, r0
mtspr SPRN_TBWL, r0
mtspr SPRN_TBWU, r0
#endif
/*----------------------------------------------------------------*/
/* Setup interrupt vectors */
/*----------------------------------------------------------------*/
mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
li r1,0x0100
mtspr ivor0,r1 /* Critical input */
mtspr SPRN_IVOR0,r1 /* Critical input */
li r1,0x0200
mtspr ivor1,r1 /* Machine check */
mtspr SPRN_IVOR1,r1 /* Machine check */
li r1,0x0300
mtspr ivor2,r1 /* Data storage */
mtspr SPRN_IVOR2,r1 /* Data storage */
li r1,0x0400
mtspr ivor3,r1 /* Instruction storage */
mtspr SPRN_IVOR3,r1 /* Instruction storage */
li r1,0x0500
mtspr ivor4,r1 /* External interrupt */
mtspr SPRN_IVOR4,r1 /* External interrupt */
li r1,0x0600
mtspr ivor5,r1 /* Alignment */
mtspr SPRN_IVOR5,r1 /* Alignment */
li r1,0x0700
mtspr ivor6,r1 /* Program check */
mtspr SPRN_IVOR6,r1 /* Program check */
li r1,0x0800
mtspr ivor7,r1 /* Floating point unavailable */
mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
li r1,0x0c00
mtspr ivor8,r1 /* System call */
mtspr SPRN_IVOR8,r1 /* System call */
li r1,0x0a00
mtspr ivor9,r1 /* Auxiliary Processor unavailable */
mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
li r1,0x0900
mtspr ivor10,r1 /* Decrementer */
mtspr SPRN_IVOR10,r1 /* Decrementer */
li r1,0x1300
mtspr ivor13,r1 /* Data TLB error */
mtspr SPRN_IVOR13,r1 /* Data TLB error */
li r1,0x1400
mtspr ivor14,r1 /* Instr TLB error */
mtspr SPRN_IVOR14,r1 /* Instr TLB error */
li r1,0x2000
mtspr ivor15,r1 /* Debug */
mtspr SPRN_IVOR15,r1 /* Debug */
/*----------------------------------------------------------------*/
/* Configure cache regions */
/*----------------------------------------------------------------*/
mtspr inv0,r0
mtspr inv1,r0
mtspr inv2,r0
mtspr inv3,r0
mtspr dnv0,r0
mtspr dnv1,r0
mtspr dnv2,r0
mtspr dnv3,r0
mtspr itv0,r0
mtspr itv1,r0
mtspr itv2,r0
mtspr itv3,r0
mtspr dtv0,r0
mtspr dtv1,r0
mtspr dtv2,r0
mtspr dtv3,r0
mtspr SPRN_INV0,r0
mtspr SPRN_INV1,r0
mtspr SPRN_INV2,r0
mtspr SPRN_INV3,r0
mtspr SPRN_DNV0,r0
mtspr SPRN_DNV1,r0
mtspr SPRN_DNV2,r0
mtspr SPRN_DNV3,r0
mtspr SPRN_ITV0,r0
mtspr SPRN_ITV1,r0
mtspr SPRN_ITV2,r0
mtspr SPRN_ITV3,r0
mtspr SPRN_DTV0,r0
mtspr SPRN_DTV1,r0
mtspr SPRN_DTV2,r0
mtspr SPRN_DTV3,r0
/*----------------------------------------------------------------*/
/* Cache victim limits */
@ -434,17 +434,17 @@ skip_debug_init:
*/
lis r1,0x0001
ori r1,r1,0xf800
mtspr ivlim,r1
mtspr dvlim,r1
mtspr SPRN_IVLIM,r1
mtspr SPRN_DVLIM,r1
/*----------------------------------------------------------------+
|Initialize MMUCR[STID] = 0.
+-----------------------------------------------------------------*/
mfspr r0,mmucr
mfspr r0,SPRN_MMUCR
addis r1,0,0xFFFF
ori r1,r1,0xFF00
and r0,r0,r1
mtspr mmucr,r0
mtspr SPRN_MMUCR,r0
/*----------------------------------------------------------------*/
/* Clear all TLB entries -- TID = 0, TS = 0 */
@ -521,9 +521,9 @@ tlbnx2: addi r4,r4,1 /* Next TLB */
b _start
3: li r0,0
mtspr srr1,r0 /* Keep things disabled for now */
mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
mflr r1
mtspr srr0,r1
mtspr SPRN_SRR0,r1
rfi
#endif /* CONFIG_440 */
@ -627,12 +627,12 @@ _start:
/*----------------------------------------------------------------*/
li r0,0x0000
lis r1,0xffff
mtspr dec,r0 /* prevent dec exceptions */
mtspr tbl,r0 /* prevent fit & wdt exceptions */
mtspr tbu,r0
mtspr tsr,r1 /* clear all timer exception status */
mtspr tcr,r0 /* disable all */
mtspr esr,r0 /* clear exception syndrome register */
mtspr SPRN_DEC,r0 /* prevent dec exceptions */
mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
mtspr SPRN_TBWU,r0
mtspr SPRN_TSR,r1 /* clear all timer exception status */
mtspr SPRN_TCR,r0 /* disable all */
mtspr SPRN_ESR,r0 /* clear exception syndrome register */
mtxer r0 /* clear integer exception register */
/*----------------------------------------------------------------*/
@ -643,10 +643,10 @@ _start:
#if defined(CONFIG_SYS_INIT_DBCR)
lis r1,0xffff
ori r1,r1,0xffff
mtspr dbsr,r1 /* Clear all status bits */
mtspr SPRN_DBSR,r1 /* Clear all status bits */
lis r0,CONFIG_SYS_INIT_DBCR@h
ori r0,r0,CONFIG_SYS_INIT_DBCR@l
mtspr dbcr0,r0
mtspr SPRN_DBCR0,r0
isync
#endif
@ -685,17 +685,17 @@ _start:
/* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
lis r1,0x0201
ori r1,r1,0xf808
mtspr dvlim,r1
mtspr SPRN_DVLIM,r1
lis r1,0x0808
ori r1,r1,0x0808
mtspr dnv0,r1
mtspr dnv1,r1
mtspr dnv2,r1
mtspr dnv3,r1
mtspr dtv0,r1
mtspr dtv1,r1
mtspr dtv2,r1
mtspr dtv3,r1
mtspr SPRN_DNV0,r1
mtspr SPRN_DNV1,r1
mtspr SPRN_DNV2,r1
mtspr SPRN_DNV3,r1
mtspr SPRN_DTV0,r1
mtspr SPRN_DTV1,r1
mtspr SPRN_DTV2,r1
mtspr SPRN_DTV3,r1
msync
isync
#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
@ -814,7 +814,7 @@ _start:
/* Set up some machine state registers. */
/*----------------------------------------------------------------------- */
addi r0,r0,0x0000 /* initialize r0 to zero */
mtspr esr,r0 /* clear Exception Syndrome Reg */
mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
mttcr r0 /* timer control register */
mtexier r0 /* disable all interrupts */
addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
@ -924,7 +924,7 @@ _start:
/*----------------------------------------------------------------------- */
addi r4,r0,0x0000
#if !defined(CONFIG_405EX)
mtspr sgr,r4
mtspr SPRN_SGR,r4
#else
/*
* On 405EX, completely clearing the SGR leads to PPC hangup
@ -933,9 +933,9 @@ _start:
*/
lis r3,0x0000
ori r3,r3,0x7FFC
mtspr sgr,r3
mtspr SPRN_SGR,r3
#endif
mtspr dcwr,r4
mtspr SPRN_DCWR,r4
mtesr r4 /* clear Exception Syndrome Reg */
mttcr r4 /* clear Timer Control Reg */
mtxer r4 /* clear Fixed-Point Exception Reg */
@ -1271,8 +1271,8 @@ crit_return:
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr csrr0,r2
mtspr csrr1,r0
mtspr SPRN_CSRR0,r2
mtspr SPRN_CSRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
@ -1302,8 +1302,8 @@ mck_return:
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr mcsrr0,r2
mtspr mcsrr1,r0
mtspr SPRN_MCSRR0,r2
mtspr SPRN_MCSRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
@ -1453,17 +1453,17 @@ relocate_code:
/* set TFLOOR/NFLOOR to 0 again */
lis r6,0x0001
ori r6,r6,0xf800
mtspr dvlim,r6
mtspr SPRN_DVLIM,r6
lis r6,0x0000
ori r6,r6,0x0000
mtspr dnv0,r6
mtspr dnv1,r6
mtspr dnv2,r6
mtspr dnv3,r6
mtspr dtv0,r6
mtspr dtv1,r6
mtspr dtv2,r6
mtspr dtv3,r6
mtspr SPRN_DNV0,r6
mtspr SPRN_DNV1,r6
mtspr SPRN_DNV2,r6
mtspr SPRN_DNV3,r6
mtspr SPRN_DTV0,r6
mtspr SPRN_DTV1,r6
mtspr SPRN_DTV2,r6
mtspr SPRN_DTV3,r6
msync
isync
#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
@ -1483,8 +1483,8 @@ relocate_code:
isync
/* Clear all potential pending exceptions */
mfspr r1,mcsr
mtspr mcsr,r1
mfspr r1,SPRN_MCSR
mtspr SPRN_MCSR,r1
#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
#else
@ -1728,9 +1728,9 @@ trap_init:
__440_msr_set:
addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
mtspr srr1,r7
mtspr SPRN_SRR1,r7
mflr r7
mtspr srr0,r7
mtspr SPRN_SRR0,r7
rfi
__440_msr_continue:
#endif
@ -2064,7 +2064,7 @@ pll_wait:
* Not sure if this is needed...
*/
addis r3,0,0x1000
mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
/* execution will continue from the poweron */
/* vector of 0xfffffffc */
#endif /* CONFIG_405EP */

46
include/asm-ppc/processor.h
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@ -96,6 +96,10 @@
#define CONFIG_BOOKE
#endif
#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
#ifdef CONFIG_BOOKE
#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
#endif
#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
@ -166,6 +170,9 @@
#define SPRN_DBSR 0x3F0 /* Debug Status Register */
#else
#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
#ifdef CONFIG_BOOKE
#define SPRN_DBDR 0x3f3 /* Debug Data Register */
#endif
#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
@ -173,6 +180,10 @@
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define DCCR_NOCACHE 0 /* Noncacheable */
#define DCCR_CACHE 1 /* Cacheable */
#ifndef CONFIG_BOOKE
#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
#endif
#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
#define DCWR_COPY 0 /* Copy-back */
@ -184,7 +195,20 @@
#endif /* CONFIG_BOOKE */
#define SPRN_DEC 0x016 /* Decrement Register */
#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
#ifdef CONFIG_BOOKE
#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
#endif
#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
#ifdef CONFIG_BOOKE
#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
#endif
#define SPRN_EAR 0x11A /* External Address Register */
#ifndef CONFIG_BOOKE
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
@ -269,16 +293,34 @@
#define ICCR_NOCACHE 0 /* Noncacheable */
#define ICCR_CACHE 1 /* Cacheable */
#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
#ifdef CONFIG_BOOKE
#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
#endif
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#ifdef CONFIG_BOOKE
#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
#endif
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
#define SPRN_MBAR 0x137 /* System memory base address */
#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
#ifdef CONFIG_BOOKE
#define SPRN_MMUCR 0x3b2 /* MMU Control Register */
#endif
#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
@ -297,6 +339,9 @@
#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
#define SPRN_PVR 0x11F /* Processor Version Register */
#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
#ifdef CONFIG_BOOKE
#define SPRN_RSTCFG 0x39b /* Reset Configuration */
#endif
#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
@ -315,6 +360,7 @@
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#ifdef CONFIG_BOOKE
#define SPRN_SVR 0x3FF /* System Version Register */
#else

55
include/ppc405.h
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@ -32,61 +32,6 @@
#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */
#endif
/*--------------------------------------------------------------------- */
/* Special Purpose Registers */
/*--------------------------------------------------------------------- */
#define srr2 0x3de /* save/restore register 2 */
#define srr3 0x3df /* save/restore register 3 */
/*
* 405 does not really have CSRR0/1 but SRR2/3 are used during critical
* exception for the exact same purposes - let's alias them and have a
* common handling in crit_return() and CRIT_EXCEPTION
*/
#define csrr0 srr2
#define csrr1 srr3
#define dbsr 0x3f0 /* debug status register */
#define dbcr0 0x3f2 /* debug control register 0 */
#define dbcr1 0x3bd /* debug control register 1 */
#define iac1 0x3f4 /* instruction address comparator 1 */
#define iac2 0x3f5 /* instruction address comparator 2 */
#define iac3 0x3b4 /* instruction address comparator 3 */
#define iac4 0x3b5 /* instruction address comparator 4 */
#define dac1 0x3f6 /* data address comparator 1 */
#define dac2 0x3f7 /* data address comparator 2 */
#define dccr 0x3fa /* data cache control register */
#define iccr 0x3fb /* instruction cache control register */
#define esr 0x3d4 /* execption syndrome register */
#define dear 0x3d5 /* data exeption address register */
#define evpr 0x3d6 /* exeption vector prefix register */
#define tsr 0x3d8 /* timer status register */
#define tcr 0x3da /* timer control register */
#define pit 0x3db /* programmable interval timer */
#define sgr 0x3b9 /* storage guarded reg */
#define dcwr 0x3ba /* data cache write-thru reg*/
#define sler 0x3bb /* storage little-endian reg */
#define cdbcr 0x3d7 /* cache debug cntrl reg */
#define icdbdr 0x3d3 /* instr cache dbug data reg*/
#define ccr0 0x3b3 /* core configuration register */
#define dvc1 0x3b6 /* data value compare register 1 */
#define dvc2 0x3b7 /* data value compare register 2 */
#define pid 0x3b1 /* process ID */
#define su0r 0x3bc /* storage user-defined register 0 */
#define zpr 0x3b0 /* zone protection regsiter */
#define tbl 0x11c /* time base lower - privileged write */
#define tbu 0x11d /* time base upper - privileged write */
#define sprg4r 0x104 /* Special purpose general 4 - read only */
#define sprg5r 0x105 /* Special purpose general 5 - read only */
#define sprg6r 0x106 /* Special purpose general 6 - read only */
#define sprg7r 0x107 /* Special purpose general 7 - read only */
#define sprg4w 0x114 /* Special purpose general 4 - write only */
#define sprg5w 0x115 /* Special purpose general 5 - write only */
#define sprg6w 0x116 /* Special purpose general 6 - write only */
#define sprg7w 0x117 /* Special purpose general 7 - write only */
/******************************************************************************
* Special for PPC405GP
******************************************************************************/

93
include/ppc440.h
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@ -48,99 +48,6 @@
#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
/*--------------------------------------------------------------------- */
/* Special Purpose Registers */
/*--------------------------------------------------------------------- */
#define xer_reg 0x001
#define lr_reg 0x008
#define dec 0x016 /* decrementer */
#define srr0 0x01a /* save/restore register 0 */
#define srr1 0x01b /* save/restore register 1 */
#define pid 0x030 /* process id */
#define decar 0x036 /* decrementer auto-reload */
#define csrr0 0x03a /* critical save/restore register 0 */
#define csrr1 0x03b /* critical save/restore register 1 */
#define dear 0x03d /* data exception address register */
#define esr 0x03e /* exception syndrome register */
#define ivpr 0x03f /* interrupt prefix register */
#define usprg0 0x100 /* user special purpose register general 0 */
#define usprg1 0x110 /* user special purpose register general 1 */
#define tblr 0x10c /* time base lower, read only */
#define tbur 0x10d /* time base upper, read only */
#define sprg1 0x111 /* special purpose register general 1 */
#define sprg2 0x112 /* special purpose register general 2 */
#define sprg3 0x113 /* special purpose register general 3 */
#define sprg4 0x114 /* special purpose register general 4 */
#define sprg5 0x115 /* special purpose register general 5 */
#define sprg6 0x116 /* special purpose register general 6 */
#define sprg7 0x117 /* special purpose register general 7 */
#define tbl 0x11c /* time base lower (supervisor)*/
#define tbu 0x11d /* time base upper (supervisor)*/
#define pir 0x11e /* processor id register */
#define dbsr 0x130 /* debug status register */
#define dbcr0 0x134 /* debug control register 0 */
#define dbcr1 0x135 /* debug control register 1 */
#define dbcr2 0x136 /* debug control register 2 */
#define iac1 0x138 /* instruction address compare 1 */
#define iac2 0x139 /* instruction address compare 2 */
#define iac3 0x13a /* instruction address compare 3 */
#define iac4 0x13b /* instruction address compare 4 */
#define dac1 0x13c /* data address compare 1 */
#define dac2 0x13d /* data address compare 2 */
#define dvc1 0x13e /* data value compare 1 */
#define dvc2 0x13f /* data value compare 2 */
#define tsr 0x150 /* timer status register */
#define tcr 0x154 /* timer control register */
#define ivor0 0x190 /* interrupt vector offset register 0 */
#define ivor1 0x191 /* interrupt vector offset register 1 */
#define ivor2 0x192 /* interrupt vector offset register 2 */
#define ivor3 0x193 /* interrupt vector offset register 3 */
#define ivor4 0x194 /* interrupt vector offset register 4 */
#define ivor5 0x195 /* interrupt vector offset register 5 */
#define ivor6 0x196 /* interrupt vector offset register 6 */
#define ivor7 0x197 /* interrupt vector offset register 7 */
#define ivor8 0x198 /* interrupt vector offset register 8 */
#define ivor9 0x199 /* interrupt vector offset register 9 */
#define ivor10 0x19a /* interrupt vector offset register 10 */
#define ivor11 0x19b /* interrupt vector offset register 11 */
#define ivor12 0x19c /* interrupt vector offset register 12 */
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
#if defined(CONFIG_440)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
#endif
#define inv0 0x370 /* instruction cache normal victim 0 */
#define inv1 0x371 /* instruction cache normal victim 1 */
#define inv2 0x372 /* instruction cache normal victim 2 */
#define inv3 0x373 /* instruction cache normal victim 3 */
#define itv0 0x374 /* instruction cache transient victim 0 */
#define itv1 0x375 /* instruction cache transient victim 1 */
#define itv2 0x376 /* instruction cache transient victim 2 */
#define itv3 0x377 /* instruction cache transient victim 3 */
#define dnv0 0x390 /* data cache normal victim 0 */
#define dnv1 0x391 /* data cache normal victim 1 */
#define dnv2 0x392 /* data cache normal victim 2 */
#define dnv3 0x393 /* data cache normal victim 3 */
#define dtv0 0x394 /* data cache transient victim 0 */
#define dtv1 0x395 /* data cache transient victim 1 */
#define dtv2 0x396 /* data cache transient victim 2 */
#define dtv3 0x397 /* data cache transient victim 3 */
#define dvlim 0x398 /* data cache victim limit */
#define ivlim 0x399 /* instruction cache victim limit */
#define rstcfg 0x39b /* reset configuration */
#define dcdbtrl 0x39c /* data cache debug tag register low */
#define dcdbtrh 0x39d /* data cache debug tag register high */
#define icdbtrl 0x39e /* instruction cache debug tag register low */
#define icdbtrh 0x39f /* instruction cache debug tag register high */
#define mmucr 0x3b2 /* mmu control register */
#define ccr0 0x3b3 /* core configuration register 0 */
#define ccr1 0x378 /* core configuration for 440x5 only */
#define icdbdr 0x3d3 /* instruction cache debug data register */
#define dbdr 0x3f3 /* debug data register */
/******************************************************************************
* DCRs & Related
******************************************************************************/

6
post/cpu/ppc4xx/fpu.c
Unescape View File

@ -34,7 +34,7 @@
int fpu_status(void)
{
if (mfspr(ccr0) & CCR0_DAPUIB)
if (mfspr(SPRN_CCR0) & CCR0_DAPUIB)
return 0; /* Disabled */
else
return 1; /* Enabled */
@ -43,14 +43,14 @@ int fpu_status(void)
void fpu_disable(void)
{
mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB);
mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) | CCR0_DAPUIB);
mtmsr(mfmsr() & ~MSR_FP);
}
void fpu_enable(void)
{
mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~CCR0_DAPUIB);
mtmsr(mfmsr() | MSR_FP);
}

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