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@ -14,13 +14,15 @@ |
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#ifndef AT91_PMC_H |
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#define AT91_PMC_H |
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#ifdef __ASSEMBLY__ |
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#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20) |
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#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28) |
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#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c) |
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#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30) |
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#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68) |
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#ifndef __ASSEMBLY__ |
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#else |
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#include <asm/types.h> |
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@ -137,13 +139,6 @@ typedef struct at91_pmc { |
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#define AT91_PMC_IXR_PCKRDY2 0x00000400 |
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#define AT91_PMC_IXR_PCKRDY3 0x00000800 |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ |
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#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ |
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#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ |
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#endif |
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ |
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ |
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ |
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@ -159,34 +154,18 @@ typedef struct at91_pmc { |
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#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ |
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#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ |
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#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ |
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#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ |
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#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ |
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#endif |
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#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ |
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#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ |
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#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ |
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#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ |
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#endif |
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ |
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ |
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#endif |
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#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ |
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#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ |
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#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ |
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#endif |
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#define AT91_PMC_DIV (0xff << 0) /* Divider */ |
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#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ |
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#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ |
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@ -198,9 +177,6 @@ typedef struct at91_pmc { |
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#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ |
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#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ |
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#endif |
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#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ |
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#define AT91_PMC_CSS_SLOW (0 << 0) |
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#define AT91_PMC_CSS_MAIN (1 << 0) |
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@ -228,9 +204,6 @@ typedef struct at91_pmc { |
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#define AT91_PMC_PDIV_1 (0 << 12) |
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#define AT91_PMC_PDIV_2 (1 << 12) |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register */ |
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#endif |
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#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */ |
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#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */ |
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#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */ |
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@ -238,13 +211,6 @@ typedef struct at91_pmc { |
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#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */ |
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#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */ |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ |
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#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ |
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#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ |
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#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ |
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#endif |
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#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ |
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#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
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#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
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@ -255,13 +221,6 @@ typedef struct at91_pmc { |
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#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
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#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |
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#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ |
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#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ |
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#endif |
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#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ |
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#ifdef CONFIG_AT91_LEGACY |
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#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ |
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#endif /* CONFIG_AT91_LEGACY */ |
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#endif |
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