This patch adds the driver for the Amlogic Meson Successive Approximation Register (SAR) A/D Converter based on the Linux IIO driver thanks to the great work of Martin Blumenstingl. The driver has been adapted to U-Boot and the ADC UClass. This patch depends on the regmap "regmap: add regmap_update_bits() helper" patch and has been tested using the newly introducted "adc" CLI command in the "cmd: add ADC cli commands" patch. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>lime2-spi
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
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* Copyright (C) 2018 BayLibre, SAS |
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* Author: Neil Armstrong <narmstrong@baylibre.com> |
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* |
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* Amlogic Meson Successive Approximation Register (SAR) A/D Converter |
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*/ |
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#include <common.h> |
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#include <adc.h> |
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#include <clk.h> |
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#include <dm.h> |
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#include <regmap.h> |
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#include <errno.h> |
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#include <asm/io.h> |
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#include <linux/math64.h> |
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#include <linux/bitfield.h> |
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#define MESON_SAR_ADC_REG0 0x00 |
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#define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31) |
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#define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28) |
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#define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30) |
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#define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29) |
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#define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28) |
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#define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27) |
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#define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26) |
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#define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21) |
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#define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19) |
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#define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16) |
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#define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15) |
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#define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14) |
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#define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12) |
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#define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10) |
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#define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9) |
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#define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4) |
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#define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3) |
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#define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2) |
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#define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1) |
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#define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0) |
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#define MESON_SAR_ADC_CHAN_LIST 0x04 |
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#define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24) |
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#define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \ |
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(GENMASK(2, 0) << ((_chan) * 3)) |
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#define MESON_SAR_ADC_AVG_CNTL 0x08 |
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#define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \ |
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(16 + ((_chan) * 2)) |
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#define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \ |
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(GENMASK(17, 16) << ((_chan) * 2)) |
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#define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \ |
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(0 + ((_chan) * 2)) |
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#define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \ |
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(GENMASK(1, 0) << ((_chan) * 2)) |
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#define MESON_SAR_ADC_REG3 0x0c |
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#define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31) |
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#define MESON_SAR_ADC_REG3_CLK_EN BIT(30) |
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#define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28) |
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#define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27) |
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#define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26) |
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#define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23) |
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#define MESON_SAR_ADC_REG3_DETECT_EN BIT(22) |
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#define MESON_SAR_ADC_REG3_ADC_EN BIT(21) |
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#define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) |
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#define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) |
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#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 |
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#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5 |
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#define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) |
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#define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0) |
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#define MESON_SAR_ADC_DELAY 0x10 |
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#define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24) |
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#define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15) |
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#define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14) |
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#define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16) |
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#define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8) |
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#define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0) |
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#define MESON_SAR_ADC_LAST_RD 0x14 |
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#define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16) |
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#define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0) |
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#define MESON_SAR_ADC_FIFO_RD 0x18 |
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#define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12) |
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#define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0) |
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#define MESON_SAR_ADC_AUX_SW 0x1c |
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#define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \ |
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(8 + (((_chan) - 2) * 3)) |
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#define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6) |
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#define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5) |
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#define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4) |
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#define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3) |
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#define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2) |
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#define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1) |
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#define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0) |
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#define MESON_SAR_ADC_CHAN_10_SW 0x20 |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1) |
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#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24 |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1) |
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#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0) |
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#define MESON_SAR_ADC_DELTA_10 0x28 |
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#define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27) |
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#define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26) |
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#define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16) |
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#define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15) |
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#define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11 |
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#define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11) |
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#define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10) |
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#define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0) |
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/*
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* NOTE: registers from here are undocumented (the vendor Linux kernel driver |
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* and u-boot source served as reference). These only seem to be relevant on |
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* GXBB and newer. |
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*/ |
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#define MESON_SAR_ADC_REG11 0x2c |
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#define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13) |
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#define MESON_SAR_ADC_REG13 0x34 |
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#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8) |
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#define MESON_SAR_ADC_MAX_FIFO_SIZE 32 |
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#define MESON_SAR_ADC_TIMEOUT 100 /* ms */ |
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#define NUM_CHANNELS 8 |
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#define MILLION 1000000 |
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struct meson_saradc_data { |
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int num_bits; |
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}; |
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struct meson_saradc_priv { |
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const struct meson_saradc_data *data; |
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struct regmap *regmap; |
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struct clk core_clk; |
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struct clk adc_clk; |
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bool initialized; |
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int active_channel; |
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int calibbias; |
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int calibscale; |
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}; |
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static unsigned int |
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meson_saradc_get_fifo_count(struct meson_saradc_priv *priv) |
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{ |
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u32 regval; |
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regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); |
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return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); |
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} |
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static int meson_saradc_lock(struct meson_saradc_priv *priv) |
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{ |
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uint val, timeout = 10000; |
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/* prevent BL30 from using the SAR ADC while we are using it */ |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, |
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MESON_SAR_ADC_DELAY_KERNEL_BUSY, |
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MESON_SAR_ADC_DELAY_KERNEL_BUSY); |
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/*
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* wait until BL30 releases it's lock (so we can use the SAR ADC) |
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*/ |
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do { |
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udelay(1); |
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regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); |
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} while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); |
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if (timeout < 0) { |
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printf("Timeout while waiting for BL30 unlock\n"); |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static void meson_saradc_unlock(struct meson_saradc_priv *priv) |
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{ |
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/* allow BL30 to use the SAR ADC again */ |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, |
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MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0); |
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} |
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static void meson_saradc_clear_fifo(struct meson_saradc_priv *priv) |
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{ |
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unsigned int count, tmp; |
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for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) { |
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if (!meson_saradc_get_fifo_count(priv)) |
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break; |
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regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp); |
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} |
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} |
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static int meson_saradc_calib_val(struct meson_saradc_priv *priv, int val) |
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{ |
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int tmp; |
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/* use val_calib = scale * val_raw + offset calibration function */ |
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tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; |
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return clamp(tmp, 0, (1 << priv->data->num_bits) - 1); |
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} |
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static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv) |
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{ |
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uint regval, timeout = 10000; |
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/*
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* NOTE: we need a small delay before reading the status, otherwise |
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* the sample engine may not have started internally (which would |
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* seem to us that sampling is already finished). |
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*/ |
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do { |
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udelay(1); |
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regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); |
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} while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); |
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if (timeout < 0) |
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return -ETIMEDOUT; |
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return 0; |
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} |
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static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv, |
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unsigned int channel, uint *val) |
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{ |
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uint regval, fifo_chan, fifo_val, count; |
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int ret; |
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ret = meson_saradc_wait_busy_clear(priv); |
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if (ret) |
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return ret; |
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count = meson_saradc_get_fifo_count(priv); |
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if (count != 1) { |
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printf("ADC FIFO has %d element(s) instead of one\n", count); |
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return -EINVAL; |
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} |
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regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); |
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fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); |
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if (fifo_chan != channel) { |
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printf("ADC FIFO entry belongs to channel %d instead of %d\n", |
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fifo_chan, channel); |
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return -EINVAL; |
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} |
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fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval); |
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fifo_val &= GENMASK(priv->data->num_bits - 1, 0); |
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*val = meson_saradc_calib_val(priv, fifo_val); |
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return 0; |
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} |
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static void meson_saradc_start_sample_engine(struct meson_saradc_priv *priv) |
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{ |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, |
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MESON_SAR_ADC_REG0_FIFO_IRQ_EN, |
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MESON_SAR_ADC_REG0_FIFO_IRQ_EN); |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, |
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MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, |
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MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE); |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, |
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MESON_SAR_ADC_REG0_SAMPLING_START, |
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MESON_SAR_ADC_REG0_SAMPLING_START); |
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} |
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static void meson_saradc_stop_sample_engine(struct meson_saradc_priv *priv) |
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{ |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, |
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MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0); |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, |
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MESON_SAR_ADC_REG0_SAMPLING_STOP, |
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MESON_SAR_ADC_REG0_SAMPLING_STOP); |
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/* wait until all modules are stopped */ |
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meson_saradc_wait_busy_clear(priv); |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, |
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MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0); |
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} |
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enum meson_saradc_avg_mode { |
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NO_AVERAGING = 0x0, |
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MEAN_AVERAGING = 0x1, |
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MEDIAN_AVERAGING = 0x2, |
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}; |
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enum meson_saradc_num_samples { |
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ONE_SAMPLE = 0x0, |
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TWO_SAMPLES = 0x1, |
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FOUR_SAMPLES = 0x2, |
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EIGHT_SAMPLES = 0x3, |
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}; |
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static void meson_saradc_set_averaging(struct meson_saradc_priv *priv, |
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unsigned int channel, |
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enum meson_saradc_avg_mode mode, |
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enum meson_saradc_num_samples samples) |
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{ |
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int val; |
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val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel); |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, |
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MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel), |
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val); |
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val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel); |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, |
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MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val); |
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} |
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static void meson_saradc_enable_channel(struct meson_saradc_priv *priv, |
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unsigned int channel) |
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{ |
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uint regval; |
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/*
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* the SAR ADC engine allows sampling multiple channels at the same |
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* time. to keep it simple we're only working with one *internal* |
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* channel, which starts counting at index 0 (which means: count = 1). |
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*/ |
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regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0); |
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, |
||||
MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval); |
||||
|
||||
/* map channel index 0 to the channel which we want to read */ |
||||
regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, |
||||
MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval); |
||||
|
||||
regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, |
||||
channel); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, |
||||
MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, |
||||
regval); |
||||
|
||||
regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, |
||||
channel); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, |
||||
MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, |
||||
regval); |
||||
|
||||
if (channel == 6) |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, |
||||
MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0); |
||||
} |
||||
|
||||
static int meson_saradc_get_sample(struct meson_saradc_priv *priv, |
||||
int chan, uint *val) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = meson_saradc_lock(priv); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/* clear the FIFO to make sure we're not reading old values */ |
||||
meson_saradc_clear_fifo(priv); |
||||
|
||||
meson_saradc_set_averaging(priv, chan, MEAN_AVERAGING, EIGHT_SAMPLES); |
||||
|
||||
meson_saradc_enable_channel(priv, chan); |
||||
|
||||
meson_saradc_start_sample_engine(priv); |
||||
ret = meson_saradc_read_raw_sample(priv, chan, val); |
||||
meson_saradc_stop_sample_engine(priv); |
||||
|
||||
meson_saradc_unlock(priv); |
||||
|
||||
if (ret) { |
||||
printf("failed to read sample for channel %d: %d\n", |
||||
chan, ret); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int meson_saradc_channel_data(struct udevice *dev, int channel, |
||||
unsigned int *data) |
||||
{ |
||||
struct meson_saradc_priv *priv = dev_get_priv(dev); |
||||
|
||||
if (channel != priv->active_channel) { |
||||
pr_err("Requested channel is not active!"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
return meson_saradc_get_sample(priv, channel, data); |
||||
} |
||||
|
||||
enum meson_saradc_chan7_mux_sel { |
||||
CHAN7_MUX_VSS = 0x0, |
||||
CHAN7_MUX_VDD_DIV4 = 0x1, |
||||
CHAN7_MUX_VDD_DIV2 = 0x2, |
||||
CHAN7_MUX_VDD_MUL3_DIV4 = 0x3, |
||||
CHAN7_MUX_VDD = 0x4, |
||||
CHAN7_MUX_CH7_INPUT = 0x7, |
||||
}; |
||||
|
||||
static void meson_saradc_set_chan7_mux(struct meson_saradc_priv *priv, |
||||
enum meson_saradc_chan7_mux_sel sel) |
||||
{ |
||||
u32 regval; |
||||
|
||||
regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, |
||||
MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); |
||||
|
||||
udelay(20); |
||||
} |
||||
|
||||
static int meson_saradc_calib(struct meson_saradc_priv *priv) |
||||
{ |
||||
uint nominal0, nominal1, value0, value1; |
||||
int ret; |
||||
|
||||
/* use points 25% and 75% for calibration */ |
||||
nominal0 = (1 << priv->data->num_bits) / 4; |
||||
nominal1 = (1 << priv->data->num_bits) * 3 / 4; |
||||
|
||||
meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_DIV4); |
||||
udelay(20); |
||||
ret = meson_saradc_get_sample(priv, 7, &value0); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_MUL3_DIV4); |
||||
udelay(20); |
||||
ret = meson_saradc_get_sample(priv, 7, &value1); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
if (value1 <= value0) { |
||||
ret = -EINVAL; |
||||
goto out; |
||||
} |
||||
|
||||
priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION, |
||||
value1 - value0); |
||||
priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale, |
||||
MILLION); |
||||
ret = 0; |
||||
out: |
||||
meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int meson_saradc_init(struct meson_saradc_priv *priv) |
||||
{ |
||||
uint regval; |
||||
int ret, i; |
||||
|
||||
priv->calibscale = MILLION; |
||||
|
||||
/*
|
||||
* make sure we start at CH7 input since the other muxes are only used |
||||
* for internal calibration. |
||||
*/ |
||||
meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT); |
||||
|
||||
/*
|
||||
* leave sampling delay and the input clocks as configured by |
||||
* BL30 to make sure BL30 gets the values it expects when |
||||
* reading the temperature sensor. |
||||
*/ |
||||
regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); |
||||
if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) |
||||
return 0; |
||||
|
||||
meson_saradc_stop_sample_engine(priv); |
||||
|
||||
/* update the channel 6 MUX to select the temperature sensor */ |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, |
||||
MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, |
||||
MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL); |
||||
|
||||
/* disable all channels by default */ |
||||
regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); |
||||
|
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, |
||||
MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, |
||||
MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY, |
||||
MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY); |
||||
|
||||
/* delay between two samples = (10+1) * 1uS */ |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, |
||||
MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, |
||||
FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, |
||||
10)); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, |
||||
MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, |
||||
FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, |
||||
0)); |
||||
|
||||
/* delay between two samples = (10+1) * 1uS */ |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, |
||||
MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, |
||||
FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, |
||||
10)); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, |
||||
MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, |
||||
FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, |
||||
1)); |
||||
|
||||
/*
|
||||
* set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW |
||||
* (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1) |
||||
*/ |
||||
regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, |
||||
MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, |
||||
regval); |
||||
regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, |
||||
MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, |
||||
regval); |
||||
|
||||
/*
|
||||
* set up the input channel muxes in MESON_SAR_ADC_AUX_SW |
||||
* (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable |
||||
* MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and |
||||
* MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver. |
||||
*/ |
||||
regval = 0; |
||||
for (i = 2; i <= 7; i++) |
||||
regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i); |
||||
regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW; |
||||
regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW; |
||||
regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval); |
||||
|
||||
ret = meson_saradc_lock(priv); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
#if CONFIG_IS_ENABLED(CLK) |
||||
ret = clk_enable(&priv->core_clk); |
||||
if (ret) |
||||
return ret; |
||||
#endif |
||||
|
||||
regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1); |
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, |
||||
MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); |
||||
|
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, |
||||
MESON_SAR_ADC_REG11_BANDGAP_EN, |
||||
MESON_SAR_ADC_REG11_BANDGAP_EN); |
||||
|
||||
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, |
||||
MESON_SAR_ADC_REG3_ADC_EN, |
||||
MESON_SAR_ADC_REG3_ADC_EN); |
||||
|
||||
udelay(5); |
||||
|
||||
#if CONFIG_IS_ENABLED(CLK) |
||||
ret = clk_enable(&priv->adc_clk); |
||||
if (ret) |
||||
return ret; |
||||
#endif |
||||
|
||||
meson_saradc_unlock(priv); |
||||
|
||||
ret = meson_saradc_calib(priv); |
||||
if (ret) { |
||||
printf("calibration failed\n"); |
||||
return -EIO; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int meson_saradc_start_channel(struct udevice *dev, int channel) |
||||
{ |
||||
struct meson_saradc_priv *priv = dev_get_priv(dev); |
||||
|
||||
if (channel < 0 || channel >= NUM_CHANNELS) { |
||||
printf("Requested channel is invalid!"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
if (!priv->initialized) { |
||||
int ret; |
||||
|
||||
ret = meson_saradc_init(priv); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
priv->initialized = true; |
||||
} |
||||
|
||||
priv->active_channel = channel; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int meson_saradc_stop(struct udevice *dev) |
||||
{ |
||||
struct meson_saradc_priv *priv = dev_get_priv(dev); |
||||
|
||||
priv->active_channel = -1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int meson_saradc_probe(struct udevice *dev) |
||||
{ |
||||
struct meson_saradc_priv *priv = dev_get_priv(dev); |
||||
int ret; |
||||
|
||||
ret = regmap_init_mem(dev, &priv->regmap); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
#if CONFIG_IS_ENABLED(CLK) |
||||
ret = clk_get_by_name(dev, "core", &priv->core_clk); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = clk_get_by_name(dev, "adc_clk", &priv->adc_clk); |
||||
if (ret) |
||||
return ret; |
||||
#endif |
||||
|
||||
priv->active_channel = -1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int meson_saradc_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); |
||||
struct meson_saradc_priv *priv = dev_get_priv(dev); |
||||
|
||||
priv->data = (struct meson_saradc_data *)dev_get_driver_data(dev); |
||||
|
||||
uc_pdata->data_mask = GENMASK(priv->data->num_bits - 1, 0); |
||||
uc_pdata->data_format = ADC_DATA_FORMAT_BIN; |
||||
uc_pdata->data_timeout_us = MESON_SAR_ADC_TIMEOUT * 1000; |
||||
uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct adc_ops meson_saradc_ops = { |
||||
.start_channel = meson_saradc_start_channel, |
||||
.channel_data = meson_saradc_channel_data, |
||||
.stop = meson_saradc_stop, |
||||
}; |
||||
|
||||
static const struct meson_saradc_data gxbb_saradc_data = { |
||||
.num_bits = 10, |
||||
}; |
||||
|
||||
static const struct meson_saradc_data gxl_saradc_data = { |
||||
.num_bits = 12, |
||||
}; |
||||
|
||||
static const struct udevice_id meson_saradc_ids[] = { |
||||
{ .compatible = "amlogic,meson-gxbb-saradc", |
||||
.data = (ulong)&gxbb_saradc_data }, |
||||
{ .compatible = "amlogic,meson-gxl-saradc", |
||||
.data = (ulong)&gxl_saradc_data }, |
||||
{ .compatible = "amlogic,meson-gxm-saradc", |
||||
.data = (ulong)&gxl_saradc_data }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(meson_saradc) = { |
||||
.name = "meson_saradc", |
||||
.id = UCLASS_ADC, |
||||
.of_match = meson_saradc_ids, |
||||
.ops = &meson_saradc_ops, |
||||
.probe = meson_saradc_probe, |
||||
.ofdata_to_platdata = meson_saradc_ofdata_to_platdata, |
||||
.priv_auto_alloc_size = sizeof(struct meson_saradc_priv), |
||||
}; |
Loading…
Reference in new issue