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@ -141,23 +141,67 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { |
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MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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iomux_v3_cfg_t const usdhc4_pads[] = { |
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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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return 1; |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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int ret; |
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if (cfg->esdhc_base == USDHC3_BASE_ADDR) |
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ret = 1; |
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else { |
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gpio_direction_input(IMX_GPIO_NR(1, 4)); |
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ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); |
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} |
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return ret; |
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} |
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struct fsl_esdhc_cfg usdhc_cfg[] = { |
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struct fsl_esdhc_cfg usdhc_cfg[2] = { |
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{USDHC3_BASE_ADDR}, |
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{USDHC4_BASE_ADDR}, |
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}; |
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int board_mmc_init(bd_t *bis) |
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{ |
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s32 status = 0; |
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u32 index = 0; |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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usdhc_cfg[0].max_bus_width = 8; |
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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usdhc_cfg[0].max_bus_width = 8; |
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usdhc_cfg[1].max_bus_width = 4; |
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for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { |
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switch (index) { |
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case 0: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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break; |
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case 1: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
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break; |
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default: |
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printf("Warning: you configured more USDHC controllers" |
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"(%d) then supported by the board (%d)\n", |
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index + 1, CONFIG_SYS_FSL_USDHC_NUM); |
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return status; |
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} |
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status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); |
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} |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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return status; |
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} |
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
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