- ATF handoff - DT syncups - gem: Use wait_for_bit(), add simple clk support - Simple clk driver for ZynqMP - Other small changes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlh18E8ACgkQykllyylKDCHM3wCeKQNF2ky4r3uTrreDdGJhdDqF Oe4AnRwSIq1fSbjxiA8ph4mgidfTdpXG =wjkD -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2017.03' of git://www.denx.de/git/u-boot-microblaze Xilinx changes for v2017.03 - ATF handoff - DT syncups - gem: Use wait_for_bit(), add simple clk support - Simple clk driver for ZynqMP - Other small changesmaster
Tom Rini
8 years ago
commit
5b30997fd2
@ -0,0 +1,87 @@ |
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/*
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* Copyright 2016 - 2017 Xilinx, Inc. |
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* |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/sys_proto.h> |
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|
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/*
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* atfhandoffparams |
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* Parameter bitfield encoding |
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* ----------------------------------------------------------------------------- |
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* Exec State 0 0 -> Aarch64, 1-> Aarch32 |
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* endianness 1 0 -> LE, 1 -> BE |
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* secure (TZ) 2 0 -> Non secure, 1 -> secure |
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* EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3 |
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* CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3 |
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*/ |
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#define FSBL_FLAGS_ESTATE_SHIFT 0 |
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#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT) |
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#define FSBL_FLAGS_ESTATE_A64 0 |
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#define FSBL_FLAGS_ESTATE_A32 1 |
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#define FSBL_FLAGS_ENDIAN_SHIFT 1 |
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#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT) |
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#define FSBL_FLAGS_ENDIAN_LE 0 |
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#define FSBL_FLAGS_ENDIAN_BE 1 |
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#define FSBL_FLAGS_TZ_SHIFT 2 |
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#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT) |
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#define FSBL_FLAGS_NON_SECURE 0 |
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#define FSBL_FLAGS_SECURE 1 |
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#define FSBL_FLAGS_EL_SHIFT 3 |
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#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT) |
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#define FSBL_FLAGS_EL0 0 |
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#define FSBL_FLAGS_EL1 1 |
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#define FSBL_FLAGS_EL2 2 |
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#define FSBL_FLAGS_EL3 3 |
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#define FSBL_FLAGS_CPU_SHIFT 5 |
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#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT) |
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#define FSBL_FLAGS_A53_0 0 |
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#define FSBL_FLAGS_A53_1 1 |
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#define FSBL_FLAGS_A53_2 2 |
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#define FSBL_FLAGS_A53_3 3 |
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#define FSBL_MAX_PARTITIONS 8 |
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/* Structure corresponding to each partition entry */ |
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struct xfsbl_partition { |
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uint64_t entry_point; |
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uint64_t flags; |
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}; |
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/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */ |
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struct xfsbl_atf_handoff_params { |
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uint8_t magic[4]; |
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uint32_t num_entries; |
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struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; |
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}; |
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#ifdef CONFIG_SPL_OS_BOOT |
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void handoff_setup(void) |
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{ |
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struct xfsbl_atf_handoff_params *atfhandoffparams; |
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atfhandoffparams = (void *)CONFIG_SPL_TEXT_BASE; |
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atfhandoffparams->magic[0] = 'X'; |
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atfhandoffparams->magic[1] = 'L'; |
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atfhandoffparams->magic[2] = 'N'; |
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atfhandoffparams->magic[3] = 'X'; |
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atfhandoffparams->num_entries = 1; |
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atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE; |
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atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 << |
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FSBL_FLAGS_EL_SHIFT; |
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writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6); |
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} |
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#endif |
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@ -0,0 +1,241 @@ |
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/*
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* ZynqMP clock driver |
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* |
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* Copyright (C) 2016 Xilinx, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <linux/bitops.h> |
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#include <clk-uclass.h> |
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#include <dm/device.h> |
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#include <clk.h> |
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#define ZYNQMP_GEM0_REF_CTRL 0xFF5E0050 |
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#define ZYNQMP_IOPLL_CTRL 0xFF5E0020 |
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#define ZYNQMP_RPLL_CTRL 0xFF5E0030 |
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#define ZYNQMP_DPLL_CTRL 0xFD1A002C |
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#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013 |
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#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013 |
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#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013 |
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#define ZYNQMP_SIP_SVC_MMIO_READ 0xC2000014 |
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#define ZYNQMP_DIV_MAX_VAL 0x3F |
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#define ZYNQMP_DIV1_SHFT 8 |
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#define ZYNQMP_DIV1_SHFT 8 |
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#define ZYNQMP_DIV2_SHFT 16 |
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#define ZYNQMP_DIV_MASK 0x3F |
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#define ZYNQMP_PLL_CTRL_FBDIV_MASK 0x7F |
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#define ZYNQMP_PLL_CTRL_FBDIV_SHFT 8 |
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#define ZYNQMP_GEM_REF_CTRL_SRC_MASK 0x7 |
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#define ZYNQMP_GEM0_CLK_ID 45 |
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#define ZYNQMP_GEM1_CLK_ID 46 |
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#define ZYNQMP_GEM2_CLK_ID 47 |
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#define ZYNQMP_GEM3_CLK_ID 48 |
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static unsigned long pss_ref_clk; |
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static int zynqmp_calculate_divisors(unsigned long req_rate, |
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unsigned long parent_rate, |
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u32 *div1, u32 *div2) |
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{ |
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u32 req_div = 1; |
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u32 i; |
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/*
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* calculate two divisors to get |
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* required rate and each divisor |
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* should be less than 63 |
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*/ |
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req_div = DIV_ROUND_UP(parent_rate, req_rate); |
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for (i = 1; i <= req_div; i++) { |
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if ((req_div % i) == 0) { |
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*div1 = req_div / i; |
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*div2 = i; |
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if ((*div1 < ZYNQMP_DIV_MAX_VAL) && |
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(*div2 < ZYNQMP_DIV_MAX_VAL)) |
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return 0; |
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} |
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} |
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return -1; |
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} |
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static int zynqmp_get_periph_id(unsigned long id) |
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{ |
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int periph_id; |
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switch (id) { |
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case ZYNQMP_GEM0_CLK_ID: |
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periph_id = 0; |
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break; |
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case ZYNQMP_GEM1_CLK_ID: |
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periph_id = 1; |
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break; |
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case ZYNQMP_GEM2_CLK_ID: |
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periph_id = 2; |
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break; |
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case ZYNQMP_GEM3_CLK_ID: |
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periph_id = 3; |
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break; |
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default: |
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printf("%s, Invalid clock id:%ld\n", __func__, id); |
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return -EINVAL; |
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} |
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return periph_id; |
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} |
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static int zynqmp_set_clk(unsigned long id, u32 div1, u32 div2) |
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{ |
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struct pt_regs regs; |
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ulong reg; |
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u32 mask, value; |
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id = zynqmp_get_periph_id(id); |
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if (id < 0) |
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return -EINVAL; |
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reg = (ulong)((u32 *)ZYNQMP_GEM0_REF_CTRL + id); |
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mask = (ZYNQMP_DIV_MASK << ZYNQMP_DIV1_SHFT) | |
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(ZYNQMP_DIV_MASK << ZYNQMP_DIV2_SHFT); |
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value = (div1 << ZYNQMP_DIV1_SHFT) | (div2 << ZYNQMP_DIV2_SHFT); |
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debug("%s: reg:0x%lx, mask:0x%x, value:0x%x\n", __func__, reg, mask, |
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value); |
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regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_WRITE; |
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regs.regs[1] = ((u64)mask << 32) | reg; |
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regs.regs[2] = value; |
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regs.regs[3] = 0; |
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smc_call(®s); |
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return regs.regs[0]; |
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} |
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static unsigned long zynqmp_clk_get_rate(struct clk *clk) |
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{ |
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struct pt_regs regs; |
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ulong reg; |
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unsigned long value; |
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int id; |
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id = zynqmp_get_periph_id(clk->id); |
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if (id < 0) |
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return -EINVAL; |
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reg = (ulong)((u32 *)ZYNQMP_GEM0_REF_CTRL + id); |
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regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_READ; |
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regs.regs[1] = reg; |
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regs.regs[2] = 0; |
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regs.regs[3] = 0; |
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smc_call(®s); |
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value = upper_32_bits(regs.regs[0]); |
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value &= ZYNQMP_GEM_REF_CTRL_SRC_MASK; |
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switch (value) { |
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case 0: |
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regs.regs[1] = ZYNQMP_IOPLL_CTRL; |
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break; |
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case 2: |
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regs.regs[1] = ZYNQMP_RPLL_CTRL; |
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break; |
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case 3: |
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regs.regs[1] = ZYNQMP_DPLL_CTRL; |
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break; |
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default: |
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return -EINVAL; |
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} |
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regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_READ; |
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regs.regs[2] = 0; |
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regs.regs[3] = 0; |
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smc_call(®s); |
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value = upper_32_bits(regs.regs[0]) & |
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(ZYNQMP_PLL_CTRL_FBDIV_MASK << |
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ZYNQMP_PLL_CTRL_FBDIV_SHFT); |
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value >>= ZYNQMP_PLL_CTRL_FBDIV_SHFT; |
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value *= pss_ref_clk; |
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return value; |
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} |
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static ulong zynqmp_clk_set_rate(struct clk *clk, unsigned long clk_rate) |
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{ |
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int ret; |
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u32 div1 = 0; |
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u32 div2 = 0; |
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unsigned long input_clk; |
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input_clk = zynqmp_clk_get_rate(clk); |
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if (IS_ERR_VALUE(input_clk)) { |
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dev_err(dev, "failed to get input_clk\n"); |
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return -EINVAL; |
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} |
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debug("%s: i/p CLK %ld, clk_rate:0x%ld\n", __func__, input_clk, |
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clk_rate); |
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ret = zynqmp_calculate_divisors(clk_rate, input_clk, &div1, &div2); |
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if (ret) { |
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dev_err(dev, "failed to proper divisors\n"); |
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return -EINVAL; |
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} |
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debug("%s: Div1:%d, Div2:%d\n", __func__, div1, div2); |
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ret = zynqmp_set_clk(clk->id, div1, div2); |
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if (ret) { |
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dev_err(dev, "failed to set gem clk\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int zynqmp_clk_probe(struct udevice *dev) |
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{ |
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struct clk clk; |
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int ret; |
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debug("%s\n", __func__); |
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ret = clk_get_by_name(dev, "pss_ref_clk", &clk); |
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if (ret < 0) { |
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dev_err(dev, "failed to get pss_ref_clk\n"); |
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return ret; |
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} |
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pss_ref_clk = clk_get_rate(&clk); |
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if (IS_ERR_VALUE(pss_ref_clk)) { |
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dev_err(dev, "failed to get rate pss_ref_clk\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static struct clk_ops zynqmp_clk_ops = { |
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.set_rate = zynqmp_clk_set_rate, |
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.get_rate = zynqmp_clk_get_rate, |
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}; |
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static const struct udevice_id zynqmp_clk_ids[] = { |
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{ .compatible = "xlnx,zynqmp-clkc" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(zynqmp_clk) = { |
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.name = "zynqmp-clk", |
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.id = UCLASS_CLK, |
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.of_match = zynqmp_clk_ids, |
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.probe = zynqmp_clk_probe, |
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.ops = &zynqmp_clk_ops, |
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}; |
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