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@ -111,8 +111,6 @@ |
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#define NUMMEMWORDS 8 |
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#define NUMLOOPS 64 /* memory test loops */ |
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#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */ |
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/*
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* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory |
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* region. Right now the cache should still be disabled in U-Boot because of the |
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@ -2268,39 +2266,6 @@ static void program_ecc(unsigned long *dimm_populated, |
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return; |
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} |
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#ifdef CONFIG_ECC_ERROR_RESET |
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/*
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* Check for ECC errors and reset board upon any error here |
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* |
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* On the Katmai 440SPe eval board, from time to time, the first |
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* lword write access after DDR2 initializazion with ECC checking |
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* enabled, leads to an ECC error. I couldn't find a configuration |
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* without this happening. On my board with the current setup it |
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* happens about 1 from 10 times. |
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* |
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* The ECC modules used for testing are: |
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* - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's) |
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* |
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* This has to get fixed for the Katmai and tested for the other |
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* board (440SP/440SPe) that will eventually use this code in the |
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* future. |
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* |
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* 2007-03-01, sr |
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*/ |
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static void check_ecc(void) |
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{ |
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u32 val; |
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mfsdram(SDRAM_ECCCR, val); |
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if (val != 0) { |
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printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n", |
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val, mfdcr(0x4c), mfdcr(0x4e)); |
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printf("ECC error occured, resetting board...\n"); |
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do_reset(NULL, 0, 0, NULL); |
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} |
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} |
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#endif |
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static void wait_ddr_idle(void) |
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{ |
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u32 val; |
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@ -2375,15 +2340,6 @@ static void program_ecc_addr(unsigned long start_address, |
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sync(); |
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eieio(); |
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wait_ddr_idle(); |
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#ifdef CONFIG_ECC_ERROR_RESET |
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/*
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* One write to 0 is enough to trigger this ECC error |
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* (see description above) |
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*/ |
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out_be32(0, 0x12345678); |
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check_ecc(); |
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#endif |
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} |
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} |
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#endif |
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