These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>master
Masahiro Yamada
10 years ago
committed by
Tom Rini
parent
a2ee47d5f6
commit
5d2a5ef712
@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_8xx=y |
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CONFIG_TARGET_FPS850L=y |
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@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_8xx=y |
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CONFIG_TARGET_FPS860L=y |
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@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_8xx=y |
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CONFIG_TARGET_NSCU=y |
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@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_8xx=y |
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CONFIG_TARGET_SM850=y |
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@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_8xx=y |
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CONFIG_TARGET_TK885D=y |
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@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_8xx=y |
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CONFIG_TARGET_VIRTLAB2=y |
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@ -1,413 +0,0 @@ |
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/*
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* (C) Copyright 2000-2008 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ |
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#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */ |
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#define CONFIG_SYS_TEXT_BASE 0x40000000 |
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#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
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#define CONFIG_SYS_SMC_RXBUFLEN 128 |
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#define CONFIG_SYS_MAXIDLE 10 |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_BOOTCOUNT_LIMIT |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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#define CONFIG_BOARD_TYPES 1 /* support board types */ |
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#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_8xx\0" \
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"hostname=FPS850L\0" \
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"bootfile=FPS850L/uImage\0" \
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"fdt_addr=40040000\0" \
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"kernel_addr=40060000\0" \
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"ramdisk_addr=40200000\0" \
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"u-boot=FPS850L/u-image.bin\0" \
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"load=tftp 200000 ${u-boot}\0" \
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"update=prot off 40000000 +${filesize};" \
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"era 40000000 +${filesize};" \
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"cp.b 200000 40000000 ${filesize};" \
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"sete filesize;save\0" \
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"" |
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#define CONFIG_BOOTCOMMAND "run flash_self" |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_SUBNETMASK |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_SUBNETMASK |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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#define CONFIG_BOOTP_NISDOMAIN |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_DNS |
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#define CONFIG_BOOTP_DNS2 |
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#define CONFIG_BOOTP_SEND_HOSTNAME |
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#define CONFIG_BOOTP_NTPSERVER |
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#define CONFIG_BOOTP_TIMEOFFSET |
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_ASKENV |
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#define CONFIG_CMD_DATE |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_JFFS2 |
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#define CONFIG_CMD_NFS |
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#define CONFIG_CMD_SNTP |
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#define CONFIG_NETCONSOLE |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
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#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
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/*
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* Low Level Configuration Settings |
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* (address mappings, register initial values, etc.) |
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* You should know what you are doing if you make changes here. |
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*/ |
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register |
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*/ |
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#define CONFIG_SYS_IMMR 0xFFF00000 |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_FLASH_BASE 0x40000000 |
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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/* use CFI flash driver */ |
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } |
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#define CONFIG_SYS_FLASH_EMPTY_INFO |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
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/* Address and size of Redundant Environment Sector */ |
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
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#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
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#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
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/*-----------------------------------------------------------------------
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* Dynamic MTD partition support |
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*/ |
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#define CONFIG_CMD_MTDPARTS |
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
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#define CONFIG_FLASH_CFI_MTD |
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#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" |
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#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ |
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"128k(dtb)," \
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"1664k(kernel)," \
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"2m(rootfs)," \
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"4m(data)" |
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/*-----------------------------------------------------------------------
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* Hardware Information Block |
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*/ |
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#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
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#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
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#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
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#endif |
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9 |
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* SYPCR can only be written once after reset! |
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*----------------------------------------------------------------------- |
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
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*/ |
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#if defined(CONFIG_WATCHDOG) |
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
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#else |
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
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#endif |
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6 |
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*----------------------------------------------------------------------- |
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* PCMCIA config., multi-function pin tri-state |
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*/ |
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26 |
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*----------------------------------------------------------------------- |
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* Clear Reference Interrupt Status, Timebase freezing enabled |
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*/ |
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27 |
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*----------------------------------------------------------------------- |
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*/ |
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#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31 |
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*----------------------------------------------------------------------- |
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
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*/ |
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
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*----------------------------------------------------------------------- |
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* Reset PLL lock status sticky bit, timer expired status bit and timer |
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* interrupt status bit - leave PLL multiplication factor unchanged ! |
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*/ |
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#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27 |
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*----------------------------------------------------------------------- |
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* Set clock output, timebase and RTC source and divider, |
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* power management and some other internal clocks |
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*/ |
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#define SCCR_MASK SCCR_EBDF11 |
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#define CONFIG_SYS_SCCR (SCCR_TBS | \ |
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00) |
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/*-----------------------------------------------------------------------
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* PCMCIA stuff |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
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#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
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#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
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#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
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#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
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#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
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#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
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#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
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/*-----------------------------------------------------------------------
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* |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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#define CONFIG_SYS_DER 0 |
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/*
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* Init Memory Controller: |
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* |
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* BR0/1 and OR0/1 (FLASH) |
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*/ |
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
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#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any) |
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* but not too much to meddle with FLASH accesses |
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*/ |
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#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
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#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
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/*
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* FLASH timing: |
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*/ |
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
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OR_SCY_3_CLK | OR_EHTR | OR_BI) |
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#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
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#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
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#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
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#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
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/*
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* BR2/3 and OR2/3 (SDRAM) |
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* |
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*/ |
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#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
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#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
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#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
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#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
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#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
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#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
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#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
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/*
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* Memory Periodic Timer Prescaler |
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* |
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* The Divider for PTA (refresh timer) configuration is based on an |
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* example SDRAM configuration (64 MBit, one bank). The adjustment to |
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* the number of chip selects (NCS) and the actually needed refresh |
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* rate is done by setting MPTPR. |
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* |
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* PTA is calculated from |
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* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
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* |
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* gclk CPU clock (not bus clock!) |
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* Trefresh Refresh cycle * 4 (four word bursts used) |
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* |
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* 4096 Rows from SDRAM example configuration |
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* 1000 factor s -> ms |
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* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
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* 4 Number of refresh cycles per period |
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* 64 Refresh cycle in ms per number of rows |
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* -------------------------------------------- |
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* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
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* |
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* 50 MHz => 50.000.000 / Divider = 98 |
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* 66 Mhz => 66.000.000 / Divider = 129 |
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* 80 Mhz => 80.000.000 / Divider = 156 |
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*/ |
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#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
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#define CONFIG_SYS_MAMR_PTA 98 |
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/*
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* For 16 MBit, refresh rates could be 31.3 us |
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* (= 64 ms / 2K = 125 / quad bursts). |
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* For a simpler initialization, 15.6 us is used instead. |
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* |
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* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
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* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
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*/ |
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#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
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#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
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#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
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#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
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/*
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* MAMR settings for SDRAM |
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*/ |
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/* 8 column SDRAM */ |
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#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
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/* 9 column SDRAM */ |
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#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
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/* pass open firmware flat tree */ |
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#define CONFIG_OF_LIBFDT 1 |
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#define CONFIG_OF_BOARD_SETUP 1 |
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#define CONFIG_HWCONFIG 1 |
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#endif /* __CONFIG_H */ |
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@ -1,415 +0,0 @@ |
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/*
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* (C) Copyright 2000-2008 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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|
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ |
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#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
||||
#define CONFIG_SYS_SMC_RXBUFLEN 128 |
||||
#define CONFIG_SYS_MAXIDLE 10 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"hostname=FPS860L\0" \
|
||||
"bootfile=FPS860L/uImage\0" \
|
||||
"fdt_addr=40040000\0" \
|
||||
"kernel_addr=40060000\0" \
|
||||
"ramdisk_addr=40200000\0" \
|
||||
"u-boot=FPS860L/u-image.bin\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"update=prot off 40000000 +${filesize};" \
|
||||
"era 40000000 +${filesize};" \
|
||||
"cp.b 200000 40000000 ${filesize};" \
|
||||
"sete filesize;save\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_NISDOMAIN |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_DNS |
||||
#define CONFIG_BOOTP_DNS2 |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
#define CONFIG_BOOTP_NTPSERVER |
||||
#define CONFIG_BOOTP_TIMEOFFSET |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_JFFS2 |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_SNTP |
||||
|
||||
|
||||
#define CONFIG_NETCONSOLE |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
|
||||
/* use CFI flash driver */ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } |
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
||||
|
||||
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Dynamic MTD partition support |
||||
*/ |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
||||
#define CONFIG_FLASH_CFI_MTD |
||||
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" |
||||
|
||||
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ |
||||
"128k(dtb)," \
|
||||
"1664k(kernel)," \
|
||||
"2m(rootfs)," \
|
||||
"4m(data)" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CONFIG_SYS_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: |
||||
*/ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
* |
||||
* The Divider for PTA (refresh timer) configuration is based on an |
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to |
||||
* the number of chip selects (NCS) and the actually needed refresh |
||||
* rate is done by setting MPTPR. |
||||
* |
||||
* PTA is calculated from |
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
||||
* |
||||
* gclk CPU clock (not bus clock!) |
||||
* Trefresh Refresh cycle * 4 (four word bursts used) |
||||
* |
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
* -------------------------------------------- |
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
||||
* |
||||
* 50 MHz => 50.000.000 / Divider = 98 |
||||
* 66 Mhz => 66.000.000 / Divider = 129 |
||||
* 80 Mhz => 80.000.000 / Divider = 156 |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
||||
#define CONFIG_SYS_MAMR_PTA 98 |
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us |
||||
* (= 64 ms / 2K = 125 / quad bursts). |
||||
* For a simpler initialization, 15.6 us is used instead. |
||||
* |
||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
||||
*/ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CONFIG_SCC1_ENET |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_HWCONFIG 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,463 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2008 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ |
||||
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ |
||||
#define CONFIG_NSCU 1 |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ |
||||
#define CONFIG_SYS_SMC_RXBUFLEN 128 |
||||
#define CONFIG_SYS_MAXIDLE 10 |
||||
|
||||
#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"hostname=NSCU\0" \
|
||||
"bootfile=${hostname}/uImage\0" \
|
||||
"kernel_addr=40080000\0" \
|
||||
"ramdisk_addr=40180000\0" \
|
||||
"u-boot=${hostname}/u-image.bin\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"update=prot off 40000000 +${filesize};" \
|
||||
"era 40000000 +${filesize};" \
|
||||
"cp.b 200000 40000000 ${filesize};" \
|
||||
"sete filesize;save\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_MISC_INIT_R 1 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_SNTP |
||||
|
||||
|
||||
#define CONFIG_NETCONSOLE |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history |
||||
*/ |
||||
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
|
||||
/* use CFI flash driver */ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } |
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
*/ |
||||
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/* NSCU use both slots, SLOT_A as "primary". */ |
||||
#define CONFIG_PCMCIA_SLOT_A 1 |
||||
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ |
||||
#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ |
||||
#undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE buses */ |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */ |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: |
||||
*/ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
||||
#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
||||
#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
||||
#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) |
||||
#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ |
||||
BR_PS_8 | BR_MS_UPMB | BR_V ) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
#ifdef CONFIG_ISP1362_USB |
||||
#define CONFIG_SYS_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ |
||||
#define CONFIG_SYS_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
||||
#define CONFIG_SYS_OR5_ISP1362 (CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \ |
||||
OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) |
||||
#define CONFIG_SYS_BR5_ISP1362 ((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \ |
||||
BR_PS_16 | BR_MS_GPCM | BR_V ) |
||||
#endif /* CONFIG_ISP1362_USB */ |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
* |
||||
* The Divider for PTA (refresh timer) configuration is based on an |
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to |
||||
* the number of chip selects (NCS) and the actually needed refresh |
||||
* rate is done by setting MPTPR. |
||||
* |
||||
* PTA is calculated from |
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
||||
* |
||||
* gclk CPU clock (not bus clock!) |
||||
* Trefresh Refresh cycle * 4 (four word bursts used) |
||||
* |
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
* -------------------------------------------- |
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
||||
* |
||||
* 50 MHz => 50.000.000 / Divider = 98 |
||||
* 66 Mhz => 66.000.000 / Divider = 129 |
||||
* 80 Mhz => 80.000.000 / Divider = 156 |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
||||
#define CONFIG_SYS_MAMR_PTA 98 |
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us |
||||
* (= 64 ms / 2K = 125 / quad bursts). |
||||
* For a simpler initialization, 15.6 us is used instead. |
||||
* |
||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
||||
*/ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#undef CONFIG_SCC1_ENET |
||||
#define CONFIG_FEC_ENET |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_HWCONFIG 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,351 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2008 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */ |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ |
||||
#define CONFIG_SM850 1 /*...on a MPC850 Service Module */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
||||
#define CONFIG_SYS_SMC_RXBUFLEN 128 |
||||
#define CONFIG_SYS_MAXIDLE 10 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#undef CONFIG_STATUS_LED /* Status LED not enabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DATE |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#if defined(DEBUG) |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
/* use CFI flash driver */ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } |
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
* |
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! |
||||
*/ |
||||
#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ |
||||
#define CONFIG_SYS_PLPRCR \ |
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
||||
#else |
||||
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
#endif /* TQM8xxL_80MHz */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ |
||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
#else /* up to 50 MHz we use a 1:1 clock */ |
||||
#define CONFIG_SYS_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
#endif /* TQM8xxL_80MHz */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
||||
OR_SCY_5_CLK | OR_EHTR) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
||||
#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
||||
#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
||||
#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) |
||||
#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ |
||||
BR_PS_8 | BR_MS_UPMB | BR_V ) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_HWCONFIG 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,490 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2005 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2006 |
||||
* Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ |
||||
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ |
||||
#define CONFIG_TK885D 1 /* ...in a TK885D base board */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ |
||||
#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
||||
#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ |
||||
#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ |
||||
/* (it will be used if there is no */ |
||||
/* 'cpuclk' variable with valid value) */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#define CONFIG_SYS_SMC_RXBUFLEN 128 |
||||
#define CONFIG_SYS_MAXIDLE 10 |
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"ethprime=FEC\0" \
|
||||
"ethact=FEC\0" \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"bootfile=/tftpboot/tk885d/uImage\0" \
|
||||
"u-boot=/tftpboot/tk885d/u-boot.bin\0" \
|
||||
"kernel_addr=40080000\0" \
|
||||
"ramdisk_addr=40180000\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"update=protect off 40000000 +${filesize};" \
|
||||
"erase 40000000 +${filesize};" \
|
||||
"cp.b 200000 40000000 ${filesize};" \
|
||||
"protect on 40000000 +${filesize}\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL 0x00000020 /* PB 26 */ |
||||
#define PB_SDA 0x00000010 /* PB 27 */ |
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
||||
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
|
||||
# define CONFIG_RTC_DS1337 1 |
||||
# define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ |
||||
|
||||
#define CONFIG_TIMESTAMP /* but print image timestmps */ |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PING |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ |
||||
#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive |
||||
memory test.*/ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Enable loopw command. |
||||
*/ |
||||
#define CONFIG_LOOPW |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
|
||||
/* use CFI flash driver */ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: Default value of OR0 after reset |
||||
*/ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
||||
OR_SCY_6_CLK | OR_TRLX) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
||||
#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
||||
#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
||||
#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) |
||||
#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ |
||||
BR_PS_8 | BR_MS_UPMB | BR_V ) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*
|
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
*/ |
||||
#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
||||
|
||||
/*
|
||||
* Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) |
||||
* |
||||
* CPUclock(MHz) * 31.2 |
||||
* CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 |
||||
* 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 |
||||
* |
||||
* CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us |
||||
* CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us |
||||
* CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us |
||||
* CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us |
||||
* |
||||
* Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will |
||||
* be met also in the default configuration, i.e. if environment variable |
||||
* 'cpuclk' is not set. |
||||
*/ |
||||
#define CONFIG_SYS_MAMR_PTA 128 |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler Register (MPTPR) values. |
||||
*/ |
||||
/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 |
||||
/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 10 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
/*
|
||||
* Network configuration |
||||
*/ |
||||
#define CONFIG_FEC_ENET /* enable ethernet on FEC */ |
||||
#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ |
||||
#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ |
||||
|
||||
#define CONFIG_LAST_STAGE_INIT 1 /* Have to configure PHYs for Linux */ |
||||
|
||||
/* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */ |
||||
#if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2)) |
||||
#define CONFIG_SYS_DISCOVER_PHY |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_DISCOVER_PHY |
||||
/* PHY addresses - hard wired in hardware */ |
||||
#define CONFIG_FEC1_PHY 1 |
||||
#define CONFIG_FEC2_PHY 2 |
||||
#endif |
||||
|
||||
#define CONFIG_MII_INIT 1 |
||||
|
||||
#define CONFIG_NET_RETRY_COUNT 3 |
||||
#define CONFIG_ETHPRIME "FEC" |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_HWCONFIG 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,469 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2006-2008 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
||||
#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */ |
||||
#define CONFIG_TQM8xxL 1 |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#define CONFIG_SYS_SMC_RXBUFLEN 128 |
||||
#define CONFIG_SYS_MAXIDLE 10 |
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"hostname=virtlab2\0" \
|
||||
"bootfile=virtlab2/uImage\0" \
|
||||
"fdt_addr=40040000\0" \
|
||||
"kernel_addr=40060000\0" \
|
||||
"ramdisk_addr=40200000\0" \
|
||||
"u-boot=virtlab2/u-image.bin\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"update=prot off 40000000 +${filesize};" \
|
||||
"era 40000000 +${filesize};" \
|
||||
"cp.b 200000 40000000 ${filesize};" \
|
||||
"sete filesize;save\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#if defined(CONFIG_LCD) |
||||
# undef CONFIG_STATUS_LED /* disturbs display */ |
||||
#else |
||||
# define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
#endif /* CONFIG_LCD */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_JFFS2 |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_SNTP |
||||
|
||||
#if defined(CONFIG_SPLASH_SCREEN) |
||||
#define CONFIG_CMD_BMP |
||||
#endif |
||||
|
||||
|
||||
#define CONFIG_NETCONSOLE |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
|
||||
/* use CFI flash driver */ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } |
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
||||
|
||||
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Dynamic MTD partition support |
||||
*/ |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
||||
#define CONFIG_FLASH_CFI_MTD |
||||
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" |
||||
|
||||
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ |
||||
"128k(dtb)," \
|
||||
"1664k(kernel)," \
|
||||
"2m(rootfs)," \
|
||||
"4m(data)" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
*/ |
||||
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: |
||||
*/ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
||||
#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
||||
#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
||||
#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) |
||||
#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ |
||||
BR_PS_8 | BR_MS_UPMB | BR_V ) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
* |
||||
* The Divider for PTA (refresh timer) configuration is based on an |
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to |
||||
* the number of chip selects (NCS) and the actually needed refresh |
||||
* rate is done by setting MPTPR. |
||||
* |
||||
* PTA is calculated from |
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
||||
* |
||||
* gclk CPU clock (not bus clock!) |
||||
* Trefresh Refresh cycle * 4 (four word bursts used) |
||||
* |
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
* -------------------------------------------- |
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
||||
* |
||||
* 50 MHz => 50.000.000 / Divider = 98 |
||||
* 66 Mhz => 66.000.000 / Divider = 129 |
||||
* 80 Mhz => 80.000.000 / Divider = 156 |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
||||
#define CONFIG_SYS_MAMR_PTA 98 |
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us |
||||
* (= 64 ms / 2K = 125 / quad bursts). |
||||
* For a simpler initialization, 15.6 us is used instead. |
||||
* |
||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
||||
*/ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
/* Map peripheral control registers on CS4 */ |
||||
#define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000 |
||||
#define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
||||
#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \ |
||||
OR_SCY_2_CLK) |
||||
#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) |
||||
#define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00) |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_HWCONFIG 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue