- Add support for Altera FPGA ACEX1K * Patches by Thomas Lange, 09 Oct 2003: - Endian swap ATA identity for all big endian CPUs, not just PPC - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize args to linux - add support for dbau1x00 board (MIPS32)master
parent
15647dc7fd
commit
5da627a424
@ -0,0 +1,41 @@ |
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o flash.o
|
||||
SOBJS = memsetup.o
|
||||
|
||||
$(LIB): .depend $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,53 @@ |
||||
By Thomas.Lange@corelatus.se 2003-10-06 |
||||
---------------------------------------- |
||||
DbAu1000 is a development board from AMD containing |
||||
an Alchemy AU1000 with mips32 core. |
||||
|
||||
Limitations & comments |
||||
---------------------- |
||||
I assume that you set board to BIG endian! |
||||
Little endian not tested, most probably broken. |
||||
|
||||
I named the board dbau1x00, to allow |
||||
support for all three development boards |
||||
some day ( dbau1000, dbau1100 and dbau1500 ). |
||||
|
||||
I only have a dbau1000, so all testing is limited |
||||
to this board! |
||||
|
||||
The board has two different flash banks, that can |
||||
be selected via dip switch. This makes it possible |
||||
to test new bootloaders without thrashing the YAMON |
||||
boot loader deliviered with board. |
||||
|
||||
Ethernet only supported for mac0. |
||||
|
||||
Pcmcia only supported for slot 0, only 3.3V. |
||||
|
||||
Pcmcia IDE tested with Sandisk Compact Flash and |
||||
IBM microdrive. |
||||
|
||||
################################### |
||||
######## NOTE!!!!!! ######### |
||||
################################### |
||||
If you partition a disk on another system (e.g. laptop), |
||||
all bytes will be swapped on 16bit level when using |
||||
PCMCIA!!!! |
||||
|
||||
This is probably due to an error in Au1000 chip. |
||||
|
||||
Solution: |
||||
|
||||
a) Boot via network and partition disk directly from |
||||
dbau1x00. The endian will then be correct. |
||||
|
||||
b) Partition disk on "laptop" and fill it with all files |
||||
you need. Then write a simple program that endian swaps |
||||
whole disk, |
||||
|
||||
Example: |
||||
Original "laptop" byte order: |
||||
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... |
||||
|
||||
Dbau1000 byte order will then be: |
||||
B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... |
@ -0,0 +1,32 @@ |
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
|
||||
#
|
||||
|
||||
# ROM version
|
||||
TEXT_BASE = 0xbfc00000
|
||||
|
||||
# RAM version
|
||||
#TEXT_BASE = 0x80100000
|
@ -0,0 +1,110 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Thomas.Lange@corelatus.se |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/au1x00.h> |
||||
#include <asm/mipsregs.h> |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
/* Sdram is setup by assembler code */ |
||||
/* If memory could be changed, we should return the true value here */ |
||||
return 64*1024*1024; |
||||
} |
||||
|
||||
#define BCSR_PCMCIA_PC0DRVEN 0x0010 |
||||
#define BCSR_PCMCIA_PC0RST 0x0080 |
||||
|
||||
/* In cpu/mips/cpu.c */ |
||||
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
u16 status; |
||||
volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); |
||||
volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC); |
||||
volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; |
||||
u32 proc_id; |
||||
|
||||
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ |
||||
|
||||
proc_id = read_32bit_cp0_register(CP0_PRID); |
||||
|
||||
switch(proc_id>>24){ |
||||
case 0: |
||||
puts("Board: Merlot (DbAu1000)\n"); |
||||
printf("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", |
||||
(proc_id>>8)&0xFF,proc_id&0xFF); |
||||
break; |
||||
default: |
||||
printf("Unsupported cpu %d, proc_id=0x%x\n",proc_id>>24,proc_id); |
||||
} |
||||
#ifdef CONFIG_IDE_PCMCIA |
||||
/* Enable 3.3 V on slot 0 ( VCC )
|
||||
No 5V */ |
||||
status = 4; |
||||
*pcmcia_bcsr = status; |
||||
|
||||
status |= BCSR_PCMCIA_PC0DRVEN; |
||||
*pcmcia_bcsr = status; |
||||
au_sync(); |
||||
|
||||
udelay(300*1000); |
||||
|
||||
status |= BCSR_PCMCIA_PC0RST; |
||||
*pcmcia_bcsr = status; |
||||
au_sync(); |
||||
|
||||
udelay(100*1000); |
||||
|
||||
/* PCMCIA is on a 36 bit physical address.
|
||||
We need to map it into a 32 bit addresses */ |
||||
|
||||
#if 0 |
||||
/* We dont need theese unless we run whole pcmcia package */ |
||||
write_one_tlb(20, /* index */ |
||||
0x01ffe000, /* Pagemask, 16 MB pages */ |
||||
CFG_PCMCIA_IO_BASE, /* Hi */ |
||||
0x3C000017, /* Lo0 */ |
||||
0x3C200017); /* Lo1 */ |
||||
|
||||
write_one_tlb(21, /* index */ |
||||
0x01ffe000, /* Pagemask, 16 MB pages */ |
||||
CFG_PCMCIA_ATTR_BASE, /* Hi */ |
||||
0x3D000017, /* Lo0 */ |
||||
0x3D200017); /* Lo1 */ |
||||
#endif |
||||
write_one_tlb(22, /* index */ |
||||
0x01ffe000, /* Pagemask, 16 MB pages */ |
||||
CFG_PCMCIA_MEM_ADDR, /* Hi */ |
||||
0x3E000017, /* Lo0 */ |
||||
0x3E200017); /* Lo1 */ |
||||
|
||||
/* Release reset of ethernet PHY chips */ |
||||
/* Always do this, because linux does not know about it */ |
||||
*phy = 3; |
||||
|
||||
return 0; |
||||
#endif |
||||
} |
@ -0,0 +1,43 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* flash_init() |
||||
* |
||||
* sets up flash_info and returns size of FLASH (bytes) |
||||
*/ |
||||
unsigned long flash_init (void) |
||||
{ |
||||
printf ("Skipping flash_init\n"); |
||||
return (0); |
||||
} |
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
printf ("write_buff not implemented\n"); |
||||
return (-1); |
||||
} |
@ -0,0 +1,118 @@ |
||||
/* Memory sub-system initialization code */ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/regdef.h> |
||||
#include <asm/au1x00.h> |
||||
|
||||
.globl memsetup
|
||||
memsetup: |
||||
/* First setup pll:s to make serial work ok */ |
||||
/* We have a 12 MHz crystal */ |
||||
li t0, SYS_CPUPLL |
||||
li t1, 0x21 /* 396 MHz */ |
||||
sw t1, 0(t0) |
||||
sync |
||||
nop |
||||
|
||||
/* Setup AUX PLL */ |
||||
li t0, SYS_AUXPLL |
||||
li t1, 8 /* 96 MHz */ |
||||
sw t1, 0(t0) /* aux pll */ |
||||
sync |
||||
|
||||
/* SDCS 0,1 SDRAM */ |
||||
li t0, MEM_SDMODE0 |
||||
li t1, 0x005522AA |
||||
sw t1, 0(t0) |
||||
|
||||
li t0, MEM_SDMODE1 |
||||
li t1, 0x005522AA |
||||
sw t1, 0(t0) |
||||
|
||||
li t0, MEM_SDADDR0 |
||||
li t1, 0x001003F8 |
||||
sw t1, 0(t0) |
||||
|
||||
|
||||
li t0, MEM_SDADDR1 |
||||
li t1, 0x001023F8 |
||||
sw t1, 0(t0) |
||||
sync |
||||
|
||||
li t0, MEM_SDREFCFG |
||||
li t1, 0x64000C24 /* Disable */ |
||||
sw t1, 0(t0) |
||||
sync |
||||
|
||||
li t0, MEM_SDPRECMD |
||||
sw zero, 0(t0) |
||||
sync |
||||
|
||||
li t0, MEM_SDAUTOREF |
||||
sw zero, 0(t0) |
||||
sync |
||||
sw zero, 0(t0) |
||||
sync |
||||
|
||||
li t0, MEM_SDREFCFG |
||||
li t1, 0x66000C24 /* Enable */ |
||||
sw t1, 0(t0) |
||||
sync |
||||
|
||||
li t0, MEM_SDWRMD0 |
||||
li t1, 0x00000033 |
||||
sw t1, 0(t0) |
||||
sync |
||||
|
||||
li t0, MEM_SDWRMD1 |
||||
li t1, 0x00000033 |
||||
sw t1, 0(t0) |
||||
sync |
||||
|
||||
/* Static memory controller */ |
||||
|
||||
/* RCE0 AMD 29LV640M MirrorBit Flash */ |
||||
li t0, MEM_STCFG0 |
||||
li t1, 0x00000003 |
||||
sw t1, 0(t0) |
||||
|
||||
li t0, MEM_STTIME0 |
||||
li t1, 0x22080b20 |
||||
sw t1, 0(t0) |
||||
|
||||
li t0, MEM_STADDR0 |
||||
li t1, 0x11E03F80 |
||||
sw t1, 0(t0) |
||||
|
||||
/* RCE1 CPLD Board Logic */ |
||||
li t0, MEM_STCFG1 |
||||
li t1, 0x00000080 |
||||
sw t1, 0(t0) |
||||
|
||||
li t0, MEM_STTIME1 |
||||
li t1, 0x22080a20 |
||||
sw t1, 0(t0) |
||||
|
||||
li t0, MEM_STADDR1 |
||||
li t1, 0x10c03f00 |
||||
sw t1, 0(t0) |
||||
|
||||
/* RCE3 PCMCIA 250ns */ |
||||
li t0, MEM_STCFG3 |
||||
li t1, 0x00000002 |
||||
sw t1, 0(t0) |
||||
|
||||
|
||||
li t0, MEM_STTIME3 |
||||
li t1, 0x280E3E07 |
||||
sw t1, 0(t0) |
||||
|
||||
li t0, MEM_STADDR3 |
||||
li t1, 0x10000000 |
||||
sw t1, 0(t0) |
||||
|
||||
sync |
||||
|
||||
j ra |
||||
nop |
@ -0,0 +1,68 @@ |
||||
/* |
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk Engineering, <wd@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* |
||||
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") |
||||
*/ |
||||
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") |
||||
OUTPUT_ARCH(mips) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.sdata : { *(.sdata) } |
||||
|
||||
_gp = ALIGN(16); |
||||
|
||||
__got_start = .; |
||||
.got : { *(.got) } |
||||
__got_end = .; |
||||
|
||||
.sdata : { *(.sdata) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
uboot_end_data = .; |
||||
num_got_entries = (__got_end - __got_start) >> 2; |
||||
|
||||
. = ALIGN(4); |
||||
.sbss : { *(.sbss) } |
||||
.bss : { *(.bss) } |
||||
uboot_end = .; |
||||
} |
@ -0,0 +1,371 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> /* core U-Boot definitions */ |
||||
#include <ACEX1K.h> /* ACEX device family */ |
||||
|
||||
#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) |
||||
|
||||
/* Define FPGA_DEBUG to get debug printf's */ |
||||
/* #define FPGA_DEBUG */ |
||||
|
||||
#ifdef FPGA_DEBUG |
||||
#define PRINTF(fmt,args...) printf (fmt ,##args) |
||||
#else |
||||
#define PRINTF(fmt,args...) |
||||
#endif |
||||
|
||||
#undef CFG_FPGA_CHECK_BUSY |
||||
#define CFG_FPGA_PROG_FEEDBACK |
||||
|
||||
/* Note: The assumption is that we cannot possibly run fast enough to
|
||||
* overrun the device (the Slave Parallel mode can free run at 50MHz). |
||||
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in |
||||
* the board config file to slow things down. |
||||
*/ |
||||
#ifndef CONFIG_FPGA_DELAY |
||||
#define CONFIG_FPGA_DELAY() |
||||
#endif |
||||
|
||||
#ifndef CFG_FPGA_WAIT |
||||
#define CFG_FPGA_WAIT 100 |
||||
#endif |
||||
|
||||
static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize ); |
||||
static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); |
||||
/* static int ACEX1K_ps_info( Altera_desc *desc ); */ |
||||
static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset ); |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/* ACEX1K Generic Implementation */ |
||||
int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
switch (desc->iface) { |
||||
case passive_serial: |
||||
PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); |
||||
ret_val = ACEX1K_ps_load (desc, buf, bsize); |
||||
break; |
||||
|
||||
/* Add new interface types here */ |
||||
|
||||
default: |
||||
printf ("%s: Unsupported interface type, %d\n", |
||||
__FUNCTION__, desc->iface); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
switch (desc->iface) { |
||||
case passive_serial: |
||||
PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); |
||||
ret_val = ACEX1K_ps_dump (desc, buf, bsize); |
||||
break; |
||||
|
||||
/* Add new interface types here */ |
||||
|
||||
default: |
||||
printf ("%s: Unsupported interface type, %d\n", |
||||
__FUNCTION__, desc->iface); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int ACEX1K_info( Altera_desc *desc ) |
||||
{ |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
|
||||
int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume a failure */ |
||||
|
||||
if (desc->family != Altera_ACEX1K) { |
||||
printf ("%s: Unsupported family type, %d\n", |
||||
__FUNCTION__, desc->family); |
||||
return FPGA_FAIL; |
||||
} else |
||||
switch (desc->iface) { |
||||
case passive_serial: |
||||
ret_val = ACEX1K_ps_reloc (desc, reloc_offset); |
||||
break; |
||||
|
||||
/* Add new interface types here */ |
||||
|
||||
default: |
||||
printf ("%s: Unsupported interface type, %d\n", |
||||
__FUNCTION__, desc->iface); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/* ACEX1K Passive Serial Generic Implementation */ |
||||
|
||||
static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume the worst */ |
||||
Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns; |
||||
int i; |
||||
|
||||
PRINTF ("%s: start with interface functions @ 0x%p\n", |
||||
__FUNCTION__, fn); |
||||
|
||||
if (fn) { |
||||
size_t bytecount = 0; |
||||
unsigned char *data = (unsigned char *) buf; |
||||
int cookie = desc->cookie; /* make a local copy */ |
||||
unsigned long ts; /* timestamp */ |
||||
|
||||
PRINTF ("%s: Function Table:\n" |
||||
"ptr:\t0x%p\n" |
||||
"struct: 0x%p\n" |
||||
"config:\t0x%p\n" |
||||
"status:\t0x%p\n" |
||||
"clk:\t0x%p\n" |
||||
"data:\t0x%p\n" |
||||
"done:\t0x%p\n\n", |
||||
__FUNCTION__, &fn, fn, fn->config, fn->status, |
||||
fn->clk, fn->data, fn->done); |
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
printf ("Loading FPGA Device %d (@ %ld)...\n", cookie, ts); |
||||
#endif |
||||
|
||||
/*
|
||||
* Run the pre configuration function if there is one. |
||||
*/ |
||||
if (*fn->pre) { |
||||
(*fn->pre) (cookie); |
||||
} |
||||
|
||||
/* Establish the initial state */ |
||||
(*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ |
||||
|
||||
udelay(2); /* T_cfg > 2us */ |
||||
|
||||
/* nSTATUS should be asserted now */ |
||||
(*fn->done) (cookie); |
||||
if ( !(*fn->status) (cookie) ) { |
||||
puts ("** nSTATUS is not asserted.\n"); |
||||
(*fn->abort) (cookie); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
(*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */ |
||||
udelay(2); /* T_cf2st1 < 4us */ |
||||
|
||||
/* Wait for nSTATUS to be released (i.e. deasserted) */ |
||||
ts = get_timer (0); /* get current time */ |
||||
do { |
||||
CONFIG_FPGA_DELAY (); |
||||
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ |
||||
puts ("** Timeout waiting for STATUS to go high.\n"); |
||||
(*fn->abort) (cookie); |
||||
return FPGA_FAIL; |
||||
} |
||||
(*fn->done) (cookie); |
||||
} while ((*fn->status) (cookie)); |
||||
|
||||
/* Get ready for the burn */ |
||||
CONFIG_FPGA_DELAY (); |
||||
|
||||
/* Load the data */ |
||||
while (bytecount < bsize) { |
||||
unsigned char val=0; |
||||
#ifdef CFG_FPGA_CHECK_CTRLC |
||||
if (ctrlc ()) { |
||||
(*fn->abort) (cookie); |
||||
return FPGA_FAIL; |
||||
} |
||||
#endif |
||||
/* Altera detects an error if INIT goes low (active)
|
||||
while DONE is low (inactive) */ |
||||
#if 0 /* not yet implemented */
|
||||
if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { |
||||
puts ("** CRC error during FPGA load.\n"); |
||||
(*fn->abort) (cookie); |
||||
return (FPGA_FAIL); |
||||
} |
||||
#endif |
||||
val = data [bytecount ++ ]; |
||||
i = 8; |
||||
do { |
||||
/* Deassert the clock */ |
||||
(*fn->clk) (FALSE, TRUE, cookie); |
||||
CONFIG_FPGA_DELAY (); |
||||
/* Write data */ |
||||
(*fn->data) ( (val & 0x01), TRUE, cookie); |
||||
CONFIG_FPGA_DELAY (); |
||||
/* Assert the clock */ |
||||
(*fn->clk) (TRUE, TRUE, cookie); |
||||
CONFIG_FPGA_DELAY (); |
||||
val >>= 1; |
||||
i --; |
||||
} while (i > 0); |
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
if (bytecount % (bsize / 40) == 0) |
||||
putc ('.'); /* let them know we are alive */ |
||||
#endif |
||||
} |
||||
|
||||
CONFIG_FPGA_DELAY (); |
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
putc ('\n'); /* terminate the dotted line */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Checking FPGA's CONF_DONE signal - correctly booted ? |
||||
*/ |
||||
|
||||
if ( ! (*fn->done) (cookie) ) { |
||||
puts ("** Booting failed! CONF_DONE is still deasserted.\n"); |
||||
(*fn->abort) (cookie); |
||||
return (FPGA_FAIL); |
||||
} |
||||
|
||||
/*
|
||||
* "DCLK must be clocked an additional 10 times fpr ACEX 1K..." |
||||
*/ |
||||
|
||||
for (i = 0; i < 12; i++) { |
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ |
||||
CONFIG_FPGA_DELAY (); |
||||
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ |
||||
} |
||||
|
||||
ret_val = FPGA_SUCCESS; |
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK |
||||
if (ret_val == FPGA_SUCCESS) { |
||||
puts ("Done.\n"); |
||||
} |
||||
else { |
||||
puts ("Fail.\n"); |
||||
} |
||||
#endif |
||||
(*fn->post) (cookie); |
||||
|
||||
} else { |
||||
printf ("%s: NULL Interface function table!\n", __FUNCTION__); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
/* Readback is only available through the Slave Parallel and */ |
||||
/* boundary-scan interfaces. */ |
||||
printf ("%s: Passive Serial Dumping is unavailable\n", |
||||
__FUNCTION__); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume the worst */ |
||||
Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn = |
||||
(Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns); |
||||
|
||||
if (fn) { |
||||
ulong addr; |
||||
|
||||
/* Get the relocated table address */ |
||||
addr = (ulong) fn + reloc_offset; |
||||
fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr; |
||||
|
||||
if (!fn_r->relocated) { |
||||
|
||||
if (memcmp (fn_r, fn, |
||||
sizeof (Altera_ACEX1K_Passive_Serial_fns)) |
||||
== 0) { |
||||
/* good copy of the table, fix the descriptor pointer */ |
||||
desc->iface_fns = fn_r; |
||||
} else { |
||||
PRINTF ("%s: Invalid function table at 0x%p\n", |
||||
__FUNCTION__, fn_r); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, |
||||
desc); |
||||
|
||||
addr = (ulong) (fn->pre) + reloc_offset; |
||||
fn_r->pre = (Altera_pre_fn) addr; |
||||
|
||||
addr = (ulong) (fn->config) + reloc_offset; |
||||
fn_r->config = (Altera_config_fn) addr; |
||||
|
||||
addr = (ulong) (fn->status) + reloc_offset; |
||||
fn_r->status = (Altera_status_fn) addr; |
||||
|
||||
addr = (ulong) (fn->done) + reloc_offset; |
||||
fn_r->done = (Altera_done_fn) addr; |
||||
|
||||
addr = (ulong) (fn->clk) + reloc_offset; |
||||
fn_r->clk = (Altera_clk_fn) addr; |
||||
|
||||
addr = (ulong) (fn->data) + reloc_offset; |
||||
fn_r->data = (Altera_data_fn) addr; |
||||
|
||||
addr = (ulong) (fn->abort) + reloc_offset; |
||||
fn_r->abort = (Altera_abort_fn) addr; |
||||
|
||||
addr = (ulong) (fn->post) + reloc_offset; |
||||
fn_r->post = (Altera_post_fn) addr; |
||||
|
||||
fn_r->relocated = TRUE; |
||||
|
||||
} else { |
||||
/* this table has already been moved */ |
||||
/* XXX - should check to see if the descriptor is correct */ |
||||
desc->iface_fns = fn_r; |
||||
} |
||||
|
||||
ret_val = FPGA_SUCCESS; |
||||
} else { |
||||
printf ("%s: NULL Interface function table!\n", __FUNCTION__); |
||||
} |
||||
|
||||
return ret_val; |
||||
|
||||
} |
||||
|
||||
#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */ |
@ -0,0 +1,216 @@ |
||||
/* Only eth0 supported for now
|
||||
* |
||||
* (C) Copyright 2003 |
||||
* Thomas.Lange@corelatus.se |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#include <config.h> |
||||
|
||||
#ifdef CONFIG_AU1X00 |
||||
|
||||
#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) |
||||
#error "PHY and MII not supported yet" |
||||
/* We just assume that we are running 100FD for now */ |
||||
/* We all use switches, right? ;-) */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_AU1000 |
||||
/* Base address differ between cpu:s */ |
||||
#define ETH0_BASE AU1000_ETH0_BASE |
||||
#define MAC0_ENABLE AU1000_MAC0_ENABLE |
||||
#else |
||||
#error "Au1100 and Au1500 not supported" |
||||
#endif |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <net.h> |
||||
#include <command.h> |
||||
#include <asm/io.h> |
||||
#include <asm/au1x00.h> |
||||
|
||||
/* Ethernet Transmit and Receive Buffers */ |
||||
#define DBUF_LENGTH 1520 |
||||
#define PKT_MAXBUF_SIZE 1518 |
||||
|
||||
static char txbuf[DBUF_LENGTH]; |
||||
|
||||
static int next_tx; |
||||
static int next_rx; |
||||
|
||||
/* 4 rx and 4 tx fifos */ |
||||
#define NO_OF_FIFOS 4 |
||||
|
||||
typedef struct{ |
||||
u32 status; |
||||
u32 addr; |
||||
u32 len; /* Only used for tx */ |
||||
u32 not_used; |
||||
} mac_fifo_t; |
||||
|
||||
mac_fifo_t mac_fifo[NO_OF_FIFOS]; |
||||
|
||||
#define MAX_WAIT 1000 |
||||
|
||||
static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){ |
||||
volatile mac_fifo_t *fifo_tx = |
||||
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); |
||||
int i; |
||||
int res; |
||||
|
||||
/* tx fifo should always be idle */ |
||||
fifo_tx[next_tx].len = length; |
||||
fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE; |
||||
au_sync(); |
||||
|
||||
udelay(1); |
||||
i=0; |
||||
while(!(fifo_tx[next_tx].addr&TX_T_DONE)){ |
||||
if(i>MAX_WAIT){ |
||||
printf("TX timeout\n"); |
||||
break; |
||||
} |
||||
udelay(1); |
||||
i++; |
||||
} |
||||
|
||||
/* Clear done bit */ |
||||
fifo_tx[next_tx].addr = 0; |
||||
fifo_tx[next_tx].len = 0; |
||||
au_sync(); |
||||
|
||||
res = fifo_tx[next_tx].status; |
||||
|
||||
next_tx++; |
||||
if(next_tx>=NO_OF_FIFOS){ |
||||
next_tx=0; |
||||
} |
||||
return(res); |
||||
} |
||||
|
||||
static int au1x00_recv(struct eth_device* dev){ |
||||
volatile mac_fifo_t *fifo_rx = |
||||
(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); |
||||
|
||||
int length; |
||||
u32 status; |
||||
|
||||
for(;;){ |
||||
if(!(fifo_rx[next_rx].addr&RX_T_DONE)){ |
||||
/* Nothing has been received */ |
||||
return(-1); |
||||
} |
||||
|
||||
status = fifo_rx[next_rx].status; |
||||
|
||||
length = status&0x3FFF; |
||||
|
||||
if(status&RX_ERROR){ |
||||
printf("Rx error 0x%x\n", status); |
||||
} |
||||
else{ |
||||
/* Pass the packet up to the protocol layers. */ |
||||
NetReceive(NetRxPackets[next_rx], length - 4); |
||||
} |
||||
|
||||
fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE; |
||||
|
||||
next_rx++; |
||||
if(next_rx>=NO_OF_FIFOS){ |
||||
next_rx=0; |
||||
} |
||||
} /* for */ |
||||
|
||||
return(0); /* Does anyone use this? */ |
||||
} |
||||
|
||||
static int au1x00_init(struct eth_device* dev, bd_t * bd){ |
||||
|
||||
volatile u32 *macen = (volatile u32*)MAC0_ENABLE; |
||||
volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL); |
||||
volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH); |
||||
volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW); |
||||
volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH); |
||||
volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW); |
||||
volatile mac_fifo_t *fifo_tx = |
||||
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); |
||||
volatile mac_fifo_t *fifo_rx = |
||||
(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); |
||||
int i; |
||||
|
||||
next_tx = 0; |
||||
next_rx = 0; |
||||
|
||||
/* We have to enable clocks before releasing reset */ |
||||
*macen = MAC_EN_CLOCK_ENABLE; |
||||
udelay(10); |
||||
|
||||
/* Enable MAC0 */ |
||||
/* We have to release reset before accessing registers */ |
||||
*macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0| |
||||
MAC_EN_RESET1|MAC_EN_RESET2; |
||||
udelay(10); |
||||
|
||||
for(i=0;i<NO_OF_FIFOS;i++){ |
||||
fifo_tx[i].len = 0; |
||||
fifo_tx[i].addr = virt_to_phys(&txbuf[0]); |
||||
fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE; |
||||
} |
||||
|
||||
/* Put mac addr in little endian */ |
||||
#define ea eth_get_dev()->enetaddr |
||||
*mac_addr_high = (ea[5] << 8) | (ea[4] ) ; |
||||
*mac_addr_low = (ea[3] << 24) | (ea[2] << 16) | |
||||
(ea[1] << 8) | (ea[0] ) ; |
||||
#undef ea |
||||
|
||||
*mac_mcast_low = 0; |
||||
*mac_mcast_high = 0; |
||||
|
||||
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX; |
||||
udelay(1); |
||||
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE; |
||||
|
||||
return(1); |
||||
} |
||||
|
||||
static void au1x00_halt(struct eth_device* dev){ |
||||
} |
||||
|
||||
int au1x00_enet_initialize(bd_t *bis){ |
||||
struct eth_device* dev; |
||||
|
||||
dev = (struct eth_device*) malloc(sizeof *dev); |
||||
memset(dev, 0, sizeof *dev); |
||||
|
||||
sprintf(dev->name, "Au1X00 ETHERNET"); |
||||
dev->iobase = 0; |
||||
dev->priv = 0; |
||||
dev->init = au1x00_init; |
||||
dev->halt = au1x00_halt; |
||||
dev->send = au1x00_send; |
||||
dev->recv = au1x00_recv; |
||||
|
||||
eth_register(dev); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
#endif /* CONFIG_AU1X00 */ |
@ -0,0 +1,123 @@ |
||||
/*
|
||||
* AU1X00 UART support |
||||
* |
||||
* Hardcoded to UART 0 for now |
||||
* Speed and options also hardcoded to 115200 8N1 |
||||
* |
||||
* Copyright (c) 2003 Thomas.Lange@corelatus.se |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
|
||||
#ifdef CONFIG_AU1X00 |
||||
|
||||
#include <common.h> |
||||
#include <asm/au1x00.h> |
||||
|
||||
/******************************************************************************
|
||||
* |
||||
* serial_init - initialize a channel |
||||
* |
||||
* This routine initializes the number of data bits, parity |
||||
* and set the selected baud rate. Interrupts are disabled. |
||||
* Set the modem control signals if the option is selected. |
||||
* |
||||
* RETURNS: N/A |
||||
*/ |
||||
|
||||
int serial_init (void) |
||||
{ |
||||
volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR); |
||||
volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE); |
||||
|
||||
/* Enable clocks first */ |
||||
*uart_enable = UART_EN_CE; |
||||
|
||||
/* Then release reset */ |
||||
/* Must release reset before setting other regs */ |
||||
*uart_enable = UART_EN_CE|UART_EN_E; |
||||
|
||||
/* Activate fifos, reset tx and rx */ |
||||
/* Set tx trigger level to 12 */ |
||||
*uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR| |
||||
UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12; |
||||
|
||||
serial_setbrg(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
void serial_setbrg (void) |
||||
{ |
||||
volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK); |
||||
volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR); |
||||
|
||||
/* Set baudrate to 115200 */ |
||||
*uart_clk = 0x36; |
||||
|
||||
/* Set parity, stop bits and word length to 8N1 */ |
||||
*uart_lcr = UART_LCR_WLEN8; |
||||
} |
||||
|
||||
void serial_putc (const char c) |
||||
{ |
||||
volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); |
||||
volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX); |
||||
|
||||
if (c == '\n') serial_putc ('\r'); |
||||
|
||||
/* Wait for fifo to shift out some bytes */ |
||||
while((*uart_lsr&UART_LSR_THRE)==0); |
||||
|
||||
*uart_tx = (u32)c; |
||||
} |
||||
|
||||
void serial_puts (const char *s) |
||||
{ |
||||
while (*s) |
||||
{ |
||||
serial_putc (*s++); |
||||
} |
||||
} |
||||
|
||||
int serial_getc (void) |
||||
{ |
||||
volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX); |
||||
char c; |
||||
|
||||
while (!serial_tstc()); |
||||
|
||||
c = (*uart_rx&0xFF); |
||||
return c; |
||||
} |
||||
|
||||
int serial_tstc (void) |
||||
{ |
||||
volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); |
||||
|
||||
if(*uart_lsr&UART_LSR_DR){ |
||||
/* Data in rfifo */ |
||||
return(1); |
||||
} |
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_SERIAL_AU1X00 */ |
@ -0,0 +1,69 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _ACEX1K_H_ |
||||
#define _ACEX1K_H_ |
||||
|
||||
#include <altera.h> |
||||
|
||||
extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size ); |
||||
extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize ); |
||||
extern int ACEX1K_info( Altera_desc *desc ); |
||||
extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off ); |
||||
|
||||
/* Slave Serial Implementation function table */ |
||||
typedef struct { |
||||
Altera_pre_fn pre; |
||||
Altera_config_fn config; |
||||
Altera_clk_fn clk; |
||||
Altera_status_fn status; |
||||
Altera_done_fn done; |
||||
Altera_data_fn data; |
||||
Altera_abort_fn abort; |
||||
Altera_post_fn post; |
||||
int relocated; |
||||
} Altera_ACEX1K_Passive_Serial_fns; |
||||
|
||||
/* Device Image Sizes
|
||||
*********************************************************************/ |
||||
/* ACEX1K */ |
||||
/* FIXME: Which size do we mean?
|
||||
* Datasheet says 1337000/8=167125Bytes, |
||||
* Filesize of an *.rbf file is 166965 Bytes |
||||
*/ |
||||
#if 0 |
||||
#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */ |
||||
#endif |
||||
#define Altera_EP1K100_SIZE (166965*8) |
||||
|
||||
/* Descriptor Macros
|
||||
*********************************************************************/ |
||||
/* ACEX1K devices */ |
||||
#define Altera_EP1K100_DESC(iface, fn_table, cookie) \ |
||||
{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie } |
||||
|
||||
#endif /* _ACEX1K_H_ */ |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,168 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for the dbau1x00 board. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ |
||||
#define CONFIG_DBAU1X00 1 |
||||
#define CONFIG_AU1X00 1 /* alchemy series cpu */ |
||||
|
||||
/* Also known as Merlot */ |
||||
#define CONFIG_DBAU1000 1 /* board, Hardcoded for now */ |
||||
#define CONFIG_AU1000 1 /* cpu, Hardcoded for now */ |
||||
|
||||
#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ |
||||
|
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* valid baudrates */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"addmisc=setenv bootargs $(bootargs) " \
|
||||
"console=ttyS0,$(baudrate) " \
|
||||
"panic=1\0" \
|
||||
"bootfile=/tftpboot/vmlinux.srec\0" \
|
||||
"load=tftp 80500000 $(u-boot)\0" \
|
||||
"" |
||||
/* Boot from Compact flash partition 2 as default */ |
||||
#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;bootm" |
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ |
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_ELF ) & \
|
||||
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
|
||||
CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
|
||||
CFG_CMD_BDI | CFG_CMD_BEDBUG)) |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "DbAu1x00 # " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args*/ |
||||
|
||||
#define CFG_MALLOC_LEN 128*1024 |
||||
|
||||
#define CFG_BOOTPARAMS_LEN 128*1024 |
||||
|
||||
#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ |
||||
|
||||
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x81000000 /* default load address */ |
||||
|
||||
#define CFG_MEMTEST_START 0x80100000 |
||||
#define CFG_MEMTEST_END 0x80800000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ |
||||
|
||||
#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ |
||||
|
||||
/* The following #defines are needed to get flash environment right */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (192 << 10) |
||||
|
||||
#define CFG_INIT_SP_OFFSET 0x400000 |
||||
|
||||
/* We boot from this flash, selected with dip switch */ |
||||
#define CFG_FLASH_BASE PHYS_FLASH_2 |
||||
|
||||
/* timeout values are in ticks */ |
||||
#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#define CFG_ENV_IS_NOWHERE 1 |
||||
|
||||
/* Address and size of Primary Environment Sector */ |
||||
#define CFG_ENV_ADDR 0xB0030000 |
||||
#define CFG_ENV_SIZE 0x10000 |
||||
|
||||
#define CONFIG_FLASH_16BIT |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 2 |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
|
||||
#define CONFIG_MEMSIZE_IN_BYTES |
||||
|
||||
/*---ATA PCMCIA ------------------------------------*/ |
||||
#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ |
||||
#define CFG_PCMCIA_MEM_ADDR 0x20000000 |
||||
#define CONFIG_PCMCIA_SLOT_A |
||||
|
||||
#define CONFIG_ATAPI 1 |
||||
#define CONFIG_MAC_PARTITION 1 |
||||
|
||||
/* We run CF in "true ide" mode or a harddrive via pcmcia */ |
||||
#define CONFIG_IDE_PCMCIA 1 |
||||
|
||||
/* We only support one slot for now */ |
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET 8 |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET 0 |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 |
||||
#define CFG_ICACHE_SIZE 16384 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
|
||||
#define DB1000_BCSR_ADDR 0xAE000000 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue