TCON unit has similar layout and functionality also on newer SoCs. This commit splits out TCON code for easier reuse later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>master
parent
10d8bc5a59
commit
5e023e7eb3
@ -0,0 +1,128 @@ |
||||
/*
|
||||
* Sunxi platform timing controller register and constant defines |
||||
* |
||||
* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> |
||||
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _LCDC_H |
||||
#define _LCDC_H |
||||
|
||||
struct ctfb_res_modes; |
||||
|
||||
struct sunxi_lcdc_reg { |
||||
u32 ctrl; /* 0x00 */ |
||||
u32 int0; /* 0x04 */ |
||||
u32 int1; /* 0x08 */ |
||||
u8 res0[0x04]; /* 0x0c */ |
||||
u32 tcon0_frm_ctrl; /* 0x10 */ |
||||
u32 tcon0_frm_seed[6]; /* 0x14 */ |
||||
u32 tcon0_frm_table[4]; /* 0x2c */ |
||||
u8 res1[4]; /* 0x3c */ |
||||
u32 tcon0_ctrl; /* 0x40 */ |
||||
u32 tcon0_dclk; /* 0x44 */ |
||||
u32 tcon0_timing_active; /* 0x48 */ |
||||
u32 tcon0_timing_h; /* 0x4c */ |
||||
u32 tcon0_timing_v; /* 0x50 */ |
||||
u32 tcon0_timing_sync; /* 0x54 */ |
||||
u32 tcon0_hv_intf; /* 0x58 */ |
||||
u8 res2[0x04]; /* 0x5c */ |
||||
u32 tcon0_cpu_intf; /* 0x60 */ |
||||
u32 tcon0_cpu_wr_dat; /* 0x64 */ |
||||
u32 tcon0_cpu_rd_dat0; /* 0x68 */ |
||||
u32 tcon0_cpu_rd_dat1; /* 0x6c */ |
||||
u32 tcon0_ttl_timing0; /* 0x70 */ |
||||
u32 tcon0_ttl_timing1; /* 0x74 */ |
||||
u32 tcon0_ttl_timing2; /* 0x78 */ |
||||
u32 tcon0_ttl_timing3; /* 0x7c */ |
||||
u32 tcon0_ttl_timing4; /* 0x80 */ |
||||
u32 tcon0_lvds_intf; /* 0x84 */ |
||||
u32 tcon0_io_polarity; /* 0x88 */ |
||||
u32 tcon0_io_tristate; /* 0x8c */ |
||||
u32 tcon1_ctrl; /* 0x90 */ |
||||
u32 tcon1_timing_source; /* 0x94 */ |
||||
u32 tcon1_timing_scale; /* 0x98 */ |
||||
u32 tcon1_timing_out; /* 0x9c */ |
||||
u32 tcon1_timing_h; /* 0xa0 */ |
||||
u32 tcon1_timing_v; /* 0xa4 */ |
||||
u32 tcon1_timing_sync; /* 0xa8 */ |
||||
u8 res3[0x44]; /* 0xac */ |
||||
u32 tcon1_io_polarity; /* 0xf0 */ |
||||
u32 tcon1_io_tristate; /* 0xf4 */ |
||||
u8 res4[0x108]; /* 0xf8 */ |
||||
u32 mux_ctrl; /* 0x200 */ |
||||
u8 res5[0x1c]; /* 0x204 */ |
||||
u32 lvds_ana0; /* 0x220 */ |
||||
u32 lvds_ana1; /* 0x224 */ |
||||
}; |
||||
|
||||
/*
|
||||
* LCDC register constants. |
||||
*/ |
||||
#define SUNXI_LCDC_X(x) (((x) - 1) << 16) |
||||
#define SUNXI_LCDC_Y(y) (((y) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) |
||||
#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) |
||||
#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) |
||||
#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) |
||||
#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) |
||||
#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) |
||||
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) |
||||
#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 |
||||
#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) |
||||
#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) |
||||
#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) |
||||
#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) |
||||
#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) |
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I |
||||
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) |
||||
#else |
||||
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ |
||||
#endif |
||||
#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) |
||||
#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) |
||||
#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) |
||||
#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20) |
||||
#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) |
||||
#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) |
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I |
||||
#define SUNXI_LCDC_LVDS_ANA0 0x40040320 |
||||
#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) |
||||
#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) |
||||
#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) |
||||
#else |
||||
#define SUNXI_LCDC_LVDS_ANA0 0x3f310000 |
||||
#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) |
||||
#endif |
||||
#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) |
||||
#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) |
||||
|
||||
void lcdc_init(struct sunxi_lcdc_reg * const lcdc); |
||||
void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth); |
||||
void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct ctfb_res_modes *mode, |
||||
int clk_div, bool for_ext_vga_dac, |
||||
int depth, int dclk_phase); |
||||
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct ctfb_res_modes *mode, |
||||
bool ext_hvsync, bool is_composite); |
||||
|
||||
#endif /* _LCDC_H */ |
@ -0,0 +1,8 @@ |
||||
#
|
||||
# (C) Copyright 2000-2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o ../videomodes.o
|
@ -0,0 +1,207 @@ |
||||
/*
|
||||
* Timing controller driver for Allwinner SoCs. |
||||
* |
||||
* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be> |
||||
* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> |
||||
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#include <asm/arch/lcdc.h> |
||||
#include <asm/io.h> |
||||
|
||||
#include "../videomodes.h" |
||||
|
||||
static int lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon) |
||||
{ |
||||
int delay; |
||||
|
||||
delay = mode->lower_margin + mode->vsync_len + |
||||
mode->upper_margin; |
||||
if (mode->vmode == FB_VMODE_INTERLACED) |
||||
delay /= 2; |
||||
if (tcon == 1) |
||||
delay -= 2; |
||||
|
||||
return (delay > 30) ? 30 : delay; |
||||
} |
||||
|
||||
void lcdc_init(struct sunxi_lcdc_reg * const lcdc) |
||||
{ |
||||
/* Init lcdc */ |
||||
writel(0, &lcdc->ctrl); /* Disable tcon */ |
||||
writel(0, &lcdc->int0); /* Disable all interrupts */ |
||||
|
||||
/* Disable tcon0 dot clock */ |
||||
clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE); |
||||
|
||||
/* Set all io lines to tristate */ |
||||
writel(0xffffffff, &lcdc->tcon0_io_tristate); |
||||
writel(0xffffffff, &lcdc->tcon1_io_tristate); |
||||
} |
||||
|
||||
void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth) |
||||
{ |
||||
setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); |
||||
#ifdef CONFIG_VIDEO_LCD_IF_LVDS |
||||
setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE); |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); |
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I |
||||
udelay(2); /* delay at least 1200 ns */ |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB); |
||||
udelay(2); /* delay at least 1200 ns */ |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC); |
||||
if (depth == 18) |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7)); |
||||
else |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf)); |
||||
#else |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); |
||||
udelay(2); /* delay at least 1200 ns */ |
||||
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1); |
||||
udelay(1); /* delay at least 120 ns */ |
||||
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2); |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); |
||||
#endif |
||||
#endif |
||||
} |
||||
|
||||
void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct ctfb_res_modes *mode, |
||||
int clk_div, bool for_ext_vga_dac, |
||||
int depth, int dclk_phase) |
||||
{ |
||||
int bp, clk_delay, total, val; |
||||
|
||||
/* Use tcon0 */ |
||||
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, |
||||
SUNXI_LCDC_CTRL_IO_MAP_TCON0); |
||||
|
||||
clk_delay = lcdc_get_clk_delay(mode, 0); |
||||
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE | |
||||
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl); |
||||
|
||||
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE | |
||||
SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk); |
||||
|
||||
writel(SUNXI_LCDC_X(mode->xres) | |
||||
SUNXI_LCDC_Y(mode->yres), &lcdc->tcon0_timing_active); |
||||
|
||||
bp = mode->hsync_len + mode->left_margin; |
||||
total = mode->xres + mode->right_margin + bp; |
||||
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) | |
||||
SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h); |
||||
|
||||
bp = mode->vsync_len + mode->upper_margin; |
||||
total = mode->yres + mode->lower_margin + bp; |
||||
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) | |
||||
SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v); |
||||
|
||||
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL |
||||
writel(SUNXI_LCDC_X(mode->hsync_len) | |
||||
SUNXI_LCDC_Y(mode->vsync_len), &lcdc->tcon0_timing_sync); |
||||
|
||||
writel(0, &lcdc->tcon0_hv_intf); |
||||
writel(0, &lcdc->tcon0_cpu_intf); |
||||
#endif |
||||
#ifdef CONFIG_VIDEO_LCD_IF_LVDS |
||||
val = (depth == 18) ? 1 : 0; |
||||
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) | |
||||
SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf); |
||||
#endif |
||||
|
||||
if (depth == 18 || depth == 16) { |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]); |
||||
writel(((depth == 18) ? |
||||
SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 : |
||||
SUNXI_LCDC_TCON0_FRM_CTRL_RGB565), |
||||
&lcdc->tcon0_frm_ctrl); |
||||
} |
||||
|
||||
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase); |
||||
if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) |
||||
val |= SUNXI_LCDC_TCON_HSYNC_MASK; |
||||
if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) |
||||
val |= SUNXI_LCDC_TCON_VSYNC_MASK; |
||||
|
||||
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
||||
if (for_ext_vga_dac) |
||||
val = 0; |
||||
#endif |
||||
writel(val, &lcdc->tcon0_io_polarity); |
||||
|
||||
writel(0, &lcdc->tcon0_io_tristate); |
||||
} |
||||
|
||||
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct ctfb_res_modes *mode, |
||||
bool ext_hvsync, bool is_composite) |
||||
{ |
||||
int bp, clk_delay, total, val, yres; |
||||
|
||||
/* Use tcon1 */ |
||||
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, |
||||
SUNXI_LCDC_CTRL_IO_MAP_TCON1); |
||||
|
||||
clk_delay = lcdc_get_clk_delay(mode, 1); |
||||
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE | |
||||
((mode->vmode == FB_VMODE_INTERLACED) ? |
||||
SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) | |
||||
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl); |
||||
|
||||
yres = mode->yres; |
||||
if (mode->vmode == FB_VMODE_INTERLACED) |
||||
yres /= 2; |
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres), |
||||
&lcdc->tcon1_timing_source); |
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres), |
||||
&lcdc->tcon1_timing_scale); |
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres), |
||||
&lcdc->tcon1_timing_out); |
||||
|
||||
bp = mode->hsync_len + mode->left_margin; |
||||
total = mode->xres + mode->right_margin + bp; |
||||
writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) | |
||||
SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h); |
||||
|
||||
bp = mode->vsync_len + mode->upper_margin; |
||||
total = mode->yres + mode->lower_margin + bp; |
||||
if (mode->vmode == FB_VMODE_NONINTERLACED) |
||||
total *= 2; |
||||
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) | |
||||
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v); |
||||
|
||||
writel(SUNXI_LCDC_X(mode->hsync_len) | |
||||
SUNXI_LCDC_Y(mode->vsync_len), &lcdc->tcon1_timing_sync); |
||||
|
||||
if (ext_hvsync) { |
||||
val = 0; |
||||
if (mode->sync & FB_SYNC_HOR_HIGH_ACT) |
||||
val |= SUNXI_LCDC_TCON_HSYNC_MASK; |
||||
if (mode->sync & FB_SYNC_VERT_HIGH_ACT) |
||||
val |= SUNXI_LCDC_TCON_VSYNC_MASK; |
||||
writel(val, &lcdc->tcon1_io_polarity); |
||||
|
||||
clrbits_le32(&lcdc->tcon1_io_tristate, |
||||
SUNXI_LCDC_TCON_VSYNC_MASK | |
||||
SUNXI_LCDC_TCON_HSYNC_MASK); |
||||
} |
||||
|
||||
#ifdef CONFIG_MACH_SUN5I |
||||
if (is_composite) |
||||
clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK, |
||||
SUNXI_LCDC_MUX_CTRL_SRC0(1)); |
||||
#endif |
||||
} |
Loading…
Reference in new issue