Conflicts: include/asm-ppc/fsl_lbc.h Signed-off-by: Wolfgang Denk <wd@denx.de>master
Wolfgang Denk
17 years ago
commit
5ea67393b8
@ -0,0 +1,218 @@ |
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/*
|
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* (C) Copyright 2008 |
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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|
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#if defined(CFG_NAND_BASE) |
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#include <nand.h> |
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#include <asm/errno.h> |
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#include <asm/io.h> |
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static int state; |
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static void nand_write_byte(struct mtd_info *mtd, u_char byte); |
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static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); |
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static void nand_write_word(struct mtd_info *mtd, u16 word); |
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static u_char nand_read_byte(struct mtd_info *mtd); |
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static u16 nand_read_word(struct mtd_info *mtd); |
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static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); |
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static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); |
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static int nand_device_ready(struct mtd_info *mtdinfo); |
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd); |
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|
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#define FPGA_NAND_CMD_MASK (0x7 << 28) |
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#define FPGA_NAND_CMD_COMMAND (0x0 << 28) |
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#define FPGA_NAND_CMD_ADDR (0x1 << 28) |
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#define FPGA_NAND_CMD_READ (0x2 << 28) |
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#define FPGA_NAND_CMD_WRITE (0x3 << 28) |
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#define FPGA_NAND_BUSY (0x1 << 15) |
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#define FPGA_NAND_ENABLE (0x1 << 31) |
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#define FPGA_NAND_DATA_SHIFT 16 |
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/**
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* nand_write_byte - write one byte to the chip |
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* @mtd: MTD device structure |
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* @byte: pointer to data byte to write |
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*/ |
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static void nand_write_byte(struct mtd_info *mtd, u_char byte) |
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{ |
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nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte)); |
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} |
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|
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/**
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* nand_write_word - write one word to the chip |
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* @mtd: MTD device structure |
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* @word: data word to write |
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*/ |
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static void nand_write_word(struct mtd_info *mtd, u16 word) |
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{ |
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nand_write_buf(mtd, (const uchar *)&word, sizeof(word)); |
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} |
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|
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/**
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* nand_write_buf - write buffer to chip |
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* @mtd: MTD device structure |
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* @buf: data buffer |
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* @len: number of bytes to write |
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*/ |
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static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
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{ |
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int i; |
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struct nand_chip *this = mtd->priv; |
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long val; |
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if ((state & FPGA_NAND_CMD_MASK) == FPGA_NAND_CMD_MASK) { |
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/* Write data */ |
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val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_WRITE; |
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} else { |
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/* Write address or command */ |
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val = state; |
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} |
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for (i = 0; i < len; i++) { |
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out_be32(this->IO_ADDR_W, val | (buf[i] << FPGA_NAND_DATA_SHIFT)); |
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} |
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} |
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/**
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* nand_read_byte - read one byte from the chip |
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* @mtd: MTD device structure |
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*/ |
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static u_char nand_read_byte(struct mtd_info *mtd) |
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{ |
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u8 byte; |
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nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); |
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return byte; |
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} |
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|
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/**
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* nand_read_word - read one word from the chip |
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* @mtd: MTD device structure |
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*/ |
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static u16 nand_read_word(struct mtd_info *mtd) |
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{ |
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u16 word; |
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nand_read_buf(mtd, (uchar *)&word, sizeof(word)); |
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return word; |
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} |
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|
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/**
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* nand_read_buf - read chip data into buffer |
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* @mtd: MTD device structure |
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* @buf: buffer to store date |
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* @len: number of bytes to read |
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*/ |
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static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
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{ |
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int i; |
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struct nand_chip *this = mtd->priv; |
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int val; |
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val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; |
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out_be32(this->IO_ADDR_W, val); |
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for (i = 0; i < len; i++) { |
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buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff; |
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} |
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} |
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/**
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* nand_verify_buf - Verify chip data against buffer |
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* @mtd: MTD device structure |
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* @buf: buffer containing the data to compare |
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* @len: number of bytes to compare |
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*/ |
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static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) |
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{ |
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int i; |
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for (i = 0; i < len; i++) { |
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if (buf[i] != nand_read_byte(mtd)); |
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return -EFAULT; |
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} |
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return 0; |
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} |
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/**
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* nand_device_ready - Check the NAND device is ready for next command. |
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* @mtd: MTD device structure |
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*/ |
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static int nand_device_ready(struct mtd_info *mtdinfo) |
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{ |
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struct nand_chip *this = mtdinfo->priv; |
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if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) |
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return 0; /* busy */ |
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return 1; |
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} |
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/**
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* nand_hwcontrol - NAND control functions wrapper. |
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* @mtd: MTD device structure |
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* @cmd: Command |
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*/ |
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) |
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{ |
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switch(cmd) { |
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case NAND_CTL_CLRALE: |
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state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */ |
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break; |
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case NAND_CTL_CLRCLE: |
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state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */ |
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break; |
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case NAND_CTL_SETCLE: |
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state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_COMMAND; |
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break; |
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case NAND_CTL_SETALE: |
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state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_ADDR; |
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break; |
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case NAND_CTL_SETNCE: |
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state |= FPGA_NAND_ENABLE; |
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break; |
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case NAND_CTL_CLRNCE: |
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state &= ~FPGA_NAND_ENABLE; |
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break; |
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default: |
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printf("%s: unknown cmd %#x\n", __FUNCTION__, cmd); |
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break; |
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} |
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} |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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nand->hwcontrol = nand_hwcontrol; |
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nand->eccmode = NAND_ECC_SOFT; |
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nand->dev_ready = nand_device_ready; |
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nand->write_byte = nand_write_byte; |
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nand->read_byte = nand_read_byte; |
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nand->write_word = nand_write_word; |
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nand->read_word = nand_read_word; |
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nand->write_buf = nand_write_buf; |
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nand->read_buf = nand_read_buf; |
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nand->verify_buf = nand_verify_buf; |
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return 0; |
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} |
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#endif |
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@ -0,0 +1,55 @@ |
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/*
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* (C) Copyright 2008 |
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. |
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* |
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* Copyright 2004, 2007 Freescale Semiconductor, Inc. |
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* (C) Copyright 2003 Motorola Inc. |
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* Xianghua Xiao, (X.Xiao@motorola.com) |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __UPM_TABLE_H |
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#define __UPM_TABLE_H |
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/* UPM Table Configuration Code for FPGA access */ |
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static const unsigned int UPMTableA[] = |
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{ |
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0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, //Words 0 to 3
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0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, //Words 4 to 7
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0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, //Words 8 to 11
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0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, //Words 12 to 15
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0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, //Words 16 to 19
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23
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0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, //Words 24 to 27
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0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, //Words 28 to 31
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0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 32 to 35
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0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 36 to 39
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0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43
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0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 48 to 51
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 //Words 60 to 63
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}; |
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#endif |
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@ -0,0 +1,86 @@ |
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/*
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* Copyright 2008 Freescale Semiconductor, Inc. |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
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* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/fsl_law.h> |
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#include <asm/mmu.h> |
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/*
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* LAW(Local Access Window) configuration: |
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* |
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* Standard mapping: |
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* |
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* 0x0000_0000 0x7fff_ffff DDR 2G |
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
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* 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M |
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* 0xe000_0000 0xe000_ffff CCSR 1M |
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
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* 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M |
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* 0xef00_0000 0xefff_ffff PCI express IO 16M |
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* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M |
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* |
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* Big FLASH mapping: |
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* |
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* 0x0000_0000 0x7fff_ffff DDR 2G |
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
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* 0xa000_0000 0xa000_ffff CCSR 1M |
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* 0xa200_0000 0xa2ff_ffff PCI1 IO 16M |
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* 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M |
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* 0xaf00_0000 0xafff_ffff PCI express IO 16M |
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* 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M |
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* 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G |
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* |
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* Notes: |
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
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* If flash is 8M at default position (last 8M), no LAW needed. |
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*/ |
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#ifdef CONFIG_TQM_BIGFLASH |
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#define LAW_3_SIZE LAW_SIZE_1G |
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#define LAW_5_SIZE LAW_SIZE_256M |
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#else |
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#define LAW_3_SIZE LAW_SIZE_128M |
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#define LAW_5_SIZE LAW_SIZE_512M |
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#endif |
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struct law_entry law_table[] = { |
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SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), |
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SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
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SET_LAW(CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), |
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SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), |
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#ifdef CONFIG_PCIE1 |
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SET_LAW(CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), |
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#else /* !CONFIG_PCIE1 */ |
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SET_LAW(CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), |
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#endif /* CONFIG_PCIE1 */ |
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#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) |
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SET_LAW(CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), |
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#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ |
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#ifdef CONFIG_PCIE1 |
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SET_LAW(CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), |
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#endif /* CONFIG_PCIE */ |
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}; |
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int num_law_entries = ARRAY_SIZE (law_table); |
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@ -0,0 +1,469 @@ |
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/*
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* (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> |
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* |
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* (C) Copyright 2006 |
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* Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/processor.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/processor.h> |
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#include <asm/mmu.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/fsl_upm.h> |
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#include <ioports.h> |
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|
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#include <nand.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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extern uint get_lbc_clock (void); |
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|
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/* index of UPM RAM array run pattern for NAND command cycle */ |
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#define CFG_NAN_UPM_WRITE_CMD_OFS 0x08 |
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|
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/* index of UPM RAM array run pattern for NAND address cycle */ |
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#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x10 |
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|
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/* Structure for table with supported UPM timings */ |
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struct upm_freq { |
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ulong freq; |
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const u32 *upm_patt; |
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uchar gpl4_disable; |
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uchar ehtr; |
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uchar ead; |
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}; |
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|
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/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */ |
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|
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/* UPM pattern for bus clock = 25 MHz */ |
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static const u32 upm_patt_25[] = { |
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
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/* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00, |
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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|
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/* UPM Read Burst RAM array entry -> NAND Write CMD */ |
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/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, |
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/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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|
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */ |
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/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, |
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/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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|
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/* UPM Write Single RAM array entry -> NAND Write Data */ |
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/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, |
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/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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|
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/* UPM Write Burst RAM array entry -> unused */ |
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/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
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|
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/* UPM Refresh Timer RAM array entry -> unused */ |
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/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
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|
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/* UPM Exception RAM array entry -> unsused */ |
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/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
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}; |
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|
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/* UPM pattern for bus clock = 33.3 MHz */ |
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static const u32 upm_patt_33[] = { |
||||
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
||||
/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, |
||||
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write CMD */ |
||||
/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, |
||||
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write ADDR */ |
||||
/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, |
||||
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Single RAM array entry -> NAND Write Data */ |
||||
/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, |
||||
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Burst RAM array entry -> unused */ |
||||
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Refresh Timer RAM array entry -> unused */ |
||||
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Exception RAM array entry -> unsused */ |
||||
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
}; |
||||
|
||||
/* UPM pattern for bus clock = 41.7 MHz */ |
||||
static const u32 upm_patt_42[] = { |
||||
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
||||
/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, |
||||
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write CMD */ |
||||
/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, |
||||
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write ADDR */ |
||||
/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, |
||||
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Single RAM array entry -> NAND Write Data */ |
||||
/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, |
||||
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Burst RAM array entry -> unused */ |
||||
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Refresh Timer RAM array entry -> unused */ |
||||
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Exception RAM array entry -> unsused */ |
||||
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
}; |
||||
|
||||
/* UPM pattern for bus clock = 50 MHz */ |
||||
static const u32 upm_patt_50[] = { |
||||
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
||||
/* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00, |
||||
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write CMD */ |
||||
/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00, |
||||
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write ADDR */ |
||||
/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00, |
||||
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Single RAM array entry -> NAND Write Data */ |
||||
/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00, |
||||
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Burst RAM array entry -> unused */ |
||||
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Refresh Timer RAM array entry -> unused */ |
||||
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Exception RAM array entry -> unsused */ |
||||
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
}; |
||||
|
||||
/* UPM pattern for bus clock = 66.7 MHz */ |
||||
static const u32 upm_patt_67[] = { |
||||
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
||||
/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, |
||||
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write CMD */ |
||||
/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, |
||||
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write ADDR */ |
||||
/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, |
||||
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Single RAM array entry -> NAND Write Data */ |
||||
/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, |
||||
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Burst RAM array entry -> unused */ |
||||
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Refresh Timer RAM array entry -> unused */ |
||||
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Exception RAM array entry -> unsused */ |
||||
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
}; |
||||
|
||||
/* UPM pattern for bus clock = 83.3 MHz */ |
||||
static const u32 upm_patt_83[] = { |
||||
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
||||
/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, |
||||
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write CMD */ |
||||
/* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, |
||||
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write ADDR */ |
||||
/* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, |
||||
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Single RAM array entry -> NAND Write Data */ |
||||
/* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, |
||||
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Burst RAM array entry -> unused */ |
||||
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Refresh Timer RAM array entry -> unused */ |
||||
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Exception RAM array entry -> unsused */ |
||||
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
}; |
||||
|
||||
/* UPM pattern for bus clock = 100 MHz */ |
||||
static const u32 upm_patt_100[] = { |
||||
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
||||
/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000, |
||||
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write CMD */ |
||||
/* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, |
||||
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write ADDR */ |
||||
/* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, |
||||
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Single RAM array entry -> NAND Write Data */ |
||||
/* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, |
||||
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Burst RAM array entry -> unused */ |
||||
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Refresh Timer RAM array entry -> unused */ |
||||
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Exception RAM array entry -> unsused */ |
||||
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
}; |
||||
|
||||
/* UPM pattern for bus clock = 133.3 MHz */ |
||||
static const u32 upm_patt_133[] = { |
||||
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
||||
/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000, |
||||
/* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write CMD */ |
||||
/* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35, |
||||
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write ADDR */ |
||||
/* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35, |
||||
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Single RAM array entry -> NAND Write Data */ |
||||
/* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05, |
||||
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Burst RAM array entry -> unused */ |
||||
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Refresh Timer RAM array entry -> unused */ |
||||
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Exception RAM array entry -> unsused */ |
||||
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
}; |
||||
|
||||
/* UPM pattern for bus clock = 166.7 MHz */ |
||||
static const u32 upm_patt_167[] = { |
||||
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ |
||||
/* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300, |
||||
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write CMD */ |
||||
/* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35, |
||||
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Read Burst RAM array entry -> NAND Write ADDR */ |
||||
/* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35, |
||||
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Single RAM array entry -> NAND Write Data */ |
||||
/* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05, |
||||
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
|
||||
/* UPM Write Burst RAM array entry -> unused */ |
||||
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Refresh Timer RAM array entry -> unused */ |
||||
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
||||
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
|
||||
/* UPM Exception RAM array entry -> unsused */ |
||||
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
||||
}; |
||||
|
||||
/* Supported UPM timings */ |
||||
struct upm_freq upm_freq_table[] = { |
||||
/* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */ |
||||
{25000000, upm_patt_25, 1, 0, 0}, |
||||
{33333333, upm_patt_33, 1, 0, 0}, |
||||
{41666666, upm_patt_42, 1, 0, 0}, |
||||
{50000000, upm_patt_50, 0, 0, 0}, |
||||
{66666666, upm_patt_67, 0, 0, 0}, |
||||
{83333333, upm_patt_83, 0, 0, 0}, |
||||
{100000000, upm_patt_100, 0, 1, 1}, |
||||
{133333333, upm_patt_133, 0, 1, 1}, |
||||
{166666666, upm_patt_167, 0, 1, 1}, |
||||
}; |
||||
|
||||
#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq)) |
||||
|
||||
volatile const u32 *nand_upm_patt; |
||||
|
||||
/*
|
||||
* write into UPMB ram |
||||
*/ |
||||
static void upmb_write (u_char addr, ulong val) |
||||
{ |
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
|
||||
out_be32 (&lbc->mdr, val); |
||||
|
||||
clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK, |
||||
MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); |
||||
|
||||
/* dummy access to perform write */ |
||||
out_8 ((void __iomem *)CFG_NAND0_BASE, 0); |
||||
|
||||
clrbits_be32(&lbc->mbmr, MxMR_OP_WARR); |
||||
} |
||||
|
||||
/*
|
||||
* Initialize UPM for NAND flash access. |
||||
*/ |
||||
static void nand_upm_setup (volatile ccsr_lbc_t *lbc) |
||||
{ |
||||
uint i; |
||||
uint or3 = CFG_OR3_PRELIM; |
||||
uint clock = get_lbc_clock (); |
||||
|
||||
out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */ |
||||
out_be32 (&lbc->br3, CFG_BR3_PRELIM); |
||||
|
||||
/*
|
||||
* Search appropriate UPM table for bus clock. |
||||
* If the bus clock exceeds a tolerated value, take the UPM timing for |
||||
* the next higher supported frequency to ensure that access works |
||||
* (even the access may be slower then). |
||||
*/ |
||||
for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++) |
||||
; |
||||
|
||||
if (i >= UPM_FREQS) |
||||
/* no valid entry found */ |
||||
/* take last entry with configuration for max. bus clock */ |
||||
i--; |
||||
|
||||
if (upm_freq_table[i].ehtr) { |
||||
/* EHTR must be set due to TQM8548 timing specification */ |
||||
or3 |= OR_UPM_EHTR; |
||||
} |
||||
if (upm_freq_table[i].ead) |
||||
/* EAD must be set due to TQM8548 timing specification */ |
||||
or3 |= OR_UPM_EAD; |
||||
|
||||
out_be32 (&lbc->or3, or3); |
||||
|
||||
/* Assign address of table */ |
||||
nand_upm_patt = upm_freq_table[i].upm_patt; |
||||
|
||||
for (i = 0; i < 64; i++) { |
||||
upmb_write (i, *nand_upm_patt); |
||||
nand_upm_patt++; |
||||
} |
||||
|
||||
/* Put UPM back to normal operation mode */ |
||||
if (upm_freq_table[i].gpl4_disable) |
||||
/* GPL4 must be disabled according to timing specification */ |
||||
out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS); |
||||
|
||||
return; |
||||
} |
||||
|
||||
static struct fsl_upm_nand fun = { |
||||
.width = 8, |
||||
.upm_cmd_offset = 0x08, |
||||
.upm_addr_offset = 0x10, |
||||
.chip_delay = NAND_BIG_DELAY_US, |
||||
}; |
||||
|
||||
void board_nand_select_device (struct nand_chip *nand, int chip) |
||||
{ |
||||
} |
||||
|
||||
int board_nand_init (struct nand_chip *nand) |
||||
{ |
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
|
||||
if (!nand_upm_patt) |
||||
nand_upm_setup (lbc); |
||||
|
||||
fun.upm.io_addr = nand->IO_ADDR_R; |
||||
fun.upm.mxmr = (void __iomem *)&lbc->mbmr; |
||||
fun.upm.mdr = (void __iomem *)&lbc->mdr; |
||||
fun.upm.mar = (void __iomem *)&lbc->mar; |
||||
|
||||
return fsl_upm_nand_init (nand, &fun); |
||||
} |
||||
@ -0,0 +1,371 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct sdram_conf_s { |
||||
unsigned long size; |
||||
unsigned long reg; |
||||
#ifdef CONFIG_TQM8548 |
||||
unsigned long refresh; |
||||
#endif /* CONFIG_TQM8548 */ |
||||
}; |
||||
|
||||
typedef struct sdram_conf_s sdram_conf_t; |
||||
|
||||
#ifdef CONFIG_TQM8548 |
||||
sdram_conf_t ddr_cs_conf[] = { |
||||
{(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ |
||||
{(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ |
||||
{(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ |
||||
}; |
||||
#else /* !CONFIG_TQM8548 */ |
||||
sdram_conf_t ddr_cs_conf[] = { |
||||
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ |
||||
{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ |
||||
{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ |
||||
{( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ |
||||
}; |
||||
#endif /* CONFIG_TQM8548 */ |
||||
|
||||
#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) |
||||
|
||||
int cas_latency (void); |
||||
|
||||
/*
|
||||
* Autodetect onboard DDR SDRAM on 85xx platforms |
||||
* |
||||
* NOTE: Some of the hardcoded values are hardware dependant, |
||||
* so this should be extended for other future boards |
||||
* using this routine! |
||||
*/ |
||||
long int sdram_setup (int casl) |
||||
{ |
||||
int i; |
||||
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); |
||||
#ifdef CONFIG_TQM8548 |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
#else /* !CONFIG_TQM8548 */ |
||||
unsigned long cfg_ddr_timing1; |
||||
unsigned long cfg_ddr_mode; |
||||
#endif /* CONFIG_TQM8548 */ |
||||
|
||||
/*
|
||||
* Disable memory controller. |
||||
*/ |
||||
ddr->cs0_config = 0; |
||||
ddr->sdram_cfg = 0; |
||||
|
||||
#ifdef CONFIG_TQM8548 |
||||
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; |
||||
ddr->cs0_config = ddr_cs_conf[0].reg; |
||||
ddr->timing_cfg_3 = 0x00010000; |
||||
|
||||
/* TIMING CFG 1, 533MHz
|
||||
* PRETOACT: 4 Clocks |
||||
* ACTTOPRE: 12 Clocks |
||||
* ACTTORW: 4 Clocks |
||||
* CASLAT: 4 Clocks |
||||
* REFREC: 34 Clocks |
||||
* WRREC: 4 Clocks |
||||
* ACTTOACT: 3 Clocks |
||||
* WRTORD: 2 Clocks |
||||
*/ |
||||
ddr->timing_cfg_1 = 0x4C47A432; |
||||
|
||||
/* TIMING CFG 2, 533MHz
|
||||
* ADD_LAT: 3 Clocks |
||||
* CPO: READLAT + 1 |
||||
* WR_LAT: 3 Clocks |
||||
* RD_TO_PRE: 2 Clocks |
||||
* WR_DATA_DELAY: 1/2 Clock |
||||
* CKE_PLS: 1 Clock |
||||
* FOUR_ACT: 13 Clocks |
||||
*/ |
||||
ddr->timing_cfg_2 = 0x3318484D; |
||||
|
||||
/* DDR SDRAM Mode, 533MHz
|
||||
* MRS: Extended Mode Register |
||||
* OUT: Outputs enabled |
||||
* RDQS: no |
||||
* DQS: enabled |
||||
* OCD: default state |
||||
* RTT: 75 Ohms |
||||
* Posted CAS: 3 Clocks |
||||
* ODS: reduced strength |
||||
* DLL: enabled |
||||
* MR: Mode Register |
||||
* PD: fast exit |
||||
* WR: 4 Clocks |
||||
* DLL: no DLL reset |
||||
* TM: normal |
||||
* CAS latency: 4 Clocks |
||||
* BT: sequential |
||||
* Burst length: 4 |
||||
*/ |
||||
ddr->sdram_mode = 0x439E0642; |
||||
|
||||
/* DDR SDRAM Interval, 533MHz
|
||||
* REFINT: 1040 Clocks |
||||
* BSTOPRE: 256 |
||||
*/ |
||||
ddr->sdram_interval = (1040 << 16) | 0x100; |
||||
|
||||
/*
|
||||
* workaround for erratum DD10 of MPC8458 family below rev. 2.0: |
||||
* DDR IO receiver must be set to an acceptable bias point by modifying |
||||
* a hidden register. |
||||
*/ |
||||
if (SVR_REV (get_svr ()) < 0x20) { |
||||
gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */ |
||||
} |
||||
|
||||
/* DDR SDRAM CFG 2
|
||||
* FRC_SR: normal mode |
||||
* SR_IE: no self-refresh interrupt |
||||
* DLL_RST_DIS: don't care, leave at reset value |
||||
* DQS_CFG: differential DQS signals |
||||
* ODT_CFG: assert ODT to internal IOs only during reads to DRAM |
||||
* LVWx_CFG: don't care, leave at reset value |
||||
* NUM_PR: 1 refresh will be issued at a time |
||||
* DM_CFG: don't care, leave at reset value |
||||
* D_INIT: no data initialization |
||||
*/ |
||||
ddr->sdram_cfg_2 = 0x04401000; |
||||
|
||||
/* DDR SDRAM MODE 2
|
||||
* MRS: Extended Mode Register 2 |
||||
*/ |
||||
ddr->sdram_mode_2 = 0x8000C000; |
||||
|
||||
/* DDR SDRAM CLK CNTL
|
||||
* CLK_ADJUST: 1/2 Clock 0x02000000 |
||||
* CLK_ADJUST: 5/8 Clock 0x02800000 |
||||
*/ |
||||
ddr->sdram_clk_cntl = 0x02800000; |
||||
|
||||
/* wait for clock stabilization */ |
||||
asm ("sync;isync;msync"); |
||||
udelay(1000); |
||||
|
||||
/* DDR SDRAM CLK CNTL
|
||||
* MEM_EN: enabled |
||||
* SREN: don't care, leave at reset value |
||||
* ECC_EN: no error report |
||||
* RD_EN: no register DIMMs |
||||
* SDRAM_TYPE: DDR2 |
||||
* DYN_PWR: no power management |
||||
* 32_BE: don't care, leave at reset value |
||||
* 8_BE: 4 beat burst |
||||
* NCAP: don't care, leave at reset value |
||||
* 2T_EN: 1T Timing |
||||
* BA_INTLV_CTL: no interleaving |
||||
* x32_EN: x16 organization |
||||
* PCHB8: MA[10] for auto-precharge |
||||
* HSE: half strength for single and 2-layer stacks |
||||
* (full strength for 3- and 4-layer stacks no yet considered) |
||||
* MEM_HALT: no halt |
||||
* BI: automatic initialization |
||||
*/ |
||||
ddr->sdram_cfg = 0x83000008; |
||||
asm ("sync; isync; msync"); |
||||
udelay(1000); |
||||
|
||||
#else /* !CONFIG_TQM8548 */ |
||||
switch (casl) { |
||||
case 20: |
||||
cfg_ddr_timing1 = 0x47405331 | (3 << 16); |
||||
cfg_ddr_mode = 0x40020002 | (2 << 4); |
||||
break; |
||||
|
||||
case 25: |
||||
cfg_ddr_timing1 = 0x47405331 | (4 << 16); |
||||
cfg_ddr_mode = 0x40020002 | (6 << 4); |
||||
break; |
||||
|
||||
case 30: |
||||
default: |
||||
cfg_ddr_timing1 = 0x47405331 | (5 << 16); |
||||
cfg_ddr_mode = 0x40020002 | (3 << 4); |
||||
break; |
||||
} |
||||
|
||||
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; |
||||
ddr->cs0_config = ddr_cs_conf[0].reg; |
||||
ddr->timing_cfg_1 = cfg_ddr_timing1; |
||||
ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ |
||||
ddr->sdram_mode = cfg_ddr_mode; |
||||
ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ |
||||
ddr->err_disable = 0x0000000D; |
||||
|
||||
asm ("sync; isync; msync"); |
||||
udelay (1000); |
||||
|
||||
ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ |
||||
asm ("sync; isync; msync"); |
||||
udelay (1000); |
||||
#endif /* CONFIG_TQM8548 */ |
||||
|
||||
for (i = 0; i < N_DDR_CS_CONF; i++) { |
||||
ddr->cs0_config = ddr_cs_conf[i].reg; |
||||
|
||||
if (get_ram_size (0, ddr_cs_conf[i].size) == |
||||
ddr_cs_conf[i].size) { |
||||
/*
|
||||
* size detected -> set Chip Select Bounds Register |
||||
*/ |
||||
ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24; |
||||
|
||||
break; |
||||
} |
||||
} |
||||
|
||||
#ifdef CONFIG_TQM8548 |
||||
if (i < N_DDR_CS_CONF) { |
||||
/* Adjust refresh rate for DDR2 */ |
||||
|
||||
ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000; |
||||
|
||||
ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) | |
||||
(ddr_cs_conf[i].refresh & 0x0000F000); |
||||
|
||||
return ddr_cs_conf[i].size; |
||||
} |
||||
#endif /* CONFIG_TQM8548 */ |
||||
|
||||
/* return size if detected, else return 0 */ |
||||
return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; |
||||
} |
||||
|
||||
void board_add_ram_info (int use_default) |
||||
{ |
||||
int casl; |
||||
|
||||
if (use_default) |
||||
casl = CONFIG_DDR_DEFAULT_CL; |
||||
else |
||||
casl = cas_latency (); |
||||
|
||||
puts (" (CL="); |
||||
switch (casl) { |
||||
case 20: |
||||
puts ("2)"); |
||||
break; |
||||
|
||||
case 25: |
||||
puts ("2.5)"); |
||||
break; |
||||
|
||||
case 30: |
||||
puts ("3)"); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
int casl; |
||||
|
||||
#if defined(CONFIG_DDR_DLL) |
||||
/*
|
||||
* This DLL-Override only used on TQM8540 and TQM8560 |
||||
*/ |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
int i, x; |
||||
|
||||
x = 10; |
||||
|
||||
/*
|
||||
* Work around to stabilize DDR DLL |
||||
*/ |
||||
gur->ddrdllcr = 0x81000000; |
||||
asm ("sync; isync; msync"); |
||||
udelay (200); |
||||
while (gur->ddrdllcr != 0x81000100) { |
||||
gur->devdisr = gur->devdisr | 0x00010000; |
||||
asm ("sync; isync; msync"); |
||||
for (i = 0; i < x; i++) |
||||
; |
||||
gur->devdisr = gur->devdisr & 0xfff7ffff; |
||||
asm ("sync; isync; msync"); |
||||
x++; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
casl = cas_latency (); |
||||
dram_size = sdram_setup (casl); |
||||
if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { |
||||
/*
|
||||
* Try again with default CAS latency |
||||
*/ |
||||
puts ("Problem with CAS lantency"); |
||||
board_add_ram_info (1); |
||||
puts (", using default CL!\n"); |
||||
casl = CONFIG_DDR_DEFAULT_CL; |
||||
dram_size = sdram_setup (casl); |
||||
puts (" "); |
||||
} |
||||
|
||||
return dram_size; |
||||
} |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) CFG_MEMTEST_START; |
||||
uint *pend = (uint *) CFG_MEMTEST_END; |
||||
uint *p; |
||||
|
||||
printf ("SDRAM test phase 1:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf ("SDRAM test phase 2:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf ("SDRAM test passed.\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,248 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
#ifndef CONFIG_TQM_BIGFLASH |
||||
/*
|
||||
* TLB 0, 1: 128M Non-cacheable, guarded |
||||
* 0xf8000000 128M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_64M, 1), |
||||
SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000, |
||||
CFG_FLASH_BASE + 0x4000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M PCI express MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M PCI express MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000, |
||||
CFG_PCIE1_MEM_BASE + 0x10000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_256M, 1), |
||||
#else /* !CONFIG_PCIE */ |
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000, |
||||
CFG_RIO_MEM_BASE + 0x10000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_256M, 1), |
||||
#endif /* CONFIG_PCIE */ |
||||
|
||||
/*
|
||||
* TLB 6: 64M Non-cacheable, guarded |
||||
* 0xe0000000 1M CCSRBAR |
||||
* 0xe2000000 16M PCI1 IO |
||||
* 0xe3000000 16M CAN and NAND Flash |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7+8: 512M DDR, cache disabled (needed for memory test) |
||||
* 0x00000000 512M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, |
||||
CFG_DDR_SDRAM_BASE + 0x10000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 8, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
/*
|
||||
* TLB 9: 16M Non-cacheable, guarded |
||||
* 0xef000000 16M PCI express IO |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 9, BOOKE_PAGESZ_16M, 1), |
||||
#endif /* CONFIG_PCIE */ |
||||
|
||||
#else /* CONFIG_TQM_BIGFLASH */ |
||||
|
||||
/*
|
||||
* TLB 0,1,2,3: 1G Non-cacheable, guarded |
||||
* 0xc0000000 1G FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000, |
||||
CFG_FLASH_BASE + 0x10000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000, |
||||
CFG_FLASH_BASE + 0x20000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000, |
||||
CFG_FLASH_BASE + 0x30000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
/*
|
||||
* TLB 6: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M PCI express MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_256M, 1), |
||||
#else /* !CONFIG_PCIE */ |
||||
/*
|
||||
* TLB 6: 256M Non-cacheable, guarded |
||||
* 0xb0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
#endif /* CONFIG_PCIE */ |
||||
|
||||
/*
|
||||
* TLB 7: 64M Non-cacheable, guarded |
||||
* 0xa0000000 1M CCSRBAR |
||||
* 0xa2000000 16M PCI1 IO |
||||
* 0xa3000000 16M CAN and NAND Flash |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 8+9: 512M DDR, cache disabled (needed for memory test) |
||||
* 0x00000000 512M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 8, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, |
||||
CFG_DDR_SDRAM_BASE + 0x10000000, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 9, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
/*
|
||||
* TLB 10: 16M Non-cacheable, guarded |
||||
* 0xaf000000 16M PCI express IO |
||||
*/ |
||||
SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, |
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
||||
0, 10, BOOKE_PAGESZ_16M, 1), |
||||
#endif /* CONFIG_PCIE */ |
||||
|
||||
#endif /* CONFIG_TQM_BIGFLASH */ |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE (tlb_table); |
||||
@ -0,0 +1,744 @@ |
||||
/*
|
||||
* (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> |
||||
* |
||||
* (C) Copyright 2006 |
||||
* Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de. |
||||
* |
||||
* (C) Copyright 2005 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* (C) Copyright 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao, (X.Xiao@motorola.com) |
||||
* |
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/immap_fsl_pci.h> |
||||
#include <asm/io.h> |
||||
#include <ioports.h> |
||||
#include <flash.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
extern flash_info_t flash_info[]; /* FLASH chips info */ |
||||
|
||||
void local_bus_init (void); |
||||
ulong flash_get_size (ulong base, int banknum); |
||||
|
||||
#ifdef CONFIG_PS2MULT |
||||
void ps2mult_early_init (void); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CPM2 |
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
*/ |
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
|
||||
/* Port A: conf, ppar, psor, pdir, podr, pdat */ |
||||
{ |
||||
{1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */ |
||||
{1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */ |
||||
{1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */ |
||||
{1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */ |
||||
{1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */ |
||||
{1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */ |
||||
{0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */ |
||||
{0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */ |
||||
{0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */ |
||||
{0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */ |
||||
{1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */ |
||||
{1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */ |
||||
{1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */ |
||||
{1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */ |
||||
{1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */ |
||||
{1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */ |
||||
{1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */ |
||||
{1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */ |
||||
{0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */ |
||||
{0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */ |
||||
{0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */ |
||||
{0, 0, 0, 1, 0, 0} /* PA0 : PA0 */ |
||||
}, |
||||
|
||||
/* Port B: conf, ppar, psor, pdir, podr, pdat */ |
||||
{ |
||||
{1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */ |
||||
{1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */ |
||||
{0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */ |
||||
{0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */ |
||||
{0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */ |
||||
{0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */ |
||||
}, |
||||
|
||||
/* Port C: conf, ppar, psor, pdir, podr, pdat */ |
||||
{ |
||||
{0, 0, 0, 1, 0, 0}, /* PC31: PC31 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC30: PC30 */ |
||||
{0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC28: PC28 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC26: PC26 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC25: PC25 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC24: PC24 */ |
||||
{0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */ |
||||
{0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */ |
||||
{1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */ |
||||
{1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */ |
||||
{1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */ |
||||
{1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */ |
||||
{1, 1, 0, 0, 0, 0}, /* PC17: PC17 */ |
||||
{1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */ |
||||
{0, 1, 0, 0, 0, 0}, /* PC15: PC15 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */ |
||||
{0, 1, 0, 0, 0, 0}, /* PC13: PC13 */ |
||||
{0, 1, 0, 1, 0, 0}, /* PC12: PC12 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */ |
||||
{0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */ |
||||
{0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */ |
||||
}, |
||||
|
||||
/* Port D: conf, ppar, psor, pdir, podr, pdat */ |
||||
{ |
||||
#ifdef CONFIG_TQM8560 |
||||
{1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */ |
||||
{1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */ |
||||
{1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */ |
||||
#else /* !CONFIG_TQM8560 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD31: PD31 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD30: PD30 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD29: PD29 */ |
||||
#endif /* CONFIG_TQM8560 */ |
||||
{1, 1, 0, 0, 0, 0}, /* PD28: PD28 */ |
||||
{1, 1, 0, 1, 0, 0}, /* PD27: PD27 */ |
||||
{1, 1, 0, 1, 0, 0}, /* PD26: PD26 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD25: PD25 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD24: PD24 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD23: PD23 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD22: PD22 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD21: PD21 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD20: PD20 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD19: PD19 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD18: PD18 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */ |
||||
{0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */ |
||||
{0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD14: LED */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD13: PD13 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD12: PD12 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD11: PD11 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD10: PD10 */ |
||||
{0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */ |
||||
{0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */ |
||||
{0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */ |
||||
} |
||||
}; |
||||
#endif /* CONFIG_CPM2 */ |
||||
|
||||
#define CASL_STRING1 "casl=xx" |
||||
#define CASL_STRING2 "casl=" |
||||
|
||||
static const int casl_table[] = { 20, 25, 30 }; |
||||
#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) |
||||
|
||||
int cas_latency (void) |
||||
{ |
||||
char *s = getenv ("serial#"); |
||||
int casl; |
||||
int val; |
||||
int i; |
||||
|
||||
casl = CONFIG_DDR_DEFAULT_CL; |
||||
|
||||
if (s != NULL) { |
||||
if (strncmp(s + strlen (s) - strlen (CASL_STRING1), |
||||
CASL_STRING2, strlen (CASL_STRING2)) == 0) { |
||||
val = simple_strtoul (s + strlen (s) - 2, NULL, 10); |
||||
|
||||
for (i = 0; i < N_CASL; ++i) { |
||||
if (val == casl_table[i]) { |
||||
return val; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
return casl; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
char *s = getenv ("serial#"); |
||||
|
||||
printf ("Board: %s", CONFIG_BOARDNAME); |
||||
if (s != NULL) { |
||||
puts (", serial# "); |
||||
puts (s); |
||||
} |
||||
putc ('\n'); |
||||
|
||||
/*
|
||||
* Initialize local bus. |
||||
*/ |
||||
local_bus_init (); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
|
||||
/*
|
||||
* Adjust flash start and offset to detected values |
||||
*/ |
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
||||
gd->bd->bi_flashoffset = 0; |
||||
|
||||
/*
|
||||
* Recalculate CS configuration if second FLASH bank is available |
||||
*/ |
||||
if (flash_info[0].size > 0) { |
||||
memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | |
||||
(CFG_OR1_PRELIM & 0x00007fff); |
||||
memctl->br1 = gd->bd->bi_flashstart | |
||||
(CFG_BR1_PRELIM & 0x00007fff); |
||||
/*
|
||||
* Re-check to get correct base address for bank 1 |
||||
*/ |
||||
flash_get_size (gd->bd->bi_flashstart, 0); |
||||
} else { |
||||
memctl->or1 = 0; |
||||
memctl->br1 = 0; |
||||
} |
||||
|
||||
/*
|
||||
* If bank 1 is equipped, bank 0 is mapped after bank 1 |
||||
*/ |
||||
memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | |
||||
(CFG_OR0_PRELIM & 0x00007fff); |
||||
memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | |
||||
(CFG_BR0_PRELIM & 0x00007fff); |
||||
/*
|
||||
* Re-check to get correct base address for bank 0 |
||||
*/ |
||||
flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1); |
||||
|
||||
/*
|
||||
* Re-do flash protection upon new addresses |
||||
*/ |
||||
flash_protect (FLAG_PROTECT_CLEAR, |
||||
gd->bd->bi_flashstart, 0xffffffff, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Monitor protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE + monitor_flash_len - 1, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Environment protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
|
||||
#ifdef CFG_ENV_ADDR_REDUND |
||||
/* Redundant environment protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR_REDUND, |
||||
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CAN_DRIVER |
||||
/*
|
||||
* Initialize UPMC RAM |
||||
*/ |
||||
static void upmc_write (u_char addr, uint val) |
||||
{ |
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
|
||||
out_be32 (&lbc->mdr, val); |
||||
|
||||
clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK, |
||||
MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); |
||||
|
||||
/* dummy access to perform write */ |
||||
out_8 ((void __iomem *)CFG_CAN_BASE, 0); |
||||
|
||||
/* normal operation */ |
||||
clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); |
||||
} |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
uint get_lbc_clock (void) |
||||
{ |
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
sys_info_t sys_info; |
||||
ulong clkdiv = lbc->lcrr & 0x0f; |
||||
|
||||
get_sys_info (&sys_info); |
||||
|
||||
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { |
||||
#ifdef CONFIG_MPC8548 |
||||
/*
|
||||
* Yes, the entire PQ38 family use the same |
||||
* bit-representation for twice the clock divider value. |
||||
*/ |
||||
clkdiv *= 2; |
||||
#endif |
||||
return sys_info.freqSystemBus / clkdiv; |
||||
} |
||||
|
||||
puts("Invalid clock divider value in CFG_LBC_LCRR\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Initialize Local Bus |
||||
*/ |
||||
void local_bus_init (void) |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
uint lbc_mhz = get_lbc_clock () / 1000000; |
||||
|
||||
#ifdef CONFIG_MPC8548 |
||||
uint svr = get_svr (); |
||||
uint lcrr; |
||||
|
||||
/*
|
||||
* MPC revision < 2.0 |
||||
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1: |
||||
* Modify engineering use only register at address 0xE_0F20. |
||||
* "1. Read register at offset 0xE_0F20 |
||||
* 2. And value with 0x0000_FFFF |
||||
* 3. OR result with 0x0000_0004 |
||||
* 4. Write result back to offset 0xE_0F20." |
||||
* |
||||
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2: |
||||
* Modify engineering use only register at address 0xE_0F20. |
||||
* "1. Read register at offset 0xE_0F20 |
||||
* 2. And value with 0xFFFF_FFDF |
||||
* 3. Write result back to offset 0xE_0F20." |
||||
* |
||||
* Since it is the same register, we do the modification in one step. |
||||
*/ |
||||
if (SVR_MAJ (svr) < 2) { |
||||
uint dummy = gur->lbiuiplldcr1; |
||||
dummy &= 0x0000FFDF; |
||||
dummy |= 0x00000004; |
||||
gur->lbiuiplldcr1 = dummy; |
||||
} |
||||
|
||||
lcrr = CFG_LBC_LCRR; |
||||
|
||||
/*
|
||||
* Local Bus Clock > 83.3 MHz. According to timing |
||||
* specifications set LCRR[EADC] to 2 delay cycles. |
||||
*/ |
||||
if (lbc_mhz > 83) { |
||||
lcrr &= ~LCRR_EADC; |
||||
lcrr |= LCRR_EADC_2; |
||||
} |
||||
|
||||
/*
|
||||
* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 |
||||
* disable PLL bypass for Local Bus Clock > 83 MHz. |
||||
*/ |
||||
if (lbc_mhz >= 66) |
||||
lcrr &= (~LCRR_DBYP); /* DLL Enabled */ |
||||
|
||||
else |
||||
lcrr |= LCRR_DBYP; /* DLL Bypass */ |
||||
|
||||
lbc->lcrr = lcrr; |
||||
asm ("sync;isync;msync"); |
||||
|
||||
/*
|
||||
* According to MPC8548ERMAD Rev.1.3 read back LCRR |
||||
* and terminate with isync |
||||
*/ |
||||
lcrr = lbc->lcrr; |
||||
asm ("isync;"); |
||||
|
||||
/* let DLL stabilize */ |
||||
udelay (500); |
||||
|
||||
#else /* !CONFIG_MPC8548 */ |
||||
|
||||
/*
|
||||
* Errata LBC11. |
||||
* Fix Local Bus clock glitch when DLL is enabled. |
||||
* |
||||
* If localbus freq is < 66Mhz, DLL bypass mode must be used. |
||||
* If localbus freq is > 133Mhz, DLL can be safely enabled. |
||||
* Between 66 and 133, the DLL is enabled with an override workaround. |
||||
*/ |
||||
|
||||
if (lbc_mhz < 66) { |
||||
lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ |
||||
lbc->ltedr = 0xa4c80000; /* DK: !!! */ |
||||
|
||||
} else if (lbc_mhz >= 133) { |
||||
lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
||||
|
||||
} else { |
||||
/*
|
||||
* On REV1 boards, need to change CLKDIV before enable DLL. |
||||
* Default CLKDIV is 8, change it to 4 temporarily. |
||||
*/ |
||||
uint pvr = get_pvr (); |
||||
uint temp_lbcdll = 0; |
||||
|
||||
if (pvr == PVR_85xx_REV1) { |
||||
/* FIXME: Justify the high bit here. */ |
||||
lbc->lcrr = 0x10000004; |
||||
} |
||||
|
||||
lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
||||
udelay (200); |
||||
|
||||
/*
|
||||
* Sample LBC DLL ctrl reg, upshift it to set the |
||||
* override bits. |
||||
*/ |
||||
temp_lbcdll = gur->lbcdllcr; |
||||
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
||||
asm ("sync;isync;msync"); |
||||
} |
||||
#endif /* !CONFIG_MPC8548 */ |
||||
|
||||
#ifdef CONFIG_CAN_DRIVER |
||||
/*
|
||||
* According to timing specifications EAD must be |
||||
* set if Local Bus Clock is > 83 MHz. |
||||
*/ |
||||
if (lbc_mhz > 83) |
||||
out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD); |
||||
else |
||||
out_be32 (&lbc->or2, CFG_OR2_CAN); |
||||
out_be32 (&lbc->br2, CFG_BR2_CAN); |
||||
|
||||
/* LGPL4 is UPWAIT */ |
||||
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); |
||||
|
||||
/* Initialize UPMC for CAN: single read */ |
||||
upmc_write (0x00, 0xFFFFED00); |
||||
upmc_write (0x01, 0xCCFFCC00); |
||||
upmc_write (0x02, 0x00FFCF00); |
||||
upmc_write (0x03, 0x00FFCF00); |
||||
upmc_write (0x04, 0x00FFDC00); |
||||
upmc_write (0x05, 0x00FFCF00); |
||||
upmc_write (0x06, 0x00FFED00); |
||||
upmc_write (0x07, 0x3FFFCC07); |
||||
|
||||
/* Initialize UPMC for CAN: single write */ |
||||
upmc_write (0x18, 0xFFFFED00); |
||||
upmc_write (0x19, 0xCCFFEC00); |
||||
upmc_write (0x1A, 0x00FFED80); |
||||
upmc_write (0x1B, 0x00FFED80); |
||||
upmc_write (0x1C, 0x00FFFC00); |
||||
upmc_write (0x1D, 0x0FFFEC00); |
||||
upmc_write (0x1E, 0x0FFFEF00); |
||||
upmc_write (0x1F, 0x3FFFEC05); |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
} |
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found. |
||||
*/ |
||||
static int first_free_busno; |
||||
|
||||
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) |
||||
static struct pci_controller pci1_hose; |
||||
#endif /* CONFIG_PCI || CONFIG_PCI1 */ |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
static struct pci_controller pcie1_hose; |
||||
#endif /* CONFIG_PCIE1 */ |
||||
|
||||
static inline void init_pci1(void) |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) |
||||
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; |
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR; |
||||
extern void fsl_pci_init(struct pci_controller *hose); |
||||
struct pci_controller *hose = &pci1_hose; |
||||
|
||||
/* PORDEVSR[15] */ |
||||
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; |
||||
/* PORDEVSR[14] */ |
||||
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; |
||||
/* PORPLLSR[16] */ |
||||
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; |
||||
|
||||
uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || |
||||
(host_agent == 6); |
||||
|
||||
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ |
||||
|
||||
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { |
||||
printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n", |
||||
(pci_32) ? 32 : 64, |
||||
(pci_speed == 33333333) ? "33" : |
||||
(pci_speed == 66666666) ? "66" : "unknown", |
||||
pci_clk_sel ? "sync" : "async", |
||||
pci_agent ? "agent" : "host", |
||||
pci_arb ? "arbiter" : "external-arbiter"); |
||||
|
||||
|
||||
/* inbound */ |
||||
pci_set_region (hose->regions + 0, |
||||
CFG_PCI_MEMORY_BUS, |
||||
CFG_PCI_MEMORY_PHYS, |
||||
CFG_PCI_MEMORY_SIZE, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
|
||||
/* outbound memory */ |
||||
pci_set_region (hose->regions + 1, |
||||
CFG_PCI1_MEM_BASE, |
||||
CFG_PCI1_MEM_PHYS, |
||||
CFG_PCI1_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* outbound io */ |
||||
pci_set_region (hose->regions + 2, |
||||
CFG_PCI1_IO_BASE, |
||||
CFG_PCI1_IO_PHYS, |
||||
CFG_PCI1_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = 3; |
||||
|
||||
hose->first_busno = first_free_busno; |
||||
pci_setup_indirect (hose, (int)&pci->cfg_addr, |
||||
(int)&pci->cfg_data); |
||||
|
||||
fsl_pci_init (hose); |
||||
|
||||
printf (" PCI on bus %02x..%02x\n", |
||||
hose->first_busno, hose->last_busno); |
||||
|
||||
first_free_busno = hose->last_busno + 1; |
||||
#ifdef CONFIG_PCIX_CHECK |
||||
if (!(gur->pordevsr & PORDEVSR_PCI)) { |
||||
ushort reg16 = |
||||
PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | |
||||
PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; |
||||
uint dev = PCI_BDF(hose->first_busno, 0, 0); |
||||
|
||||
/* PCI-X init */ |
||||
if (CONFIG_SYS_CLK_FREQ < 66000000) |
||||
puts ("PCI-X will only work at 66 MHz\n"); |
||||
|
||||
pci_hose_write_config_word (hose, dev, PCIX_COMMAND, |
||||
reg16); |
||||
} |
||||
#endif |
||||
} else { |
||||
puts ("PCI1: disabled\n"); |
||||
} |
||||
#else /* !(CONFIG_PCI || CONFIG_PCI1) */ |
||||
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ |
||||
#endif /* CONFIG_PCI || CONFIG_PCI1) */ |
||||
} |
||||
|
||||
static inline void init_pcie1(void) |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
#ifdef CONFIG_PCIE1 |
||||
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; |
||||
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; |
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR; |
||||
extern void fsl_pci_init(struct pci_controller *hose); |
||||
struct pci_controller *hose = &pcie1_hose; |
||||
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || |
||||
(host_agent == 3); |
||||
|
||||
int pcie_configured = io_sel >= 1; |
||||
|
||||
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ |
||||
printf ("PCIe: %s, base address %x", |
||||
pcie_ep ? "End point" : "Root complex", (uint)pci); |
||||
|
||||
if (pci->pme_msg_det) { |
||||
pci->pme_msg_det = 0xffffffff; |
||||
debug (", with errors. Clearing. Now 0x%08x", |
||||
pci->pme_msg_det); |
||||
} |
||||
puts ("\n"); |
||||
|
||||
/* inbound */ |
||||
pci_set_region (hose->regions + 0, |
||||
CFG_PCI_MEMORY_BUS, |
||||
CFG_PCI_MEMORY_PHYS, |
||||
CFG_PCI_MEMORY_SIZE, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
/* outbound memory */ |
||||
pci_set_region (hose->regions + 1, |
||||
CFG_PCIE1_MEM_BASE, |
||||
CFG_PCIE1_MEM_PHYS, |
||||
CFG_PCIE1_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* outbound io */ |
||||
pci_set_region (hose->regions + 2, |
||||
CFG_PCIE1_IO_BASE, |
||||
CFG_PCIE1_IO_PHYS, |
||||
CFG_PCIE1_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = 3; |
||||
|
||||
hose->first_busno = first_free_busno; |
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr, |
||||
(int)&pci->cfg_data); |
||||
|
||||
fsl_pci_init (hose); |
||||
printf (" PCIe on bus %02x..%02x\n", |
||||
hose->first_busno, hose->last_busno); |
||||
|
||||
first_free_busno = hose->last_busno + 1; |
||||
|
||||
} else { |
||||
printf ("PCIe: disabled\n"); |
||||
} |
||||
#else /* !CONFIG_PCIE1 */ |
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ |
||||
#endif /* CONFIG_PCIE1 */ |
||||
} |
||||
|
||||
void pci_init_board (void) |
||||
{ |
||||
init_pci1(); |
||||
init_pcie1(); |
||||
} |
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP |
||||
void ft_board_setup (void *blob, bd_t *bd) |
||||
{ |
||||
int node, tmp[2]; |
||||
const char *path; |
||||
|
||||
ft_cpu_setup (blob, bd); |
||||
|
||||
node = fdt_path_offset (blob, "/aliases"); |
||||
tmp[0] = 0; |
||||
if (node >= 0) { |
||||
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) |
||||
path = fdt_getprop (blob, node, "pci0", NULL); |
||||
if (path) { |
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; |
||||
do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); |
||||
} |
||||
#endif /* CONFIG_PCI || CONFIG_PCI1 */ |
||||
#ifdef CONFIG_PCIE1 |
||||
path = fdt_getprop (blob, node, "pci1", NULL); |
||||
if (path) { |
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; |
||||
do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); |
||||
} |
||||
#endif /* CONFIG_PCIE1 */ |
||||
} |
||||
} |
||||
#endif /* CONFIG_OF_BOARD_SETUP */ |
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_R |
||||
int board_early_init_r (void) |
||||
{ |
||||
#ifdef CONFIG_PS2MULT |
||||
ps2mult_early_init (); |
||||
#endif /* CONFIG_PS2MULT */ |
||||
return (0); |
||||
} |
||||
#endif /* CONFIG_BOARD_EARLY_INIT_R */ |
||||
@ -1,54 +0,0 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -1,223 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct sdram_conf_s { |
||||
unsigned long size; |
||||
unsigned long reg; |
||||
}; |
||||
|
||||
typedef struct sdram_conf_s sdram_conf_t; |
||||
|
||||
sdram_conf_t ddr_cs_conf[] = { |
||||
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ |
||||
{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ |
||||
{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ |
||||
{(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ |
||||
}; |
||||
|
||||
#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) |
||||
|
||||
int cas_latency(void); |
||||
|
||||
/*
|
||||
* Autodetect onboard DDR SDRAM on 85xx platforms |
||||
* |
||||
* NOTE: Some of the hardcoded values are hardware dependant, |
||||
* so this should be extended for other future boards |
||||
* using this routine! |
||||
*/ |
||||
long int sdram_setup(int casl) |
||||
{ |
||||
int i; |
||||
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); |
||||
unsigned long cfg_ddr_timing1; |
||||
unsigned long cfg_ddr_mode; |
||||
|
||||
/*
|
||||
* Disable memory controller. |
||||
*/ |
||||
ddr->cs0_config = 0; |
||||
ddr->sdram_cfg = 0; |
||||
|
||||
switch (casl) { |
||||
case 20: |
||||
cfg_ddr_timing1 = 0x47405331 | (3 << 16); |
||||
cfg_ddr_mode = 0x40020002 | (2 << 4); |
||||
break; |
||||
|
||||
case 25: |
||||
cfg_ddr_timing1 = 0x47405331 | (4 << 16); |
||||
cfg_ddr_mode = 0x40020002 | (6 << 4); |
||||
break; |
||||
|
||||
case 30: |
||||
default: |
||||
cfg_ddr_timing1 = 0x47405331 | (5 << 16); |
||||
cfg_ddr_mode = 0x40020002 | (3 << 4); |
||||
break; |
||||
} |
||||
|
||||
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; |
||||
ddr->cs0_config = ddr_cs_conf[0].reg; |
||||
ddr->timing_cfg_1 = cfg_ddr_timing1; |
||||
ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ |
||||
ddr->sdram_mode = cfg_ddr_mode; |
||||
ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ |
||||
ddr->err_disable = 0x0000000D; |
||||
|
||||
asm ("sync;isync;msync"); |
||||
udelay(1000); |
||||
|
||||
ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ |
||||
asm ("sync; isync; msync"); |
||||
udelay(1000); |
||||
|
||||
for (i=0; i<N_DDR_CS_CONF; i++) { |
||||
ddr->cs0_config = ddr_cs_conf[i].reg; |
||||
|
||||
if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) { |
||||
/*
|
||||
* OK, size detected -> all done |
||||
*/ |
||||
return ddr_cs_conf[i].size; |
||||
} |
||||
} |
||||
|
||||
return 0; /* nothing found ! */ |
||||
} |
||||
|
||||
void board_add_ram_info(int use_default) |
||||
{ |
||||
int casl; |
||||
|
||||
if (use_default) |
||||
casl = CONFIG_DDR_DEFAULT_CL; |
||||
else |
||||
casl = cas_latency(); |
||||
|
||||
puts(" (CL="); |
||||
switch (casl) { |
||||
case 20: |
||||
puts("2)"); |
||||
break; |
||||
|
||||
case 25: |
||||
puts("2.5)"); |
||||
break; |
||||
|
||||
case 30: |
||||
puts("3)"); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
int casl; |
||||
|
||||
#if defined(CONFIG_DDR_DLL) |
||||
/*
|
||||
* This DLL-Override only used on TQM8540 and TQM8560 |
||||
*/ |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
int i,x; |
||||
|
||||
x = 10; |
||||
|
||||
/*
|
||||
* Work around to stabilize DDR DLL |
||||
*/ |
||||
gur->ddrdllcr = 0x81000000; |
||||
asm("sync;isync;msync"); |
||||
udelay (200); |
||||
while (gur->ddrdllcr != 0x81000100) { |
||||
gur->devdisr = gur->devdisr | 0x00010000; |
||||
asm("sync;isync;msync"); |
||||
for (i=0; i<x; i++) |
||||
; |
||||
gur->devdisr = gur->devdisr & 0xfff7ffff; |
||||
asm("sync;isync;msync"); |
||||
x++; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
casl = cas_latency(); |
||||
dram_size = sdram_setup(casl); |
||||
if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { |
||||
/*
|
||||
* Try again with default CAS latency |
||||
*/ |
||||
puts("Problem with CAS lantency"); |
||||
board_add_ram_info(1); |
||||
puts(", using default CL!\n"); |
||||
casl = CONFIG_DDR_DEFAULT_CL; |
||||
dram_size = sdram_setup(casl); |
||||
puts(" "); |
||||
} |
||||
|
||||
return dram_size; |
||||
} |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) CFG_MEMTEST_START; |
||||
uint *pend = (uint *) CFG_MEMTEST_END; |
||||
uint *p; |
||||
|
||||
printf ("SDRAM test phase 1:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf ("SDRAM test phase 2:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf ("SDRAM test passed.\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -1,114 +0,0 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
|
||||
/*
|
||||
* TLB 0, 1: 128M Non-cacheable, guarded |
||||
* 0xf8000000 128M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_64M, 1), |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7+8: 512M DDR, cache disabled (needed for memory test) |
||||
* 0x00000000 512M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 8, BOOKE_PAGESZ_256M, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,419 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* (C) Copyright 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao, (X.Xiao@motorola.com) |
||||
* |
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <ioports.h> |
||||
#include <flash.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
extern flash_info_t flash_info[]; /* FLASH chips info */ |
||||
|
||||
void local_bus_init (void); |
||||
ulong flash_get_size (ulong base, int banknum); |
||||
|
||||
#ifdef CONFIG_PS2MULT |
||||
void ps2mult_early_init(void); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CPM2 |
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
*/ |
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
|
||||
/* Port A configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ |
||||
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ |
||||
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ |
||||
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ |
||||
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ |
||||
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ |
||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
||||
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ |
||||
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ |
||||
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ |
||||
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ |
||||
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ |
||||
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ |
||||
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ |
||||
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ |
||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
||||
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
||||
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ |
||||
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ |
||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
||||
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ |
||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
||||
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ |
||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
||||
}, |
||||
|
||||
/* Port B configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
||||
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
||||
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
||||
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
||||
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
||||
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
||||
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
||||
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
}, |
||||
|
||||
/* Port C */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ |
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ |
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ |
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
||||
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
||||
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ |
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ |
||||
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ |
||||
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ |
||||
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ |
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
||||
/* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ |
||||
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ |
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ |
||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ |
||||
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ |
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
||||
}, |
||||
|
||||
/* Port D */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
||||
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
||||
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
||||
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ |
||||
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ |
||||
/* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ |
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ |
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ |
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ |
||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ |
||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ |
||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ |
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ |
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ |
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
||||
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
||||
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ |
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ |
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
} |
||||
}; |
||||
#endif /* CONFIG_CPM2 */ |
||||
|
||||
#define CASL_STRING1 "casl=xx" |
||||
#define CASL_STRING2 "casl=" |
||||
|
||||
static const int casl_table[] = { 20, 25, 30 }; |
||||
#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) |
||||
|
||||
int cas_latency(void) |
||||
{ |
||||
char *s = getenv("serial#"); |
||||
int casl; |
||||
int val; |
||||
int i; |
||||
|
||||
casl = CONFIG_DDR_DEFAULT_CL; |
||||
|
||||
if (s != NULL) { |
||||
if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2, |
||||
strlen(CASL_STRING2)) == 0) { |
||||
val = simple_strtoul(s + strlen(s) - 2, NULL, 10); |
||||
|
||||
for (i=0; i<N_CASL; ++i) { |
||||
if (val == casl_table[i]) { |
||||
return val; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
return casl; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
char *s = getenv("serial#"); |
||||
|
||||
printf("Board: %s", CONFIG_BOARDNAME); |
||||
if (s != NULL) { |
||||
puts(", serial# "); |
||||
puts(s); |
||||
} |
||||
putc('\n'); |
||||
|
||||
#ifdef CONFIG_PCI |
||||
printf ("PCI1: 32 bit, %d MHz (compiled)\n", |
||||
CONFIG_SYS_CLK_FREQ / 1000000); |
||||
#else |
||||
printf ("PCI1: disabled\n"); |
||||
#endif |
||||
|
||||
/*
|
||||
* Initialize local bus. |
||||
*/ |
||||
local_bus_init (); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
|
||||
/*
|
||||
* Adjust flash start and offset to detected values |
||||
*/ |
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
||||
gd->bd->bi_flashoffset = 0; |
||||
|
||||
/*
|
||||
* Check if boot FLASH isn't max size |
||||
*/ |
||||
if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { |
||||
memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); |
||||
memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); |
||||
|
||||
/*
|
||||
* Re-check to get correct base address |
||||
*/ |
||||
flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); |
||||
} |
||||
|
||||
/*
|
||||
* Check if only one FLASH bank is available |
||||
*/ |
||||
if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { |
||||
memctl->or1 = 0; |
||||
memctl->br1 = 0; |
||||
|
||||
/*
|
||||
* Re-do flash protection upon new addresses |
||||
*/ |
||||
flash_protect (FLAG_PROTECT_CLEAR, |
||||
gd->bd->bi_flashstart, 0xffffffff, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Monitor protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Environment protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Redundant environment protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR_REDUND, |
||||
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Initialize Local Bus |
||||
*/ |
||||
void local_bus_init (void) |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
|
||||
uint clkdiv; |
||||
uint lbc_hz; |
||||
sys_info_t sysinfo; |
||||
|
||||
/*
|
||||
* Errata LBC11. |
||||
* Fix Local Bus clock glitch when DLL is enabled. |
||||
* |
||||
* If localbus freq is < 66Mhz, DLL bypass mode must be used. |
||||
* If localbus freq is > 133Mhz, DLL can be safely enabled. |
||||
* Between 66 and 133, the DLL is enabled with an override workaround. |
||||
*/ |
||||
|
||||
get_sys_info (&sysinfo); |
||||
clkdiv = lbc->lcrr & 0x0f; |
||||
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
||||
|
||||
if (lbc_hz < 66) { |
||||
lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ |
||||
lbc->ltedr = 0xa4c80000; /* DK: !!! */ |
||||
|
||||
} else if (lbc_hz >= 133) { |
||||
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ |
||||
|
||||
} else { |
||||
/*
|
||||
* On REV1 boards, need to change CLKDIV before enable DLL. |
||||
* Default CLKDIV is 8, change it to 4 temporarily. |
||||
*/ |
||||
uint pvr = get_pvr (); |
||||
uint temp_lbcdll = 0; |
||||
|
||||
if (pvr == PVR_85xx_REV1) { |
||||
/* FIXME: Justify the high bit here. */ |
||||
lbc->lcrr = 0x10000004; |
||||
} |
||||
|
||||
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ |
||||
udelay (200); |
||||
|
||||
/*
|
||||
* Sample LBC DLL ctrl reg, upshift it to set the |
||||
* override bits. |
||||
*/ |
||||
temp_lbcdll = gur->lbcdllcr; |
||||
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
||||
asm ("sync;isync;msync"); |
||||
} |
||||
} |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
/*
|
||||
* Initialize PCI Devices, report devices found. |
||||
*/ |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_mpc85xxads_config_table[] = { |
||||
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | |
||||
PCI_COMMAND_MASTER}}, |
||||
{} |
||||
}; |
||||
#endif |
||||
|
||||
|
||||
static struct pci_controller hose = { |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc85xxads_config_table, |
||||
#endif |
||||
}; |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
void pci_init_board (void) |
||||
{ |
||||
#ifdef CONFIG_PCI |
||||
pci_mpc85xx_init (&hose); |
||||
#endif /* CONFIG_PCI */ |
||||
} |
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_R |
||||
int board_early_init_r (void) |
||||
{ |
||||
#ifdef CONFIG_PS2MULT |
||||
ps2mult_early_init(); |
||||
#endif /* CONFIG_PS2MULT */ |
||||
return (0); |
||||
} |
||||
#endif /* CONFIG_BOARD_EARLY_INIT_R */ |
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in new issue