Tom Rini
6 years ago
commit
606fddd76c
@ -0,0 +1,995 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/**
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* sni_ave.c - Socionext UniPhier AVE ethernet driver |
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* Copyright 2016-2018 Socionext inc. |
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*/ |
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#include <clk.h> |
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#include <dm.h> |
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#include <fdt_support.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <miiphy.h> |
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#include <net.h> |
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#include <regmap.h> |
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#include <reset.h> |
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#include <syscon.h> |
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#define AVE_GRST_DELAY_MSEC 40 |
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#define AVE_MIN_XMITSIZE 60 |
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#define AVE_SEND_TIMEOUT_COUNT 1000 |
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#define AVE_MDIO_TIMEOUT_USEC 10000 |
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#define AVE_HALT_TIMEOUT_USEC 10000 |
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/* General Register Group */ |
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#define AVE_IDR 0x000 /* ID */ |
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#define AVE_VR 0x004 /* Version */ |
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#define AVE_GRR 0x008 /* Global Reset */ |
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#define AVE_CFGR 0x00c /* Configuration */ |
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/* Interrupt Register Group */ |
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#define AVE_GIMR 0x100 /* Global Interrupt Mask */ |
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#define AVE_GISR 0x104 /* Global Interrupt Status */ |
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/* MAC Register Group */ |
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#define AVE_TXCR 0x200 /* TX Setup */ |
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#define AVE_RXCR 0x204 /* RX Setup */ |
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#define AVE_RXMAC1R 0x208 /* MAC address (lower) */ |
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#define AVE_RXMAC2R 0x20c /* MAC address (upper) */ |
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#define AVE_MDIOCTR 0x214 /* MDIO Control */ |
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#define AVE_MDIOAR 0x218 /* MDIO Address */ |
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#define AVE_MDIOWDR 0x21c /* MDIO Data */ |
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#define AVE_MDIOSR 0x220 /* MDIO Status */ |
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#define AVE_MDIORDR 0x224 /* MDIO Rd Data */ |
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/* Descriptor Control Register Group */ |
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#define AVE_DESCC 0x300 /* Descriptor Control */ |
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#define AVE_TXDC 0x304 /* TX Descriptor Configuration */ |
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#define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */ |
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#define AVE_IIRQC 0x34c /* Interval IRQ Control */ |
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/* 64bit descriptor memory */ |
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#define AVE_DESC_SIZE_64 12 /* Descriptor Size */ |
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#define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */ |
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#define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */ |
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/* 32bit descriptor memory */ |
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#define AVE_DESC_SIZE_32 8 /* Descriptor Size */ |
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#define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */ |
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#define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */ |
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/* RMII Bridge Register Group */ |
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#define AVE_RSTCTRL 0x8028 /* Reset control */ |
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#define AVE_RSTCTRL_RMIIRST BIT(16) |
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#define AVE_LINKSEL 0x8034 /* Link speed setting */ |
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#define AVE_LINKSEL_100M BIT(0) |
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|
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/* AVE_GRR */ |
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#define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ |
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#define AVE_GRR_GRST BIT(0) /* Reset all MAC */ |
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/* AVE_CFGR */ |
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#define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ |
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/* AVE_GISR (common with GIMR) */ |
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#define AVE_GIMR_CLR 0 |
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#define AVE_GISR_CLR GENMASK(31, 0) |
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/* AVE_TXCR */ |
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#define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ |
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#define AVE_TXCR_TXSPD_1G BIT(17) |
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#define AVE_TXCR_TXSPD_100 BIT(16) |
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/* AVE_RXCR */ |
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#define AVE_RXCR_RXEN BIT(30) /* Rx enable */ |
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#define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ |
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#define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ |
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/* AVE_MDIOCTR */ |
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#define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ |
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#define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ |
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/* AVE_MDIOSR */ |
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#define AVE_MDIOSR_STS BIT(0) /* access status */ |
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/* AVE_DESCC */ |
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#define AVE_DESCC_RXDSTPSTS BIT(20) |
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#define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ |
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#define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */ |
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#define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ |
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/* AVE_TXDC/RXDC */ |
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#define AVE_DESC_SIZE(priv, num) \ |
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((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \
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AVE_DESC_SIZE_32)) |
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/* Command status for descriptor */ |
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#define AVE_STS_OWN BIT(31) /* Descriptor ownership */ |
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#define AVE_STS_OK BIT(27) /* Normal transmit */ |
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#define AVE_STS_1ST BIT(26) /* Head of buffer chain */ |
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#define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ |
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#define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0) |
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#define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0) |
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#define AVE_DESC_OFS_CMDSTS 0 |
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#define AVE_DESC_OFS_ADDRL 4 |
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#define AVE_DESC_OFS_ADDRU 8 |
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/* Parameter for ethernet frame */ |
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#define AVE_RXCR_MTU 1518 |
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/* SG */ |
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#define SG_ETPINMODE 0x540 |
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#define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ |
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#define SG_ETPINMODE_RMII(ins) BIT(ins) |
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#define AVE_MAX_CLKS 4 |
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#define AVE_MAX_RSTS 2 |
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enum desc_id { |
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AVE_DESCID_TX, |
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AVE_DESCID_RX, |
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}; |
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struct ave_private { |
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phys_addr_t iobase; |
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unsigned int nclks; |
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struct clk clk[AVE_MAX_CLKS]; |
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unsigned int nrsts; |
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struct reset_ctl rst[AVE_MAX_RSTS]; |
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struct regmap *regmap; |
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unsigned int regmap_arg; |
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struct mii_dev *bus; |
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struct phy_device *phydev; |
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int phy_mode; |
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int max_speed; |
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int rx_pos; |
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int rx_siz; |
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int rx_off; |
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int tx_num; |
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u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN]; |
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void *tx_adj_buf; |
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const struct ave_soc_data *data; |
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}; |
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struct ave_soc_data { |
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bool is_desc_64bit; |
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const char *clock_names[AVE_MAX_CLKS]; |
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const char *reset_names[AVE_MAX_RSTS]; |
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int (*get_pinmode)(struct ave_private *priv); |
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}; |
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static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry, |
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int offset) |
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{ |
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int desc_size; |
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u32 addr; |
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if (priv->data->is_desc_64bit) { |
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desc_size = AVE_DESC_SIZE_64; |
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addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; |
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} else { |
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desc_size = AVE_DESC_SIZE_32; |
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addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; |
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} |
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addr += entry * desc_size + offset; |
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return readl(priv->iobase + addr); |
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} |
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static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id, |
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int entry) |
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{ |
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return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS); |
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} |
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static void ave_desc_write(struct ave_private *priv, enum desc_id id, |
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int entry, int offset, u32 val) |
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{ |
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int desc_size; |
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u32 addr; |
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if (priv->data->is_desc_64bit) { |
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desc_size = AVE_DESC_SIZE_64; |
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addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; |
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} else { |
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desc_size = AVE_DESC_SIZE_32; |
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addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; |
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} |
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addr += entry * desc_size + offset; |
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writel(val, priv->iobase + addr); |
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} |
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static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id, |
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int entry, u32 val) |
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{ |
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ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val); |
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} |
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static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id, |
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int entry, uintptr_t paddr) |
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{ |
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ave_desc_write(priv, id, entry, |
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AVE_DESC_OFS_ADDRL, lower_32_bits(paddr)); |
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if (priv->data->is_desc_64bit) |
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ave_desc_write(priv, id, entry, |
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AVE_DESC_OFS_ADDRU, upper_32_bits(paddr)); |
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} |
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static void ave_cache_invalidate(uintptr_t vaddr, int len) |
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{ |
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invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), |
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roundup(vaddr + len, ARCH_DMA_MINALIGN)); |
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} |
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static void ave_cache_flush(uintptr_t vaddr, int len) |
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{ |
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flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), |
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roundup(vaddr + len, ARCH_DMA_MINALIGN)); |
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} |
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static int ave_mdiobus_read(struct mii_dev *bus, |
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int phyid, int devad, int regnum) |
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{ |
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struct ave_private *priv = bus->priv; |
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u32 mdioctl, mdiosr; |
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int ret; |
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/* write address */ |
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writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); |
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/* read request */ |
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mdioctl = readl(priv->iobase + AVE_MDIOCTR); |
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writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR); |
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ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, |
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!(mdiosr & AVE_MDIOSR_STS), |
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AVE_MDIO_TIMEOUT_USEC); |
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if (ret) { |
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pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n", |
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priv->phydev->dev->name, phyid, regnum); |
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return ret; |
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} |
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return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0); |
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} |
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static int ave_mdiobus_write(struct mii_dev *bus, |
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int phyid, int devad, int regnum, u16 val) |
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{ |
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struct ave_private *priv = bus->priv; |
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u32 mdioctl, mdiosr; |
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int ret; |
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/* write address */ |
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writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); |
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/* write data */ |
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writel(val, priv->iobase + AVE_MDIOWDR); |
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/* write request */ |
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mdioctl = readl(priv->iobase + AVE_MDIOCTR); |
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writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ, |
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priv->iobase + AVE_MDIOCTR); |
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ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, |
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!(mdiosr & AVE_MDIOSR_STS), |
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AVE_MDIO_TIMEOUT_USEC); |
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if (ret) |
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pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n", |
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priv->phydev->dev->name, phyid, regnum); |
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return ret; |
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} |
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static int ave_adjust_link(struct ave_private *priv) |
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{ |
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struct phy_device *phydev = priv->phydev; |
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struct eth_pdata *pdata = dev_get_platdata(phydev->dev); |
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u32 val, txcr, rxcr, rxcr_org; |
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u16 rmt_adv = 0, lcl_adv = 0; |
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u8 cap; |
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/* set RGMII speed */ |
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val = readl(priv->iobase + AVE_TXCR); |
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val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); |
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if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) |
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val |= AVE_TXCR_TXSPD_1G; |
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else if (phydev->speed == SPEED_100) |
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val |= AVE_TXCR_TXSPD_100; |
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writel(val, priv->iobase + AVE_TXCR); |
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/* set RMII speed (100M/10M only) */ |
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if (!phy_interface_is_rgmii(phydev)) { |
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val = readl(priv->iobase + AVE_LINKSEL); |
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if (phydev->speed == SPEED_10) |
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val &= ~AVE_LINKSEL_100M; |
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else |
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val |= AVE_LINKSEL_100M; |
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writel(val, priv->iobase + AVE_LINKSEL); |
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} |
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/* check current RXCR/TXCR */ |
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rxcr = readl(priv->iobase + AVE_RXCR); |
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txcr = readl(priv->iobase + AVE_TXCR); |
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rxcr_org = rxcr; |
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if (phydev->duplex) { |
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rxcr |= AVE_RXCR_FDUPEN; |
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if (phydev->pause) |
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rmt_adv |= LPA_PAUSE_CAP; |
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if (phydev->asym_pause) |
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rmt_adv |= LPA_PAUSE_ASYM; |
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if (phydev->advertising & ADVERTISED_Pause) |
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lcl_adv |= ADVERTISE_PAUSE_CAP; |
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if (phydev->advertising & ADVERTISED_Asym_Pause) |
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lcl_adv |= ADVERTISE_PAUSE_ASYM; |
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cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); |
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if (cap & FLOW_CTRL_TX) |
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txcr |= AVE_TXCR_FLOCTR; |
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else |
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txcr &= ~AVE_TXCR_FLOCTR; |
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if (cap & FLOW_CTRL_RX) |
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rxcr |= AVE_RXCR_FLOCTR; |
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else |
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rxcr &= ~AVE_RXCR_FLOCTR; |
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} else { |
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rxcr &= ~AVE_RXCR_FDUPEN; |
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rxcr &= ~AVE_RXCR_FLOCTR; |
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txcr &= ~AVE_TXCR_FLOCTR; |
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} |
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if (rxcr_org != rxcr) { |
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/* disable Rx mac */ |
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writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR); |
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/* change and enable TX/Rx mac */ |
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writel(txcr, priv->iobase + AVE_TXCR); |
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writel(rxcr, priv->iobase + AVE_RXCR); |
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} |
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pr_notice("%s: phy:%s speed:%d mac:%pM\n", |
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phydev->dev->name, phydev->drv->name, phydev->speed, |
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pdata->enetaddr); |
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return phydev->link; |
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} |
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static int ave_mdiobus_init(struct ave_private *priv, const char *name) |
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{ |
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struct mii_dev *bus = mdio_alloc(); |
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if (!bus) |
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return -ENOMEM; |
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bus->read = ave_mdiobus_read; |
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bus->write = ave_mdiobus_write; |
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snprintf(bus->name, sizeof(bus->name), "%s", name); |
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bus->priv = priv; |
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return mdio_register(bus); |
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} |
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static int ave_phy_init(struct ave_private *priv, void *dev) |
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{ |
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struct phy_device *phydev; |
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int mask = GENMASK(31, 0), ret; |
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phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode); |
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if (!phydev) |
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return -ENODEV; |
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phy_connect_dev(phydev, dev); |
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phydev->supported &= PHY_GBIT_FEATURES; |
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if (priv->max_speed) { |
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ret = phy_set_supported(phydev, priv->max_speed); |
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if (ret) |
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return ret; |
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} |
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phydev->advertising = phydev->supported; |
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priv->phydev = phydev; |
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phy_config(phydev); |
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return 0; |
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} |
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static void ave_stop(struct udevice *dev) |
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{ |
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struct ave_private *priv = dev_get_priv(dev); |
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u32 val; |
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int ret; |
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val = readl(priv->iobase + AVE_GRR); |
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if (val) |
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return; |
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val = readl(priv->iobase + AVE_RXCR); |
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val &= ~AVE_RXCR_RXEN; |
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writel(val, priv->iobase + AVE_RXCR); |
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writel(0, priv->iobase + AVE_DESCC); |
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ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val, |
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AVE_HALT_TIMEOUT_USEC); |
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if (ret) |
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pr_warn("%s: halt timeout\n", priv->phydev->dev->name); |
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writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); |
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phy_shutdown(priv->phydev); |
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} |
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static void ave_reset(struct ave_private *priv) |
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{ |
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u32 val; |
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/* reset RMII register */ |
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val = readl(priv->iobase + AVE_RSTCTRL); |
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val &= ~AVE_RSTCTRL_RMIIRST; |
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writel(val, priv->iobase + AVE_RSTCTRL); |
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/* assert reset */ |
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writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR); |
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mdelay(AVE_GRST_DELAY_MSEC); |
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/* 1st, negate PHY reset only */ |
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writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); |
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mdelay(AVE_GRST_DELAY_MSEC); |
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/* negate reset */ |
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writel(0, priv->iobase + AVE_GRR); |
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mdelay(AVE_GRST_DELAY_MSEC); |
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/* negate RMII register */ |
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val = readl(priv->iobase + AVE_RSTCTRL); |
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val |= AVE_RSTCTRL_RMIIRST; |
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writel(val, priv->iobase + AVE_RSTCTRL); |
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} |
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static int ave_start(struct udevice *dev) |
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{ |
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struct ave_private *priv = dev_get_priv(dev); |
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uintptr_t paddr; |
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u32 val; |
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int i; |
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ave_reset(priv); |
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priv->rx_pos = 0; |
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priv->rx_off = 2; /* RX data has 2byte offsets */ |
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priv->tx_num = 0; |
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priv->tx_adj_buf = |
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(void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0], |
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PKTALIGN); |
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priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off); |
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val = 0; |
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if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII) |
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val |= AVE_CFGR_MII; |
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writel(val, priv->iobase + AVE_CFGR); |
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/* use one descriptor for Tx */ |
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writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC); |
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ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0); |
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ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0); |
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/* use PKTBUFSRX descriptors for Rx */ |
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writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC); |
||||
for (i = 0; i < PKTBUFSRX; i++) { |
||||
paddr = (uintptr_t)net_rx_packets[i]; |
||||
ave_cache_flush(paddr, priv->rx_siz + priv->rx_off); |
||||
ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr); |
||||
ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz); |
||||
} |
||||
|
||||
writel(AVE_GISR_CLR, priv->iobase + AVE_GISR); |
||||
writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR); |
||||
|
||||
writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU, |
||||
priv->iobase + AVE_RXCR); |
||||
writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC); |
||||
|
||||
phy_startup(priv->phydev); |
||||
ave_adjust_link(priv); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ave_write_hwaddr(struct udevice *dev) |
||||
{ |
||||
struct ave_private *priv = dev_get_priv(dev); |
||||
struct eth_pdata *pdata = dev_get_platdata(dev); |
||||
u8 *mac = pdata->enetaddr; |
||||
|
||||
writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, |
||||
priv->iobase + AVE_RXMAC1R); |
||||
writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ave_send(struct udevice *dev, void *packet, int length) |
||||
{ |
||||
struct ave_private *priv = dev_get_priv(dev); |
||||
u32 val; |
||||
void *ptr = packet; |
||||
int count; |
||||
|
||||
/* adjust alignment for descriptor */ |
||||
if ((uintptr_t)ptr & 0x3) { |
||||
memcpy(priv->tx_adj_buf, (const void *)ptr, length); |
||||
ptr = priv->tx_adj_buf; |
||||
} |
||||
|
||||
/* padding for minimum length */ |
||||
if (length < AVE_MIN_XMITSIZE) { |
||||
memset(ptr + length, 0, AVE_MIN_XMITSIZE - length); |
||||
length = AVE_MIN_XMITSIZE; |
||||
} |
||||
|
||||
/* check ownership and wait for previous xmit done */ |
||||
count = AVE_SEND_TIMEOUT_COUNT; |
||||
do { |
||||
val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); |
||||
} while ((val & AVE_STS_OWN) && --count); |
||||
if (!count) |
||||
return -ETIMEDOUT; |
||||
|
||||
ave_cache_flush((uintptr_t)ptr, length); |
||||
ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr); |
||||
|
||||
val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST | |
||||
(length & AVE_STS_PKTLEN_TX_MASK); |
||||
ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val); |
||||
priv->tx_num++; |
||||
|
||||
count = AVE_SEND_TIMEOUT_COUNT; |
||||
do { |
||||
val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); |
||||
} while ((val & AVE_STS_OWN) && --count); |
||||
if (!count) |
||||
return -ETIMEDOUT; |
||||
|
||||
if (!(val & AVE_STS_OK)) |
||||
pr_warn("%s: bad send packet status:%08x\n", |
||||
priv->phydev->dev->name, le32_to_cpu(val)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ave_recv(struct udevice *dev, int flags, uchar **packetp) |
||||
{ |
||||
struct ave_private *priv = dev_get_priv(dev); |
||||
uchar *ptr; |
||||
int length = 0; |
||||
u32 cmdsts; |
||||
|
||||
while (1) { |
||||
cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX, |
||||
priv->rx_pos); |
||||
if (!(cmdsts & AVE_STS_OWN)) |
||||
/* hardware ownership, no received packets */ |
||||
return -EAGAIN; |
||||
|
||||
ptr = net_rx_packets[priv->rx_pos] + priv->rx_off; |
||||
if (cmdsts & AVE_STS_OK) |
||||
break; |
||||
|
||||
pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n", |
||||
priv->phydev->dev->name, priv->rx_pos, |
||||
le32_to_cpu(cmdsts), ptr); |
||||
} |
||||
|
||||
length = cmdsts & AVE_STS_PKTLEN_RX_MASK; |
||||
|
||||
/* invalidate after DMA is done */ |
||||
ave_cache_invalidate((uintptr_t)ptr, length); |
||||
*packetp = ptr; |
||||
|
||||
return length; |
||||
} |
||||
|
||||
static int ave_free_packet(struct udevice *dev, uchar *packet, int length) |
||||
{ |
||||
struct ave_private *priv = dev_get_priv(dev); |
||||
|
||||
ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos], |
||||
priv->rx_siz + priv->rx_off); |
||||
|
||||
ave_desc_write_cmdsts(priv, AVE_DESCID_RX, |
||||
priv->rx_pos, priv->rx_siz); |
||||
|
||||
if (++priv->rx_pos >= PKTBUFSRX) |
||||
priv->rx_pos = 0; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ave_pro4_get_pinmode(struct ave_private *priv) |
||||
{ |
||||
u32 reg, mask, val = 0; |
||||
|
||||
if (priv->regmap_arg > 0) |
||||
return -EINVAL; |
||||
|
||||
mask = SG_ETPINMODE_RMII(0); |
||||
|
||||
switch (priv->phy_mode) { |
||||
case PHY_INTERFACE_MODE_RMII: |
||||
val = SG_ETPINMODE_RMII(0); |
||||
break; |
||||
case PHY_INTERFACE_MODE_MII: |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
regmap_read(priv->regmap, SG_ETPINMODE, ®); |
||||
reg &= ~mask; |
||||
reg |= val; |
||||
regmap_write(priv->regmap, SG_ETPINMODE, reg); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ave_ld11_get_pinmode(struct ave_private *priv) |
||||
{ |
||||
u32 reg, mask, val = 0; |
||||
|
||||
if (priv->regmap_arg > 0) |
||||
return -EINVAL; |
||||
|
||||
mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); |
||||
|
||||
switch (priv->phy_mode) { |
||||
case PHY_INTERFACE_MODE_INTERNAL: |
||||
break; |
||||
case PHY_INTERFACE_MODE_RMII: |
||||
val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
regmap_read(priv->regmap, SG_ETPINMODE, ®); |
||||
reg &= ~mask; |
||||
reg |= val; |
||||
regmap_write(priv->regmap, SG_ETPINMODE, reg); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ave_ld20_get_pinmode(struct ave_private *priv) |
||||
{ |
||||
u32 reg, mask, val = 0; |
||||
|
||||
if (priv->regmap_arg > 0) |
||||
return -EINVAL; |
||||
|
||||
mask = SG_ETPINMODE_RMII(0); |
||||
|
||||
switch (priv->phy_mode) { |
||||
case PHY_INTERFACE_MODE_RMII: |
||||
val = SG_ETPINMODE_RMII(0); |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
regmap_read(priv->regmap, SG_ETPINMODE, ®); |
||||
reg &= ~mask; |
||||
reg |= val; |
||||
regmap_write(priv->regmap, SG_ETPINMODE, reg); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ave_pxs3_get_pinmode(struct ave_private *priv) |
||||
{ |
||||
u32 reg, mask, val = 0; |
||||
|
||||
if (priv->regmap_arg > 1) |
||||
return -EINVAL; |
||||
|
||||
mask = SG_ETPINMODE_RMII(priv->regmap_arg); |
||||
|
||||
switch (priv->phy_mode) { |
||||
case PHY_INTERFACE_MODE_RMII: |
||||
val = SG_ETPINMODE_RMII(priv->regmap_arg); |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
regmap_read(priv->regmap, SG_ETPINMODE, ®); |
||||
reg &= ~mask; |
||||
reg |= val; |
||||
regmap_write(priv->regmap, SG_ETPINMODE, reg); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ave_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct eth_pdata *pdata = dev_get_platdata(dev); |
||||
struct ave_private *priv = dev_get_priv(dev); |
||||
struct ofnode_phandle_args args; |
||||
const char *phy_mode; |
||||
const u32 *valp; |
||||
int ret, nc, nr; |
||||
const char *name; |
||||
|
||||
priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); |
||||
if (!priv->data) |
||||
return -EINVAL; |
||||
|
||||
pdata->iobase = devfdt_get_addr(dev); |
||||
pdata->phy_interface = -1; |
||||
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", |
||||
NULL); |
||||
if (phy_mode) |
||||
pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
||||
if (pdata->phy_interface == -1) { |
||||
dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
pdata->max_speed = 0; |
||||
valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", |
||||
NULL); |
||||
if (valp) |
||||
pdata->max_speed = fdt32_to_cpu(*valp); |
||||
|
||||
for (nc = 0; nc < AVE_MAX_CLKS; nc++) { |
||||
name = priv->data->clock_names[nc]; |
||||
if (!name) |
||||
break; |
||||
ret = clk_get_by_name(dev, name, &priv->clk[nc]); |
||||
if (ret) { |
||||
dev_err(dev, "Failed to get clocks property: %d\n", |
||||
ret); |
||||
goto out_clk_free; |
||||
} |
||||
priv->nclks++; |
||||
} |
||||
|
||||
for (nr = 0; nr < AVE_MAX_RSTS; nr++) { |
||||
name = priv->data->reset_names[nr]; |
||||
if (!name) |
||||
break; |
||||
ret = reset_get_by_name(dev, name, &priv->rst[nr]); |
||||
if (ret) { |
||||
dev_err(dev, "Failed to get resets property: %d\n", |
||||
ret); |
||||
goto out_reset_free; |
||||
} |
||||
priv->nrsts++; |
||||
} |
||||
|
||||
ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode", |
||||
NULL, 1, 0, &args); |
||||
if (ret) { |
||||
dev_err(dev, "Failed to get syscon-phy-mode property: %d\n", |
||||
ret); |
||||
goto out_reset_free; |
||||
} |
||||
|
||||
priv->regmap = syscon_node_to_regmap(args.node); |
||||
if (IS_ERR(priv->regmap)) { |
||||
ret = PTR_ERR(priv->regmap); |
||||
dev_err(dev, "can't get syscon: %d\n", ret); |
||||
goto out_reset_free; |
||||
} |
||||
|
||||
if (args.args_count != 1) { |
||||
ret = -EINVAL; |
||||
dev_err(dev, "Invalid argument of syscon-phy-mode\n"); |
||||
goto out_reset_free; |
||||
} |
||||
|
||||
priv->regmap_arg = args.args[0]; |
||||
|
||||
return 0; |
||||
|
||||
out_reset_free: |
||||
while (--nr >= 0) |
||||
reset_free(&priv->rst[nr]); |
||||
out_clk_free: |
||||
while (--nc >= 0) |
||||
clk_free(&priv->clk[nc]); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int ave_probe(struct udevice *dev) |
||||
{ |
||||
struct eth_pdata *pdata = dev_get_platdata(dev); |
||||
struct ave_private *priv = dev_get_priv(dev); |
||||
int ret, nc, nr; |
||||
|
||||
priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); |
||||
if (!priv->data) |
||||
return -EINVAL; |
||||
|
||||
priv->iobase = pdata->iobase; |
||||
priv->phy_mode = pdata->phy_interface; |
||||
priv->max_speed = pdata->max_speed; |
||||
|
||||
ret = priv->data->get_pinmode(priv); |
||||
if (ret) { |
||||
dev_err(dev, "Invalid phy-mode\n"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
for (nc = 0; nc < priv->nclks; nc++) { |
||||
ret = clk_enable(&priv->clk[nc]); |
||||
if (ret) { |
||||
dev_err(dev, "Failed to enable clk: %d\n", ret); |
||||
goto out_clk_release; |
||||
} |
||||
} |
||||
|
||||
for (nr = 0; nr < priv->nrsts; nr++) { |
||||
ret = reset_deassert(&priv->rst[nr]); |
||||
if (ret) { |
||||
dev_err(dev, "Failed to deassert reset: %d\n", ret); |
||||
goto out_reset_release; |
||||
} |
||||
} |
||||
|
||||
ave_reset(priv); |
||||
|
||||
ret = ave_mdiobus_init(priv, dev->name); |
||||
if (ret) { |
||||
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); |
||||
goto out_reset_release; |
||||
} |
||||
|
||||
priv->bus = miiphy_get_dev_by_name(dev->name); |
||||
|
||||
ret = ave_phy_init(priv, dev); |
||||
if (ret) { |
||||
dev_err(dev, "Failed to initialize phy: %d\n", ret); |
||||
goto out_mdiobus_release; |
||||
} |
||||
|
||||
return 0; |
||||
|
||||
out_mdiobus_release: |
||||
mdio_unregister(priv->bus); |
||||
mdio_free(priv->bus); |
||||
out_reset_release: |
||||
reset_release_all(priv->rst, nr); |
||||
out_clk_release: |
||||
clk_release_all(priv->clk, nc); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int ave_remove(struct udevice *dev) |
||||
{ |
||||
struct ave_private *priv = dev_get_priv(dev); |
||||
|
||||
free(priv->phydev); |
||||
mdio_unregister(priv->bus); |
||||
mdio_free(priv->bus); |
||||
reset_release_all(priv->rst, priv->nrsts); |
||||
clk_release_all(priv->clk, priv->nclks); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct eth_ops ave_ops = { |
||||
.start = ave_start, |
||||
.stop = ave_stop, |
||||
.send = ave_send, |
||||
.recv = ave_recv, |
||||
.free_pkt = ave_free_packet, |
||||
.write_hwaddr = ave_write_hwaddr, |
||||
}; |
||||
|
||||
static const struct ave_soc_data ave_pro4_data = { |
||||
.is_desc_64bit = false, |
||||
.clock_names = { |
||||
"gio", "ether", "ether-gb", "ether-phy", |
||||
}, |
||||
.reset_names = { |
||||
"gio", "ether", |
||||
}, |
||||
.get_pinmode = ave_pro4_get_pinmode, |
||||
}; |
||||
|
||||
static const struct ave_soc_data ave_pxs2_data = { |
||||
.is_desc_64bit = false, |
||||
.clock_names = { |
||||
"ether", |
||||
}, |
||||
.reset_names = { |
||||
"ether", |
||||
}, |
||||
.get_pinmode = ave_pro4_get_pinmode, |
||||
}; |
||||
|
||||
static const struct ave_soc_data ave_ld11_data = { |
||||
.is_desc_64bit = false, |
||||
.clock_names = { |
||||
"ether", |
||||
}, |
||||
.reset_names = { |
||||
"ether", |
||||
}, |
||||
.get_pinmode = ave_ld11_get_pinmode, |
||||
}; |
||||
|
||||
static const struct ave_soc_data ave_ld20_data = { |
||||
.is_desc_64bit = true, |
||||
.clock_names = { |
||||
"ether", |
||||
}, |
||||
.reset_names = { |
||||
"ether", |
||||
}, |
||||
.get_pinmode = ave_ld20_get_pinmode, |
||||
}; |
||||
|
||||
static const struct ave_soc_data ave_pxs3_data = { |
||||
.is_desc_64bit = false, |
||||
.clock_names = { |
||||
"ether", |
||||
}, |
||||
.reset_names = { |
||||
"ether", |
||||
}, |
||||
.get_pinmode = ave_pxs3_get_pinmode, |
||||
}; |
||||
|
||||
static const struct udevice_id ave_ids[] = { |
||||
{ |
||||
.compatible = "socionext,uniphier-pro4-ave4", |
||||
.data = (ulong)&ave_pro4_data, |
||||
}, |
||||
{ |
||||
.compatible = "socionext,uniphier-pxs2-ave4", |
||||
.data = (ulong)&ave_pxs2_data, |
||||
}, |
||||
{ |
||||
.compatible = "socionext,uniphier-ld11-ave4", |
||||
.data = (ulong)&ave_ld11_data, |
||||
}, |
||||
{ |
||||
.compatible = "socionext,uniphier-ld20-ave4", |
||||
.data = (ulong)&ave_ld20_data, |
||||
}, |
||||
{ |
||||
.compatible = "socionext,uniphier-pxs3-ave4", |
||||
.data = (ulong)&ave_pxs3_data, |
||||
}, |
||||
{ /* Sentinel */ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(ave) = { |
||||
.name = "ave", |
||||
.id = UCLASS_ETH, |
||||
.of_match = ave_ids, |
||||
.probe = ave_probe, |
||||
.remove = ave_remove, |
||||
.ofdata_to_platdata = ave_ofdata_to_platdata, |
||||
.ops = &ave_ops, |
||||
.priv_auto_alloc_size = sizeof(struct ave_private), |
||||
.platdata_auto_alloc_size = sizeof(struct eth_pdata), |
||||
}; |
||||
Loading…
Reference in new issue