Update omap5912osk board support

- Fix OMAP support that omap5912osk compiles in current source tree
  - Update with code from "http://omap.spectrumdigital.com/osk5912"
    to fix problems with DDR initialization
  - Fix timer setup
  - Use CFI flash driver and support complete 32MB of onboard flash
  - Add "print_cpuinfo()" and "checkboard()" functions to display
    CPU (with frequency) and Board infos
Patch by Stefan Roese, 10 May 2006
master
Stefan Roese 18 years ago
parent 4af099bda9
commit 6080a0eb63
  1. 10
      CHANGELOG
  2. 183
      board/omap5912osk/lowlevel_init.S
  3. 18
      board/omap5912osk/omap5912osk.c
  4. 2
      cpu/arm926ejs/Makefile
  5. 245
      cpu/arm926ejs/cpuinfo.c
  6. 52
      include/asm-arm/arch-omap/sizes.h
  7. 36
      include/configs/omap5912osk.h

@ -2,6 +2,16 @@
Changes since U-Boot 1.1.4:
======================================================================
* Update omap5912osk board support
- Fix OMAP support that omap5912osk compiles in current source tree
- Update with code from "http://omap.spectrumdigital.com/osk5912"
to fix problems with DDR initialization
- Fix timer setup
- Use CFI flash driver and support complete 32MB of onboard flash
- Add "print_cpuinfo()" and "checkboard()" functions to display
CPU (with frequency) and Board infos
Patch by Stefan Roese, 10 May 2006
* Fix watchdog issues for ColdFire boards.
* Add M5271EVB board support.

@ -41,6 +41,13 @@ _TEXT_BASE:
.globl lowlevel_init
lowlevel_init:
/*------------------------------------------------------*
* Ensure i-cache is enabled *
* To configure TC regs without fetching instruction *
*------------------------------------------------------*/
mrc p15, 0, r0, c1, c0
orr r0, r0, #0x1000
mcr p15, 0, r0, c1, c0
/*------------------------------------------------------*
*mask all IRQs by setting all bits in the INTMR default*
@ -59,33 +66,34 @@ lowlevel_init:
str r1, [r0]
/*------------------------------------------------------*
* Set up ARM CLM registers (IDLECT2) *
* Set up ARM CLM registers (IDLECT2) *
*------------------------------------------------------*/
ldr r0, REG_ARM_IDLECT2
ldr r1, VAL_ARM_IDLECT2
str r1, [r0]
/*------------------------------------------------------*
* Set up ARM CLM registers (IDLECT3) *
* Set up ARM CLM registers (IDLECT3) *
*------------------------------------------------------*/
ldr r0, REG_ARM_IDLECT3
ldr r1, VAL_ARM_IDLECT3
str r1, [r0]
mov r1, #0x01 /* PER_EN bit */
mov r1, #0x01 /* PER_EN bit */
ldr r0, REG_ARM_RSTCT2
strh r1, [r0] /* CLKM; Peripheral reset. */
strh r1, [r0] /* CLKM; Peripheral reset. */
/* Set CLKM to Sync-Scalable */
/* I supposedly need to enable the dsp clock before switching */
mov r1, #0x0000
/* Set CLKM to Sync-Scalable */
mov r1, #0x1000
ldr r0, REG_ARM_SYSST
strh r1, [r0]
mov r0, #0x400
1:
subs r0, r0, #0x1 /* wait for any bubbles to finish */
mov r2, #0
1: cmp r2, #1
streqh r1, [r0]
add r2, r2, #1
cmp r2, #0x100 /* wait for any bubbles to finish */
bne 1b
ldr r1, VAL_ARM_CKCTL
ldr r0, REG_ARM_CKCTL
strh r1, [r0]
@ -107,17 +115,16 @@ lowlevel_init:
ldr r1, VAL_DPLL1_CTL
ldr r0, REG_DPLL1_CTL
strh r1, [r0]
ands r1, r1, #0x10 /* Check if PLL is enabled. */
beq lock_end /* Do not look for lock if BYPASS selected */
ands r1, r1, #0x10 /* Check if PLL is enabled. */
beq lock_end /* Do not look for lock if BYPASS selected */
2:
ldrh r1, [r0]
ands r1, r1, #0x01 /* Check the LOCK bit.*/
beq 2b /* loop until bit goes hi. */
ands r1, r1, #0x01 /* Check the LOCK bit.*/
beq 2b /* loop until bit goes hi. */
lock_end:
/*------------------------------------------------------*
* Turn off the watchdog during init... *
* Turn off the watchdog during init... *
*------------------------------------------------------*/
ldr r0, REG_WATCHDOG
ldr r1, WATCHDOG_VAL1
@ -143,30 +150,49 @@ watch2Wait:
tst r1, #0x10
bne watch2Wait
/* Set memory timings corresponding to the new clock speed */
ldr r3, VAL_SDRAM_CONFIG_SDF0
/* Check execution location to determine current execution location
* and branch to appropriate initialization code.
*/
/* Load physical SDRAM base. */
mov r0, #0x10000000
/* Get current execution location. */
mov r1, pc
/* Compare. */
cmp r1, r0
/* Skip over EMIF-fast initialization if running from SDRAM. */
bge skip_sdram
mov r0, #0x10000000 /* Load physical SDRAM base. */
mov r1, pc /* Get current execution location. */
cmp r1, r0 /* Compare. */
bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
/* identify the device revision, -- TMX or TMP(TMS) */
ldr r0, REG_DEVICE_ID
ldr r1, [r0]
ldr r0, VAL_DEVICE_ID_TMP
mov r1, r1, lsl #15
mov r1, r1, lsr #16
cmp r0, r1
bne skip_TMP_Patch
/* Enable TMP/TMS device new features */
mov r0, #1
ldr r1, REG_TC_EMIFF_DOUBLER
str r0, [r1]
/* Enable new ac parameters */
mov r0, #0x0b
ldr r1, REG_SDRAM_CONFIG2
str r0, [r1]
ldr r3, VAL_SDRAM_CONFIG_SDF1
skip_TMP_Patch:
/*
* Delay for SDRAM initialization.
*/
mov r3, #0x1800 /* value should be checked */
mov r0, #0x1800 /* value should be checked */
3:
subs r3, r3, #0x1 /* Decrement count */
subs r0, r0, #0x1 /* Decrement count */
bne 3b
/*
* Set SDRAM control values. Disable refresh before MRS command.
*/
@ -178,14 +204,15 @@ watch2Wait:
/* config register */
ldr r0, REG_SDRAM_CONFIG
ldr r1, SDRAM_CONFIG_VAL
str r1, [r0]
str r3, [r0]
/* manual command register */
ldr r0, REG_SDRAM_MANUAL_CMD
/* issue set cke high */
mov r1, #CMD_SDRAM_CKE_SET_HIGH
str r1, [r0]
/* issue nop */
mov r1, #CMD_SDRAM_NOP
str r1, [r0]
@ -228,25 +255,23 @@ waitMDDR1:
str r1, [r0]
/* delay loop */
mov r2, #0x0100
mov r0, #0x0100
waitMDDR2:
subs r2, r2, #1
subs r0, r0, #1
bne waitMDDR2
/*
* Delay for SDRAM initialization.
*/
mov r3, #0x1800
mov r0, #0x1800
4:
subs r3, r3, #1 /* Decrement count. */
subs r0, r0, #1 /* Decrement count. */
bne 4b
b common_tc
skip_sdram:
ldr r0, REG_SDRAM_CONFIG
ldr r1, SDRAM_CONFIG_VAL
str r1, [r0]
str r3, [r0]
common_tc:
/* slow interface */
@ -257,10 +282,15 @@ common_tc:
ldr r1, VAL_TC_EMIFS_CS1_CONFIG
ldr r0, REG_TC_EMIFS_CS1_CONFIG
str r1, [r0] /* Chip Select 1 */
ldr r1, VAL_TC_EMIFS_CS3_CONFIG
ldr r0, REG_TC_EMIFS_CS3_CONFIG
str r1, [r0] /* Chip Select 3 */
ldr r1, VAL_TC_EMIFS_DWS
ldr r0, REG_TC_EMIFS_DWS
str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */
#ifdef CONFIG_H2_OMAP1610
/* inserting additional 2 clock cycle hold time for LAN */
ldr r0, REG_TC_EMIFS_CS1_ADVANCED
@ -282,8 +312,9 @@ common_tc:
/* the literal pools origin */
.ltorg
REG_TC_EMIFS_CONFIG: /* 32 bits */
REG_DEVICE_ID: /* 32 bits */
.word 0xfffe2004
REG_TC_EMIFS_CONFIG:
.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
.word 0xfffecc10
@ -293,7 +324,8 @@ REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
.word 0xfffecc1c
REG_TC_EMIFS_DWS: /* 32 bits */
.word 0xfffecc40
#ifdef CONFIG_H2_OMAP1610
REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
.word 0xfffecc54
@ -302,18 +334,17 @@ REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL: /* 16 bits */
.word 0xfffece00
REG_ARM_IDLECT3: /* 16 bits */
.word 0xfffece24
REG_ARM_IDLECT2: /* 16 bits */
.word 0xfffece08
REG_ARM_IDLECT1: /* 16 bits */
.word 0xfffece04
REG_ARM_RSTCT2: /* 16 bits */
.word 0xfffece14
REG_ARM_SYSST: /* 16 bits */
.word 0xfffece18
/* DPLL control registers */
REG_DPLL1_CTL: /* 16 bits */
.word 0xfffecf00
@ -335,6 +366,10 @@ WSPRDOG_VAL2:
counter @8192 rows, 10 ns, 8 burst */
REG_SDRAM_CONFIG:
.word 0xfffecc20
REG_SDRAM_CONFIG2:
.word 0xfffecc3c
REG_TC_EMIFF_DOUBLER: /* 32 bits */
.word 0xfffecc60
/* Operation register */
REG_SDRAM_OPERATION:
@ -356,35 +391,47 @@ REG_SDRAM_EMRS1:
REG_DLL_WRT_CONTROL:
.word 0xfffecc68
DLL_WRT_CONTROL_VAL:
.word 0x03f00002
.word 0x03f00002 /* Phase of 72deg, write offset +31 */
/* URD DLL register */
REG_DLL_URD_CONTROL:
.word 0xfffeccc0
DLL_URD_CONTROL_VAL:
.word 0x00800002
.word 0x00800002 /* Phase of 72deg, read offset +31 */
/* LRD DLL register */
REG_DLL_LRD_CONTROL:
.word 0xfffecccc
DLL_LRD_CONTROL_VAL:
.word 0x00800002 /* read offset +31 */
REG_WATCHDOG:
.word 0xfffec808
WATCHDOG_VAL1:
.word 0x000000f5
WATCHDOG_VAL2:
.word 0x000000a0
REG_MPU_LOAD_TIMER:
.word 0xfffec600
.word 0xfffec504
REG_MPU_CNTL_TIMER:
.word 0xfffec500
VAL_MPU_LOAD_TIMER:
.word 0xffffffff
VAL_MPU_CNTL_TIMER:
.word 0xffffffa1
/* 96 MHz Samsung Mobile DDR */
SDRAM_CONFIG_VAL:
.word 0x001200f4
/* Original setting for TMX device */
VAL_SDRAM_CONFIG_SDF0:
.word 0x0014e6fe
DLL_LRD_CONTROL_VAL:
.word 0x00800002
/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
VAL_SDRAM_CONFIG_SDF1:
.word 0x0114e6fe
VAL_ARM_CKCTL:
.word 0x3000
.word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */
VAL_DPLL1_CTL:
.word 0x2830
@ -396,7 +443,11 @@ VAL_TC_EMIFS_CS1_CONFIG:
VAL_TC_EMIFS_CS2_CONFIG:
.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
.word 0x88011131
.word 0x88013141
VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */
.word 0x000000c0
VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */
.word 0xb65f
#endif
#ifdef CONFIG_H2_OMAP1610
@ -407,36 +458,20 @@ VAL_TC_EMIFS_CS1_CONFIG:
VAL_TC_EMIFS_CS2_CONFIG:
.word 0xf800f22a
VAL_TC_EMIFS_CS3_CONFIG:
.word 0x88011131
.word 0x88013141
VAL_TC_EMIFS_CS1_ADVANCED:
.word 0x00000022
#endif
VAL_TC_EMIFF_SDRAM_CONFIG:
.word 0x010290fc
VAL_TC_EMIFF_MRS:
.word 0x00000027
VAL_ARM_IDLECT1:
.word 0x00000400
VAL_ARM_IDLECT2:
.word 0x00000886
VAL_ARM_IDLECT3:
.word 0x00000015
WATCHDOG_VAL1:
.word 0x000000f5
WATCHDOG_VAL2:
.word 0x000000a0
VAL_MPU_LOAD_TIMER:
.word 0xffffffff
VAL_MPU_CNTL_TIMER:
.word 0xffffffa1
/* command values */
.equ CMD_SDRAM_NOP, 0x00000000
.equ CMD_SDRAM_PRECHARGE, 0x00000001
.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
.equ CMD_SDRAM_NOP, 0x00000000
.equ CMD_SDRAM_PRECHARGE, 0x00000001
.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007

@ -288,3 +288,21 @@ void peripheral_power_enable (void)
*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
}
/*
* Check Board Identity
*/
int checkboard(void)
{
char *s = getenv("serial#");
puts("Board: OSK5912");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return (0);
}

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
OBJS = interrupts.o cpu.o
OBJS = interrupts.o cpu.o cpuinfo.o
all: .depend $(START) $(LIB)

@ -0,0 +1,245 @@
/*
* OMAP1 CPU identification code
*
* Copyright (C) 2004 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <command.h>
#include <arm926ejs.h>
#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
#define omap_readw(x) *(volatile unsigned short *)(x)
#define omap_readl(x) *(volatile unsigned long *)(x)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define OMAP_DIE_ID_0 0xfffe1800
#define OMAP_DIE_ID_1 0xfffe1804
#define OMAP_PRODUCTION_ID_0 0xfffe2000
#define OMAP_PRODUCTION_ID_1 0xfffe2004
#define OMAP32_ID_0 0xfffed400
#define OMAP32_ID_1 0xfffed404
struct omap_id {
u16 jtag_id; /* Used to determine OMAP type */
u8 die_rev; /* Processor revision */
u32 omap_id; /* OMAP revision */
u32 type; /* Cpu id bits [31:08], cpu class bits [07:00] */
};
/* Register values to detect the OMAP version */
static struct omap_id omap_ids[] = {
{ .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
{ .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
{ .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
{ .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000},
{ .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000},
{ .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00},
{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00},
{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
{ .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000},
{ .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00},
{ .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00},
{ .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300},
{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300},
{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300},
{ .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000},
{ .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000},
{ .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000},
};
/*
* Get OMAP type from PROD_ID.
* 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
* 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
* Undocumented register in TEST BLOCK is used as fallback; This seems to
* work on 1510, 1610 & 1710. The official way hopefully will work in future
* processors.
*/
static u16 omap_get_jtag_id(void)
{
u32 prod_id, omap_id;
prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
omap_id = omap_readl(OMAP32_ID_1);
/* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
if (((prod_id >> 20) == 0) || (prod_id == omap_id))
prod_id = 0;
else
prod_id &= 0xffff;
if (prod_id)
return prod_id;
/* Use OMAP32_ID_1 as fallback */
prod_id = ((omap_id >> 12) & 0xffff);
return prod_id;
}
/*
* Get OMAP revision from DIE_REV.
* Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
* Undocumented register in the TEST BLOCK is used as fallback.
* REVISIT: This does not seem to work on 1510
*/
static u8 omap_get_die_rev(void)
{
u32 die_rev;
die_rev = omap_readl(OMAP_DIE_ID_1);
/* Check for broken OMAP_DIE_ID on early 1710 */
if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
die_rev = 0;
die_rev = (die_rev >> 17) & 0xf;
if (die_rev)
return die_rev;
die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
return die_rev;
}
static unsigned long dpll1(void)
{
unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG);
unsigned long rate;
rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */
if (pll_ctl_val & 0x10) {
/* PLL enabled, apply multiplier and divisor */
if (pll_ctl_val & 0xf80)
rate *= (pll_ctl_val & 0xf80) >> 7;
rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
} else {
/* PLL disabled, apply bypass divisor */
switch (pll_ctl_val & 0xc) {
case 0:
break;
case 0x4:
rate /= 2;
break;
default:
rate /= 4;
break;
}
}
return rate;
}
static unsigned long armcore(void)
{
unsigned short arm_ckctl = omap_readw(ARM_CKCTL);
return (dpll1() >> ((arm_ckctl & 0x0030) >> 4));
}
int print_cpuinfo (void)
{
int i;
u16 jtag_id;
u8 die_rev;
u32 omap_id;
u8 cpu_type;
u32 system_serial_high;
u32 system_serial_low;
u32 system_rev = 0;
jtag_id = omap_get_jtag_id();
die_rev = omap_get_die_rev();
omap_id = omap_readl(OMAP32_ID_0);
#ifdef DEBUG
printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
omap_readl(OMAP_DIE_ID_1),
(omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0));
printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
omap_readl(OMAP_PRODUCTION_ID_1),
omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
#endif
system_serial_high = omap_readl(OMAP_DIE_ID_0);
system_serial_low = omap_readl(OMAP_DIE_ID_1);
/* First check only the major version in a safe way */
for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
if (jtag_id == (omap_ids[i].jtag_id)) {
system_rev = omap_ids[i].type;
break;
}
}
/* Check if we can find the die revision */
for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) {
system_rev = omap_ids[i].type;
break;
}
}
/* Finally check also the omap_id */
for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
if (jtag_id == omap_ids[i].jtag_id
&& die_rev == omap_ids[i].die_rev
&& omap_id == omap_ids[i].omap_id) {
system_rev = omap_ids[i].type;
break;
}
}
/* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
cpu_type = system_rev >> 24;
switch (cpu_type) {
case 0x07:
system_rev |= 0x07;
break;
case 0x03:
case 0x15:
system_rev |= 0x15;
break;
case 0x16:
case 0x17:
system_rev |= 0x16;
break;
case 0x24:
system_rev |= 0x24;
break;
default:
printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
}
printf("CPU: OMAP%04x", system_rev >> 16);
if ((system_rev >> 8) & 0xff)
printf("%x", (system_rev >> 8) & 0xff);
#ifdef DEBUG
printf(" revision %i handled as %02xxx id: %08x%08x",
die_rev, system_rev & 0xff, system_serial_low, system_serial_high);
#endif
printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n",
armcore() / 1000000, (armcore() / 100000) % 10,
dpll1() / 1000000, (dpll1() / 100000) % 10);
return 0;
}
#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */

@ -0,0 +1,52 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* DO NOT EDIT!! - this file automatically generated
* from .s file by awk -f s2h.awk
*/
/* Size defintions
* Copyright (C) ARM Limited 1998. All rights reserved.
*/
#ifndef __sizes_h
#define __sizes_h 1
/* handy sizes */
#define SZ_1K 0x00000400
#define SZ_4K 0x00001000
#define SZ_8K 0x00002000
#define SZ_16K 0x00004000
#define SZ_64K 0x00010000
#define SZ_128K 0x00020000
#define SZ_256K 0x00040000
#define SZ_512K 0x00080000
#define SZ_1M 0x00100000
#define SZ_2M 0x00200000
#define SZ_4M 0x00400000
#define SZ_8M 0x00800000
#define SZ_16M 0x01000000
#define SZ_32M 0x02000000
#define SZ_64M 0x04000000
#define SZ_128M 0x08000000
#define SZ_256M 0x10000000
#define SZ_512M 0x20000000
#define SZ_1G 0x40000000
#define SZ_2G 0x80000000
#endif
/* END */

@ -35,6 +35,9 @@
#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */
#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
/* input clock of PLL */
/* the OMAP5912 OSK has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
@ -45,11 +48,13 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
@ -142,27 +147,44 @@
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
/*-----------------------------------------------------------------------
* FLASH and environment organization
* FLASH driver setup
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
/* addr of environment */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_ENV_IS_IN_FLASH 1
/* addr of environment */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
#define CFG_ENV_OFFSET 0x20000 /* environment starts here */

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