As we use device tree to control u-boot now, the generic board can be removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>master
Thomas Chou
9 years ago
parent
7cacb64a35
commit
6168dc6a7a
@ -1,33 +0,0 @@ |
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/*
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* Altera CF drvier |
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* |
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* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#if defined(CONFIG_IDE_RESET) && defined(CONFIG_SYS_CF_CTL_BASE) |
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/* ide_set_reset for Altera CF interface */ |
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#define ALTERA_CF_CTL_STATUS 0 |
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#define ALTERA_CF_IDE_CTL 4 |
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#define ALTERA_CF_CTL_STATUS_PRESENT_MSK (0x1) |
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#define ALTERA_CF_CTL_STATUS_POWER_MSK (0x2) |
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#define ALTERA_CF_CTL_STATUS_RESET_MSK (0x4) |
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#define ALTERA_CF_CTL_STATUS_IRQ_EN_MSK (0x8) |
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#define ALTERA_CF_IDE_CTL_IRQ_EN_MSK (0x1) |
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void ide_set_reset(int idereset) |
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{ |
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int i; |
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writel(idereset ? ALTERA_CF_CTL_STATUS_RESET_MSK : |
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ALTERA_CF_CTL_STATUS_POWER_MSK, |
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CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS); |
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/* wait 500 ms for power to stabilize */ |
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for (i = 0; i < 500; i++) |
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udelay(1000); |
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} |
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#endif |
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@ -1,12 +0,0 @@ |
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if TARGET_NIOS2_GENERIC |
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config SYS_BOARD |
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default "nios2-generic" |
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config SYS_VENDOR |
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default "altera" |
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config SYS_CONFIG_NAME |
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default "nios2-generic" |
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endif |
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@ -1,6 +0,0 @@ |
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NIOS2-GENERIC BOARD |
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M: Scott McNutt <smcnutt@psyent.com> |
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S: Maintained |
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F: board/altera/nios2-generic/ |
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F: include/configs/nios2-generic.h |
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F: configs/nios2-generic_defconfig |
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@ -1,10 +0,0 @@ |
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := nios2-generic.o
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obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
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@ -1,12 +0,0 @@ |
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#
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# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
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# Scott McNutt <smcnutt@psyent.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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@ -1,89 +0,0 @@ |
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/*
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* This header is generated by sopc2dts |
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* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl> |
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* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _CUSTOM_FPGA_H_ |
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#define _CUSTOM_FPGA_H_ |
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/* generated from qsys_ghrd_3c120.sopcinfo */ |
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/* Dumping slaves of cpu.data_master */ |
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/* cpu.jtag_debug_module is a altera_nios2_qsys */ |
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#define CONFIG_SYS_CLK_FREQ 125000000 |
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#define CONFIG_SYS_DCACHE_SIZE 32768 |
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#define CONFIG_SYS_DCACHELINE_SIZE 32 |
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#define CONFIG_SYS_ICACHELINE_SIZE 32 |
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#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020 |
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#define CONFIG_SYS_ICACHE_SIZE 32768 |
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#define CONFIG_SYS_RESET_ADDR 0xc2800000 |
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#define IO_REGION_BASE 0xE0000000 |
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/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */ |
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/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */ |
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/* ddr2_bot.s1 is a altmemddr2 */ |
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#define CONFIG_SYS_SDRAM_BASE 0xD0000000 |
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000 |
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/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */ |
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/* Dumping slaves of pb_cpu_to_io.m0 */ |
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/* timer_1ms.s1 is a altera_avalon_timer */ |
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#define CONFIG_SYS_TIMER_IRQ 11 |
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#define CONFIG_SYS_TIMER_FREQ 125000000 |
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#define CONFIG_SYS_TIMER_BASE 0xE8400000 |
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/* sysid.control_slave is a altera_avalon_sysid_qsys */ |
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#define CONFIG_SYS_SYSID_BASE 0xE8004D40 |
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/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */ |
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#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50 |
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/* tse_mac.control_port is a triple_speed_ethernet */ |
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#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048 |
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#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800 |
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#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400 |
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#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048 |
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#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000 |
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#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000 |
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#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000 |
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#define CONFIG_ALTERA_TSE |
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#define CONFIG_MII |
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#define CONFIG_CMD_MII |
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#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18 |
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#define CONFIG_SYS_ALTERA_TSE_FLAGS 1 |
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/* uart.s1 is a altera_avalon_uart */ |
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#define CONFIG_SYS_UART_BAUD 115200 |
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#define CONFIG_SYS_UART_BASE 0xE8004C80 |
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#define CONFIG_SYS_UART_FREQ 62500000 |
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/* user_led_pio_8out.s1 is a altera_avalon_pio */ |
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#define USER_LED_PIO_8OUT_BASE 0xE8004CC0 |
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/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */ |
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#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0 |
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#define USER_DIPSW_PIO_8IN_IRQ 8 |
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/* user_pb_pio_4in.s1 is a altera_avalon_pio */ |
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#define USER_PB_PIO_4IN_BASE 0xE8004D00 |
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#define USER_PB_PIO_4IN_IRQ 9 |
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/* cfi_flash_64m.uas is a altera_generic_tristate_controller */ |
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#define CFI_FLASH_64M_BASE 0xE0000000 |
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/* ext_flash.s1 is a altera_avalon_cfi_flash */ |
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#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
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#define CONFIG_SYS_FLASH_PROTECTION |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_SYS_MAX_FLASH_SECT 512 |
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#endif /* _CUSTOM_FPGA_H_ */ |
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@ -1,76 +0,0 @@ |
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/*
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* (C) Copyright 2005, Psyent Corporation <www.psyent.com> |
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* Scott McNutt <smcnutt@psyent.com> |
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* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#if defined(CONFIG_CFI_FLASH_MTD) |
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#include <mtd/cfi_flash.h> |
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#endif |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ |
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defined(CONFIG_CFI_FLASH_MTD) |
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static void __early_flash_cmd_reset(void) |
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{ |
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/* reset flash before we read env */ |
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writeb(AMD_CMD_RESET, CONFIG_ENV_ADDR); |
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writeb(FLASH_CMD_RESET, CONFIG_ENV_ADDR); |
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} |
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void early_flash_cmd_reset(void) |
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__attribute__((weak,alias("__early_flash_cmd_reset"))); |
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#endif |
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int board_early_init_f(void) |
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{ |
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#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ |
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defined(CONFIG_CFI_FLASH_MTD) |
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early_flash_cmd_reset(); |
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#endif |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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#ifdef CONFIG_ALTERA_SYSID |
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display_sysid(); |
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#endif |
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printf("BOARD: %s\n", CONFIG_BOARD_NAME); |
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return 0; |
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} |
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#ifdef CONFIG_CMD_NET |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_SMC91111 |
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rc += smc91111_initialize(0, CONFIG_SMC91111_BASE); |
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#endif |
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#ifdef CONFIG_DRIVER_DM9000 |
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rc += dm9000_initialize(bis); |
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#endif |
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#ifdef CONFIG_ALTERA_TSE |
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rc += altera_tse_initialize(0, |
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CONFIG_SYS_ALTERA_TSE_MAC_BASE, |
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CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE, |
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CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE, |
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#if defined(CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_BASE) && \ |
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(CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_SIZE > 0) |
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CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_BASE, |
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CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_SIZE); |
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#else |
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0, |
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0); |
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#endif |
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#endif |
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#ifdef CONFIG_ETHOC |
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rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE); |
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#endif |
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return rc; |
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} |
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#endif |
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