- serial console on UART1 - Ethernet RMII over UCC4 - PHY SMSC LAN8700 - 64MB Flash - 128 MB DDR2 RAM - I2C - bootcount This board is similiar to the kmeter1 (8360) board, so common config options are extracted into the include/configs/km83xx-common.h file. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com>master
Heiko Schocher
15 years ago
committed by
Wolfgang Denk
parent
de3ad13de5
commit
62ddcf05e7
@ -0,0 +1,324 @@ |
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/*
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* (C) Copyright 2010 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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*/ |
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#ifndef __CONFIG_KM83XX_H |
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#define __CONFIG_KM83XX_H |
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/* include common defines/options for all Keymile boards */ |
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#include "keymile-common.h" |
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#include "km-powerpc.h" |
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#define MTDIDS_DEFAULT "nor0=boot" |
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#define MTDPARTS_DEFAULT "mtdparts=" \ |
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"boot:" \
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"768k(u-boot)," \
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"128k(env)," \
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"128k(envred)," \
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"-(" CONFIG_KM_UBI_PARTITION_NAME ")" |
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#define CONFIG_MISC_INIT_R |
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/*
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* System Clock Setup |
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*/ |
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#define CONFIG_83XX_CLKIN 66000000 |
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#define CONFIG_SYS_CLK_FREQ 66000000 |
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#define CONFIG_83XX_PCICLK 66000000 |
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/*
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* IMMR new address |
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*/ |
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#define CONFIG_SYS_IMMR 0xE0000000 |
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/*
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* Bus Arbitration Configuration Register (ACR) |
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*/ |
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ |
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ |
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ |
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ |
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/*
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* DDR Setup |
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*/ |
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
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#define CFG_83XX_DDR_USES_CS0 |
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/*
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* Manually set up DDR parameters |
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*/ |
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#define CONFIG_DDR_II |
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#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ |
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/*
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* The reserved memory |
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*/ |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
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#define CONFIG_SYS_FLASH_BASE 0xF0000000 |
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
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#define CONFIG_SYS_RAMBOOT |
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#endif |
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/* Reserve 768 kB for Mon */ |
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
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/*
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* Initial RAM Base Address Setup |
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*/ |
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#define CONFIG_SYS_INIT_RAM_LOCK |
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ |
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#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
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GENERATED_GBL_DATA_SIZE) |
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/*
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* Init Local Bus Memory Controller: |
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* |
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* Bank Bus Machine PortSz Size Device |
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* ---- --- ------- ------ ----- ------ |
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* 0 Local GPCM 16 bit 256MB FLASH |
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* 1 Local GPCM 8 bit 128MB GPIO/PIGGY |
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* |
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*/ |
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/*
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* FLASH on the Local Bus |
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*/ |
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
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#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ |
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#define CONFIG_SYS_FLASH_PROTECTION |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ |
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ |
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) |
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ |
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_5 | \
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OR_GPCM_TRLX | OR_GPCM_EAD) |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ |
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
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/*
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* PRIO1/PIGGY on the local bus CS1 |
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*/ |
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE |
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#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ |
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ |
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(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
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BR_V) |
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#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \ |
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_2 | \
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OR_GPCM_TRLX | OR_GPCM_EAD) |
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/*
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* Serial Port |
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*/ |
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#define CONFIG_CONS_INDEX 1 |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_REG_SIZE 1 |
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) |
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/* Pass open firmware flat tree */ |
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#define CONFIG_OF_LIBFDT |
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#define CONFIG_OF_BOARD_SETUP |
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#define CONFIG_OF_STDOUT_VIA_ALIAS |
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#ifndef CONFIG_NET_MULTI |
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#define CONFIG_NET_MULTI |
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#endif |
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/*
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* QE UEC ethernet configuration |
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*/ |
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#define CONFIG_UEC_ETH |
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#define CONFIG_ETHPRIME "UEC0" |
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#define CONFIG_UEC_ETH1 /* GETH1 */ |
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#define UEC_VERBOSE_DEBUG 1 |
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#ifdef CONFIG_UEC_ETH1 |
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#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ |
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ |
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 |
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#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH |
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#define CONFIG_SYS_UEC1_PHY_ADDR 0 |
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
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#endif |
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/*
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* Environment |
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*/ |
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#ifndef CONFIG_SYS_RAMBOOT |
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#define CONFIG_ENV_IS_IN_FLASH |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
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CONFIG_SYS_MONITOR_LEN) |
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
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#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) |
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/* Address and size of Redundant Environment Sector */ |
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ |
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CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
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#else /* CFG_SYS_RAMBOOT */ |
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#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ |
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#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
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#define CONFIG_ENV_SIZE 0x2000 |
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#endif /* CFG_SYS_RAMBOOT */ |
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/* I2C */ |
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#define CONFIG_HARD_I2C /* I2C with hardware support */ |
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#define CONFIG_FSL_I2C |
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#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ |
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#define CONFIG_SYS_I2C_SLAVE 0x7F |
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#define CONFIG_SYS_I2C_OFFSET 0x3000 |
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
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#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ |
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#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ |
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#define CONFIG_SYS_DTT_MAX_TEMP 70 |
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#define CONFIG_SYS_DTT_LOW_TEMP -30 |
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#define CONFIG_SYS_DTT_HYSTERESIS 3 |
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#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) |
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#if defined(CONFIG_CMD_NAND) |
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#define CONFIG_NAND_KMETER1 |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE |
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#endif |
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#if defined(CONFIG_PCI) |
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#define CONFIG_CMD_PCI |
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#endif |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
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/*
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* Core HID Setup |
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*/ |
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#define CONFIG_SYS_HID0_INIT 0x000000000 |
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
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HID0_ENABLE_INSTRUCTION_CACHE) |
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#define CONFIG_SYS_HID2 HID2_HBE |
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/*
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* MMU Setup |
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*/ |
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
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/* DDR: cache cacheable */ |
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ |
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ |
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BATU_VS | BATU_VP) |
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
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/* IMMRBAR & PCI IO: cache-inhibit and guarded */ |
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ |
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ |
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| BATU_VP) |
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
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/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ |
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ |
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BATL_MEMCOHERENCE) |
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \ |
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BATU_VS | BATU_VP) |
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ |
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ |
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BATL_MEMCOHERENCE) |
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ |
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BATU_VS | BATU_VP) |
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#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ |
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
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/* Stack in dcache: cacheable, no memory coherence */ |
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) |
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ |
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BATU_VS | BATU_VP) |
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
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/*
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* Internal Definitions |
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* |
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* Boot Flags |
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*/ |
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
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#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
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#define BOOTFLASH_START 0xF0000000 |
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#define CONFIG_KM_CONSOLE_TTY "ttyS0" |
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/*
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* Environment Configuration |
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*/ |
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#define CONFIG_ENV_OVERWRITE |
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#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ |
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#define CONFIG_KM_DEF_ENV "km-common=empty\0" |
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#endif |
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#ifndef CONFIG_KM_DEF_ROOTPATH |
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#define CONFIG_KM_DEF_ROOTPATH \ |
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"rootpath=/opt/eldk/ppc_82xx\0" |
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#endif |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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CONFIG_KM_DEF_ENV \
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CONFIG_KM_DEF_ROOTPATH \
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"dtt_bus=pca9547:70:a\0" \
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"EEprom_ivm=pca9547:70:9\0" \
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"newenv=" \
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"prot off 0xF00C0000 +0x40000 && " \
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"era 0xF00C0000 +0x40000\0" \
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"unlock=yes\0" \
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"" |
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#if defined(CONFIG_UEC_ETH) |
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#define CONFIG_HAS_ETH0 |
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#endif |
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#endif /* __CONFIG_KM83XX_H */ |
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@ -0,0 +1,214 @@ |
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. |
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* Dave Liu <daveliu@freescale.com> |
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* |
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* Copyright (C) 2007 Logic Product Development, Inc. |
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* Peter Barada <peterb@logicpd.com> |
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* |
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* Copyright (C) 2007 MontaVista Software, Inc. |
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* Anton Vorontsov <avorontsov@ru.mvista.com> |
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* |
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* (C) Copyright 2010 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_QE /* Has QE */ |
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#define CONFIG_MPC832x /* MPC832x CPU specific */ |
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#define CONFIG_SUVD3 /* SUVD3 board specific */ |
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#define CONFIG_HOSTNAME suvd3 |
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#define CONFIG_KM_BOARD_NAME "suvd3" |
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#define CONFIG_SYS_TEXT_BASE 0xF0000000 |
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#define CONFIG_KM_DEF_NETDEV \ |
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"netdev=eth0\0" |
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#define CONFIG_KM_DEF_ROOTPATH \ |
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"rootpath=/opt/eldk/ppc_8xx\0" |
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/* include common defines/options for all 83xx Keymile boards */ |
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#include "km83xx-common.h" |
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#define CONFIG_MISC_INIT_R 1 |
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/*
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* System IO Config |
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*/ |
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#define CONFIG_SYS_SICRL SICRL_IRQ_CKS |
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/*
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* Hardware Reset Configuration Word |
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*/ |
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#define CONFIG_SYS_HRCW_LOW (\ |
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
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HRCWL_DDR_TO_SCB_CLK_2X1 | \
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HRCWL_CSB_TO_CLKIN_2X1 | \
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HRCWL_CORE_TO_CSB_2_5X1 | \
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HRCWL_CE_PLL_VCO_DIV_2 | \
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HRCWL_CE_TO_PLL_1X3) |
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#define CONFIG_SYS_HRCW_HIGH (\ |
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HRCWH_PCI_AGENT | \
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HRCWH_PCI_ARBITER_DISABLE | \
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HRCWH_CORE_ENABLE | \
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HRCWH_FROM_0X00000100 | \
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HRCWH_BOOTSEQ_DISABLE | \
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HRCWH_SW_WATCHDOG_DISABLE | \
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HRCWH_ROM_LOC_LOCAL_16BIT | \
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HRCWH_BIG_ENDIAN | \
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HRCWH_LALE_NORMAL) |
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f |
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ |
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SDRAM_CFG_32_BE | \
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SDRAM_CFG_SREN) |
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
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#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
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#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ |
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(0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) |
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ |
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CSCONFIG_ODT_WR_CFG | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10) |
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#define CONFIG_SYS_DDR_MODE 0x47860252 |
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#define CONFIG_SYS_DDR_MODE2 0x8080c000 |
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#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ |
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT)) |
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ |
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(2 << TIMING_CFG1_WRREC_SHIFT) | \
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(6 << TIMING_CFG1_REFREC_SHIFT) | \
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(2 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(2 << TIMING_CFG1_PRETOACT_SHIFT)) |
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#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ |
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT)) |
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|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
||||
|
||||
#define CONFIG_SYS_PIGGY_BASE 0xE8000000 |
||||
#define CONFIG_SYS_PIGGY_SIZE 128 |
||||
#define CONFIG_SYS_APP1_BASE 0xA0000000 |
||||
#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ |
||||
#define CONFIG_SYS_APP2_BASE 0xB0000000 |
||||
#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ |
||||
|
||||
/* EEprom support */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) |
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000 |
||||
|
||||
/*
|
||||
* Init Local Bus Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Size Device |
||||
* ---- --- ------- ------ ----- ------ |
||||
* 2 Local UPMA 16 bit 256MB APP1 |
||||
* 3 Local GPCM 16 bit 256MB APP2 |
||||
* |
||||
*/ |
||||
|
||||
/*
|
||||
* APP1 on the local bus CS2 |
||||
*/ |
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE |
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) |
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ |
||||
BR_PS_16 | \
|
||||
BR_MS_UPMA | \
|
||||
BR_V) |
||||
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) |
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ |
||||
BR_PS_16 | \
|
||||
BR_V) |
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ |
||||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_ACS_DIV4 | \
|
||||
OR_GPCM_SCY_3 | \
|
||||
OR_GPCM_TRLX) |
||||
|
||||
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ |
||||
0x0000c000 | \
|
||||
MxMR_WLFx_2X) |
||||
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE |
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
|
||||
/* APP1: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ |
||||
BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
||||
|
||||
#ifdef CONFIG_PCI |
||||
/* PCI MEM space: cacheable */ |
||||
#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
/* PCI MMIO space: cache-inhibit and guarded */ |
||||
#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
#else /* CONFIG_PCI */ |
||||
|
||||
/* APP2: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ |
||||
BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
||||
|
||||
#define CONFIG_SYS_IBAT7L (0) |
||||
#define CONFIG_SYS_IBAT7U (0) |
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue