- add u-boot.hex target in the top level Makefile - add support for the UNSW/NICTA PLEB 2 board (pleb2) - use -mtune=xscale and -march=armv5 options for PXAmaster
parent
a562e1bd9d
commit
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@ -0,0 +1,48 @@ |
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := pleb2.o flash.o
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SOBJS := memsetup.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,3 @@ |
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TEXT_BASE = 0xa1F80000
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#TEXT_BASE = 0xa3080000
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#TEXT_BASE = 0
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@ -0,0 +1,814 @@ |
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/*
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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/* environment.h defines the various CFG_ENV_... values in terms
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* of whichever ones are given in the configuration file. |
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*/ |
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#include <environment.h> |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
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* has nothing to do with the flash chip being 8-bit or 16-bit. |
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*/ |
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#ifdef CONFIG_FLASH_16BIT |
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typedef unsigned short FLASH_PORT_WIDTH; |
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typedef volatile unsigned short FLASH_PORT_WIDTHV; |
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#define FLASH_ID_MASK 0xFFFF |
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#else |
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typedef unsigned long FLASH_PORT_WIDTH; |
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typedef volatile unsigned long FLASH_PORT_WIDTHV; |
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#define FLASH_ID_MASK 0xFFFFFFFF |
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#endif |
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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#define ORMASK(size) ((-size) & OR_AM_MSK) |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (FPWV * addr, flash_info_t * info); |
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static void flash_reset (flash_info_t * info); |
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static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data); |
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static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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#ifdef CFG_FLASH_PROTECTION |
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static void flash_sync_real_protect (flash_info_t * info); |
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#endif |
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/*-----------------------------------------------------------------------
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* flash_init() |
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* |
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* sets up flash_info and returns size of FLASH (bytes) |
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size_b; |
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int i; |
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/* Init: no FLASHes known */ |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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size_b = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); |
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flash_info[0].size = size_b; |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n", |
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size_b); |
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} |
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/* Do this again (was done already in flast_get_size), just
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* in case we move it when remap the FLASH. |
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*/ |
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flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); |
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#ifdef CFG_FLASH_PROTECTION |
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/* read the hardware protection status (if any) into the
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* protection array in flash_info. |
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*/ |
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flash_sync_real_protect (&flash_info[0]); |
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#endif |
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect (FLAG_PROTECT_SET, |
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CFG_MONITOR_BASE, |
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CFG_MONITOR_BASE + monitor_flash_len - 1, |
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&flash_info[0]); |
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#endif |
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#ifdef CFG_ENV_ADDR |
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flash_protect (FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); |
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#endif |
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#ifdef CFG_ENV_ADDR_REDUND |
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flash_protect (FLAG_PROTECT_SET, |
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CFG_ENV_ADDR_REDUND, |
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CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, |
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&flash_info[0]); |
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#endif |
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return (size_b); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_reset (flash_info_t * info) |
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{ |
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FPWV *base = (FPWV *) (info->start[0]); |
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/* Put FLASH back in read mode */ |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) |
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*base = (FPW) 0x00FF00FF; /* Intel Read Mode */ |
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else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) |
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*base = (FPW) 0x00F000F0; /* AMD Read Mode */ |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t * info) |
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{ |
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int i; |
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/* set up sector start address table */ |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL |
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&& (info->flash_id & FLASH_BTYPE)) { |
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int bootsect_size; /* number of bytes/boot sector */ |
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int sect_size; /* number of bytes/regular sector */ |
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bootsect_size = 0x00002000 * (sizeof (FPW) / 2); |
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sect_size = 0x00010000 * (sizeof (FPW) / 2); |
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/* set sector offsets for bottom boot block type */ |
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for (i = 0; i < 8; ++i) { |
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info->start[i] = base + (i * bootsect_size); |
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} |
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for (i = 8; i < info->sector_count; i++) { |
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info->start[i] = base + ((i - 7) * sect_size); |
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} |
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} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD |
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&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { |
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int sect_size; /* number of bytes/sector */ |
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sect_size = 0x00010000 * (sizeof (FPW) / 2); |
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/* set up sector start address table (uniform sector type) */ |
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for (i = 0; i < info->sector_count; i++) |
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info->start[i] = base + (i * sect_size); |
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} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD |
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&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { |
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int sect_size; /* number of bytes/sector */ |
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sect_size = 0x00010000 * (sizeof (FPW) / 2); |
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/* set up sector start address table (top boot sector type) */ |
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for (i = 0; i < info->sector_count - 3; i++) |
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info->start[i] = base + (i * sect_size); |
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i = info->sector_count - 1; |
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info->start[i--] = |
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base + (info->size - 0x00004000) * (sizeof (FPW) / 2); |
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info->start[i--] = |
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base + (info->size - 0x00006000) * (sizeof (FPW) / 2); |
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info->start[i--] = |
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base + (info->size - 0x00008000) * (sizeof (FPW) / 2); |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t * info) |
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{ |
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int i; |
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uchar *boottype; |
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uchar *bootletter; |
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uchar *fmt; |
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uchar botbootletter[] = "B"; |
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uchar topbootletter[] = "T"; |
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uchar botboottype[] = "bottom boot sector"; |
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uchar topboottype[] = "top boot sector"; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_AMD: |
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printf ("AMD "); |
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break; |
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case FLASH_MAN_BM: |
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printf ("BRIGHT MICRO "); |
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break; |
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case FLASH_MAN_FUJ: |
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printf ("FUJITSU "); |
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break; |
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case FLASH_MAN_SST: |
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printf ("SST "); |
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break; |
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case FLASH_MAN_STM: |
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printf ("STM "); |
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break; |
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case FLASH_MAN_INTEL: |
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printf ("INTEL "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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/* check for top or bottom boot, if it applies */ |
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if (info->flash_id & FLASH_BTYPE) { |
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boottype = botboottype; |
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bootletter = botbootletter; |
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} else { |
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boottype = topboottype; |
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bootletter = topbootletter; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_AM800T: |
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fmt = "29LV800B%s (8 Mbit, %s)\n"; |
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break; |
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case FLASH_AM640U: |
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fmt = "29LV641D (64 Mbit, uniform sectors)\n"; |
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break; |
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case FLASH_28F800C3B: |
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case FLASH_28F800C3T: |
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fmt = "28F800C3%s (8 Mbit, %s)\n"; |
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break; |
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case FLASH_INTEL800B: |
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case FLASH_INTEL800T: |
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fmt = "28F800B3%s (8 Mbit, %s)\n"; |
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break; |
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case FLASH_28F160C3B: |
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case FLASH_28F160C3T: |
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fmt = "28F160C3%s (16 Mbit, %s)\n"; |
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break; |
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case FLASH_INTEL160B: |
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case FLASH_INTEL160T: |
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fmt = "28F160B3%s (16 Mbit, %s)\n"; |
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break; |
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case FLASH_28F320C3B: |
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case FLASH_28F320C3T: |
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fmt = "28F320C3%s (32 Mbit, %s)\n"; |
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break; |
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case FLASH_INTEL320B: |
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case FLASH_INTEL320T: |
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fmt = "28F320B3%s (32 Mbit, %s)\n"; |
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break; |
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case FLASH_28F640C3B: |
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case FLASH_28F640C3T: |
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fmt = "28F640C3%s (64 Mbit, %s)\n"; |
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break; |
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case FLASH_INTEL640B: |
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case FLASH_INTEL640T: |
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fmt = "28F640B3%s (64 Mbit, %s)\n"; |
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break; |
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default: |
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fmt = "Unknown Chip Type\n"; |
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break; |
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} |
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printf (fmt, bootletter, boottype); |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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if ((i % 5) == 0) { |
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printf ("\n "); |
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} |
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printf (" %08lX%s", info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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ulong flash_get_size (FPWV * addr, flash_info_t * info) |
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{ |
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/* Write auto select command: read Manufacturer ID */ |
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/* Write auto select command sequence and test FLASH answer */ |
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addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ |
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addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ |
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addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ |
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/* The manufacturer codes are only 1 byte, so just use 1 byte.
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* This works for any bus width and any FLASH device width. |
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*/ |
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switch (addr[0] & 0xff) { |
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case (uchar) AMD_MANUFACT: |
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info->flash_id = FLASH_MAN_AMD; |
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break; |
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case (uchar) INTEL_MANUFACT: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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break; |
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} |
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/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ |
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if (info->flash_id != FLASH_UNKNOWN) |
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switch (addr[1]) { |
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case (FPW) AMD_ID_LV800T: |
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info->flash_id += FLASH_AM800T; |
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info->sector_count = 19; |
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info->size = 0x00100000 * (sizeof (FPW) / 2); |
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break; /* => 1 or 2 MiB */ |
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case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ |
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info->flash_id += FLASH_AM640U; |
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info->sector_count = 128; |
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info->size = 0x00800000 * (sizeof (FPW) / 2); |
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break; /* => 8 or 16 MB */ |
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case (FPW) INTEL_ID_28F800C3B: |
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info->flash_id += FLASH_28F800C3B; |
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info->sector_count = 23; |
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info->size = 0x00100000 * (sizeof (FPW) / 2); |
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break; /* => 1 or 2 MB */ |
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case (FPW) INTEL_ID_28F800B3B: |
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info->flash_id += FLASH_INTEL800B; |
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info->sector_count = 23; |
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info->size = 0x00100000 * (sizeof (FPW) / 2); |
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break; /* => 1 or 2 MB */ |
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case (FPW) INTEL_ID_28F160C3B: |
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info->flash_id += FLASH_28F160C3B; |
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info->sector_count = 39; |
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info->size = 0x00200000 * (sizeof (FPW) / 2); |
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break; /* => 2 or 4 MB */ |
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case (FPW) INTEL_ID_28F160B3B: |
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info->flash_id += FLASH_INTEL160B; |
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info->sector_count = 39; |
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info->size = 0x00200000 * (sizeof (FPW) / 2); |
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break; /* => 2 or 4 MB */ |
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case (FPW) INTEL_ID_28F320C3B: |
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info->flash_id += FLASH_28F320C3B; |
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info->sector_count = 71; |
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info->size = 0x00400000 * (sizeof (FPW) / 2); |
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break; /* => 4 or 8 MB */ |
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case (FPW) INTEL_ID_28F320B3B: |
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info->flash_id += FLASH_INTEL320B; |
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info->sector_count = 71; |
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info->size = 0x00400000 * (sizeof (FPW) / 2); |
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break; /* => 4 or 8 MB */ |
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case (FPW) INTEL_ID_28F640C3B: |
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info->flash_id += FLASH_28F640C3B; |
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info->sector_count = 135; |
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info->size = 0x00800000 * (sizeof (FPW) / 2); |
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break; /* => 8 or 16 MB */ |
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case (FPW) INTEL_ID_28F640B3B: |
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info->flash_id += FLASH_INTEL640B; |
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info->sector_count = 135; |
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info->size = 0x00800000 * (sizeof (FPW) / 2); |
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break; /* => 8 or 16 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* => no or unknown flash */ |
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} |
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flash_get_offsets ((ulong) addr, info); |
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/* Put FLASH back in read mode */ |
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flash_reset (info); |
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return (info->size); |
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} |
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#ifdef CFG_FLASH_PROTECTION |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_sync_real_protect (flash_info_t * info) |
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{ |
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FPWV *addr = (FPWV *) (info->start[0]); |
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FPWV *sect; |
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int i; |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F800C3B: |
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case FLASH_28F800C3T: |
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case FLASH_28F160C3B: |
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case FLASH_28F160C3T: |
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case FLASH_28F320C3B: |
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case FLASH_28F320C3T: |
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case FLASH_28F640C3B: |
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case FLASH_28F640C3T: |
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/* check for protected sectors */ |
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*addr = (FPW) 0x00900090; |
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for (i = 0; i < info->sector_count; i++) { |
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/* read sector protection at sector address, (A7 .. A0) = 0x02.
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* D0 = 1 for each device if protected. |
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* If at least one device is protected the sector is marked |
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* protected, but mixed protected and unprotected devices |
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* within a sector should never happen. |
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*/ |
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sect = (FPWV *) (info->start[i]); |
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info->protect[i] = |
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(sect[2] & (FPW) (0x00010001)) ? 1 : 0; |
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} |
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/* Put FLASH back in read mode */ |
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flash_reset (info); |
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break; |
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case FLASH_AM640U: |
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case FLASH_AM800T: |
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default: |
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/* no hardware protect that we support */ |
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break; |
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} |
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} |
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#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last) |
||||
{ |
||||
FPWV *addr; |
||||
int flag, prot, sect; |
||||
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; |
||||
ulong now, last; |
||||
int rcode = 0; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_INTEL800B: |
||||
case FLASH_INTEL160B: |
||||
case FLASH_INTEL320B: |
||||
case FLASH_INTEL640B: |
||||
case FLASH_28F800C3B: |
||||
case FLASH_28F160C3B: |
||||
case FLASH_28F320C3B: |
||||
case FLASH_28F640C3B: |
||||
case FLASH_AM640U: |
||||
case FLASH_AM800T: |
||||
break; |
||||
case FLASH_UNKNOWN: |
||||
default: |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect = s_first; sect <= s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
reset_timer_masked (); |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect <= s_last && rcode == 0; sect++) { |
||||
|
||||
if (info->protect[sect] != 0) /* protected, skip it */ |
||||
continue; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
reset_timer_masked (); |
||||
last = 0; |
||||
|
||||
addr = (FPWV *) (info->start[sect]); |
||||
if (intel) { |
||||
*addr = (FPW) 0x00500050; /* clear status register */ |
||||
*addr = (FPW) 0x00200020; /* erase setup */ |
||||
*addr = (FPW) 0x00D000D0; /* erase confirm */ |
||||
} else { |
||||
/* must be AMD style if not Intel */ |
||||
FPWV *base; /* first address in bank */ |
||||
|
||||
base = (FPWV *) (info->start[0]); |
||||
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ |
||||
base[0x02AA] = (FPW) 0x00550055; /* unlock */ |
||||
base[0x0555] = (FPW) 0x00800080; /* erase mode */ |
||||
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ |
||||
base[0x02AA] = (FPW) 0x00550055; /* unlock */ |
||||
*addr = (FPW) 0x00300030; /* erase sector */ |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts (); |
||||
|
||||
/* wait at least 50us for AMD, 80us for Intel.
|
||||
* Let's wait 1 ms. |
||||
*/ |
||||
udelay (1000); |
||||
|
||||
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { |
||||
if ((now = |
||||
get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
|
||||
if (intel) { |
||||
/* suspend erase */ |
||||
*addr = (FPW) 0x00B000B0; |
||||
} |
||||
|
||||
flash_reset (info); /* reset to read mode */ |
||||
rcode = 1; /* failed */ |
||||
break; |
||||
} |
||||
|
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1 * CFG_HZ) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
flash_reset (info); /* reset to read mode */ |
||||
} |
||||
|
||||
printf (" done\n"); |
||||
return rcode; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ |
||||
int bytes; /* number of bytes to program in current word */ |
||||
int left; /* number of bytes left to program */ |
||||
int i, res; |
||||
|
||||
for (left = cnt, res = 0; |
||||
left > 0 && res == 0; |
||||
addr += sizeof (data), left -= sizeof (data) - bytes) { |
||||
|
||||
bytes = addr & (sizeof (data) - 1); |
||||
addr &= ~(sizeof (data) - 1); |
||||
|
||||
/* combine source and destination data so can program
|
||||
* an entire word of 16 or 32 bits |
||||
*/ |
||||
#ifdef CFG_LITTLE_ENDIAN |
||||
for (i = 0; i < sizeof (data); i++) { |
||||
data >>= 8; |
||||
if (i < bytes || i - bytes >= left) |
||||
data += (*((uchar *) addr + i)) << 24; |
||||
else |
||||
data += (*src++) << 24; |
||||
} |
||||
#else |
||||
for (i = 0; i < sizeof (data); i++) { |
||||
data <<= 8; |
||||
if (i < bytes || i - bytes >= left) |
||||
data += *((uchar *) addr + i); |
||||
else |
||||
data += *src++; |
||||
} |
||||
#endif |
||||
|
||||
/* write one word to the flash */ |
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: |
||||
res = write_word_amd (info, (FPWV *) addr, data); |
||||
break; |
||||
case FLASH_MAN_INTEL: |
||||
res = write_word_intel (info, (FPWV *) addr, data); |
||||
break; |
||||
default: |
||||
/* unknown flash type, error! */ |
||||
printf ("missing or unknown FLASH type\n"); |
||||
res = 1; /* not really a timeout, but gives error */ |
||||
break; |
||||
} |
||||
} |
||||
|
||||
return (res); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for AMD FLASH |
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank |
||||
* (not an individual chip) is. |
||||
* |
||||
* returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) |
||||
{ |
||||
int flag; |
||||
int res = 0; /* result, assume success */ |
||||
FPWV *base; /* first address in flash bank */ |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*dest & data) != data) { |
||||
return (2); |
||||
} |
||||
|
||||
|
||||
base = (FPWV *) (info->start[0]); |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ |
||||
base[0x02AA] = (FPW) 0x00550055; /* unlock */ |
||||
base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ |
||||
|
||||
*dest = data; /* start programming the data */ |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts (); |
||||
|
||||
reset_timer_masked (); |
||||
|
||||
/* data polling for D7 */ |
||||
while (res == 0 |
||||
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { |
||||
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
||||
*dest = (FPW) 0x00F000F0; /* reset bank */ |
||||
res = 1; |
||||
} |
||||
} |
||||
|
||||
return (res); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for Intel FLASH |
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank |
||||
* (not an individual chip) is. |
||||
* |
||||
* returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) |
||||
{ |
||||
int flag; |
||||
int res = 0; /* result, assume success */ |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*dest & data) != data) { |
||||
return (2); |
||||
} |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
*dest = (FPW) 0x00500050; /* clear status register */ |
||||
*dest = (FPW) 0x00FF00FF; /* make sure in read mode */ |
||||
*dest = (FPW) 0x00400040; /* program setup */ |
||||
|
||||
*dest = data; /* start programming the data */ |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts (); |
||||
|
||||
reset_timer_masked (); |
||||
|
||||
while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { |
||||
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
||||
*dest = (FPW) 0x00B000B0; /* Suspend program */ |
||||
res = 1; |
||||
} |
||||
} |
||||
|
||||
if (res == 0 && (*dest & (FPW) 0x00100010)) |
||||
res = 1; /* write failed, time out error is close enough */ |
||||
|
||||
*dest = (FPW) 0x00500050; /* clear status register */ |
||||
*dest = (FPW) 0x00FF00FF; /* make sure in read mode */ |
||||
|
||||
return (res); |
||||
} |
||||
|
||||
#ifdef CFG_FLASH_PROTECTION |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
int flash_real_protect (flash_info_t * info, long sector, int prot) |
||||
{ |
||||
int rcode = 0; /* assume success */ |
||||
FPWV *addr; /* address of sector */ |
||||
FPW value; |
||||
|
||||
addr = (FPWV *) (info->start[sector]); |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_28F800C3B: |
||||
case FLASH_28F800C3T: |
||||
case FLASH_28F160C3B: |
||||
case FLASH_28F160C3T: |
||||
case FLASH_28F320C3B: |
||||
case FLASH_28F320C3T: |
||||
case FLASH_28F640C3B: |
||||
case FLASH_28F640C3T: |
||||
flash_reset (info); /* make sure in read mode */ |
||||
*addr = (FPW) 0x00600060L; /* lock command setup */ |
||||
if (prot) |
||||
*addr = (FPW) 0x00010001L; /* lock sector */ |
||||
else |
||||
*addr = (FPW) 0x00D000D0L; /* unlock sector */ |
||||
flash_reset (info); /* reset to read mode */ |
||||
|
||||
/* now see if it really is locked/unlocked as requested */ |
||||
*addr = (FPW) 0x00900090; |
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02.
|
||||
* D0 = 1 for each device if protected. |
||||
* If at least one device is protected the sector is marked |
||||
* protected, but return failure. Mixed protected and |
||||
* unprotected devices within a sector should never happen. |
||||
*/ |
||||
value = addr[2] & (FPW) 0x00010001; |
||||
if (value == 0) |
||||
info->protect[sector] = 0; |
||||
else if (value == (FPW) 0x00010001) |
||||
info->protect[sector] = 1; |
||||
else { |
||||
/* error, mixed protected and unprotected */ |
||||
rcode = 1; |
||||
info->protect[sector] = 1; |
||||
} |
||||
if (info->protect[sector] != prot) |
||||
rcode = 1; /* failed to protect/unprotect as requested */ |
||||
|
||||
/* reload all protection bits from hardware for now */ |
||||
flash_sync_real_protect (info); |
||||
break; |
||||
|
||||
case FLASH_AM640U: |
||||
case FLASH_AM800T: |
||||
default: |
||||
/* no hardware protect that we support */ |
||||
info->protect[sector] = prot; |
||||
break; |
||||
} |
||||
|
||||
return rcode; |
||||
} |
||||
#endif |
@ -0,0 +1,488 @@ |
||||
/* |
||||
* Most of this taken from Redboot hal_platform_setup.h with cleanup |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/arch/pxa-regs.h> |
||||
|
||||
DRAM_SIZE: .long CFG_DRAM_SIZE |
||||
|
||||
/* wait for coprocessor write complete */ |
||||
.macro CPWAIT reg |
||||
mrc p15,0,\reg,c2,c0,0 |
||||
mov \reg,\reg |
||||
sub pc,pc,#4 |
||||
.endm |
||||
|
||||
.globl memsetup
|
||||
memsetup: |
||||
|
||||
mov r10, lr |
||||
|
||||
/* Set up GPIO pins first */ |
||||
|
||||
ldr r0, =GPSR0 |
||||
ldr r1, =CFG_GPSR0_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GPSR1 |
||||
ldr r1, =CFG_GPSR1_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GPSR2 |
||||
ldr r1, =CFG_GPSR2_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GPCR0 |
||||
ldr r1, =CFG_GPCR0_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GPCR1 |
||||
ldr r1, =CFG_GPCR1_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GPCR2 |
||||
ldr r1, =CFG_GPCR2_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GRER0 |
||||
ldr r1, =CFG_GRER0_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GRER1 |
||||
ldr r1, =CFG_GRER1_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GRER2 |
||||
ldr r1, =CFG_GRER2_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GFER0 |
||||
ldr r1, =CFG_GFER0_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GFER1 |
||||
ldr r1, =CFG_GFER1_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GFER2 |
||||
ldr r1, =CFG_GFER2_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GPDR0 |
||||
ldr r1, =CFG_GPDR0_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GPDR1 |
||||
ldr r1, =CFG_GPDR1_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GPDR2 |
||||
ldr r1, =CFG_GPDR2_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GAFR0_L |
||||
ldr r1, =CFG_GAFR0_L_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GAFR0_U |
||||
ldr r1, =CFG_GAFR0_U_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GAFR1_L |
||||
ldr r1, =CFG_GAFR1_L_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GAFR1_U |
||||
ldr r1, =CFG_GAFR1_U_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GAFR2_L |
||||
ldr r1, =CFG_GAFR2_L_VAL |
||||
str r1, [r0] |
||||
|
||||
ldr r0, =GAFR2_U |
||||
ldr r1, =CFG_GAFR2_U_VAL |
||||
str r1, [r0] |
||||
|
||||
/* enable GPIO pins */ |
||||
ldr r0, =PSSR |
||||
ldr r1, =CFG_PSSR_VAL |
||||
str r1, [r0] |
||||
|
||||
|
||||
/********************************************************************* |
||||
Initlialize Memory Controller |
||||
|
||||
See PXA250 Operating System Developer's Guide |
||||
|
||||
pause for 200 uSecs- allow internal clocks to settle |
||||
*Note: only need this if hard reset... doing it anyway for now |
||||
*/ |
||||
|
||||
@ Step 1
|
||||
@ ---- Wait 200 usec
|
||||
ldr r3, =OSCR @ reset the OS Timer Count to zero
|
||||
mov r2, #0 |
||||
str r2, [r3] |
||||
ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
|
||||
1: |
||||
ldr r2, [r3] |
||||
cmp r4, r2 |
||||
bgt 1b |
||||
|
||||
mem_init: |
||||
@ get memory controller base address
|
||||
ldr r1, =MEMC_BASE |
||||
|
||||
@****************************************************************************
|
||||
@ Step 2
|
||||
@
|
||||
|
||||
@ Step 2a
|
||||
@ write msc0, read back to ensure data latches
|
||||
@
|
||||
ldr r2, =CFG_MSC0_VAL |
||||
str r2, [r1, #MSC0_OFFSET] |
||||
ldr r2, [r1, #MSC0_OFFSET] |
||||
|
||||
@ write msc1
|
||||
ldr r2, =CFG_MSC1_VAL |
||||
str r2, [r1, #MSC1_OFFSET] |
||||
ldr r2, [r1, #MSC1_OFFSET] |
||||
|
||||
@ write msc2
|
||||
ldr r2, =CFG_MSC2_VAL |
||||
str r2, [r1, #MSC2_OFFSET] |
||||
ldr r2, [r1, #MSC2_OFFSET] |
||||
|
||||
|
||||
@ Step 2b
|
||||
@ write mecr
|
||||
ldr r2, =CFG_MECR_VAL |
||||
str r2, [r1, #MECR_OFFSET] |
||||
|
||||
@ write mcmem0
|
||||
ldr r2, =CFG_MCMEM0_VAL |
||||
str r2, [r1, #MCMEM0_OFFSET] |
||||
|
||||
@ write mcmem1
|
||||
ldr r2, =CFG_MCMEM1_VAL |
||||
str r2, [r1, #MCMEM1_OFFSET] |
||||
|
||||
@ write mcatt0
|
||||
ldr r2, =CFG_MCATT0_VAL |
||||
str r2, [r1, #MCATT0_OFFSET] |
||||
|
||||
@ write mcatt1
|
||||
ldr r2, =CFG_MCATT1_VAL |
||||
str r2, [r1, #MCATT1_OFFSET] |
||||
|
||||
@ write mcio0
|
||||
ldr r2, =CFG_MCIO0_VAL |
||||
str r2, [r1, #MCIO0_OFFSET] |
||||
|
||||
@ write mcio1
|
||||
ldr r2, =CFG_MCIO1_VAL |
||||
str r2, [r1, #MCIO1_OFFSET] |
||||
|
||||
@ Step 2c
|
||||
@ fly-by-dma is defeatured on this part
|
||||
@ write flycnfg
|
||||
@ldr r2, =CFG_FLYCNFG_VAL
|
||||
@str r2, [r1, #FLYCNFG_OFFSET]
|
||||
|
||||
/* FIXME Does this sequence really make sense */ |
||||
#ifdef REDBOOT_WAY |
||||
@ Step 2d
|
||||
@ get the mdrefr settings
|
||||
ldr r3, =CFG_MDREFR_VAL |
||||
|
||||
@ extract DRI field (we need a valid DRI field)
|
||||
@
|
||||
ldr r2, =0xFFF |
||||
|
||||
@ valid DRI field in r3
|
||||
@
|
||||
and r3, r3, r2 |
||||
|
||||
@ get the reset state of MDREFR
|
||||
@
|
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
@ clear the DRI field
|
||||
@
|
||||
bic r4, r4, r2 |
||||
|
||||
@ insert the valid DRI field loaded above
|
||||
@
|
||||
orr r4, r4, r3 |
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
@ *Note: preserve the mdrefr value in r4 *
|
||||
|
||||
@****************************************************************************
|
||||
@ Step 3
|
||||
@
|
||||
@ NO SRAM
|
||||
|
||||
mov pc, r10 |
||||
|
||||
|
||||
@****************************************************************************
|
||||
@ Step 4
|
||||
@
|
||||
|
||||
@ Assumes previous mdrefr value in r4, if not then read current mdrefr
|
||||
|
||||
@ clear the free-running clock bits
|
||||
@ (clear K0Free, K1Free, K2Free
|
||||
@
|
||||
bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000) |
||||
|
||||
@ set K0RUN for CPLD clock
|
||||
@
|
||||
orr r4, r4, #0x00002000 |
||||
|
||||
@ set K1RUN if bank 0 installed
|
||||
@
|
||||
orr r4, r4, #0x00010000 |
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
@ deassert SLFRSH
|
||||
@
|
||||
bic r4, r4, #0x00400000 |
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
@ assert E1PIN
|
||||
@
|
||||
orr r4, r4, #0x00008000 |
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
nop |
||||
nop |
||||
#else |
||||
@ Step 2d
|
||||
@ get the mdrefr settings
|
||||
ldr r3, =CFG_MDREFR_VAL |
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
@ Step 4
|
||||
|
||||
@ set K0RUN for CPLD clock
|
||||
@
|
||||
orr r4, r4, #0x00002000 |
||||
|
||||
@ set K1RUN for bank 0
|
||||
@
|
||||
orr r4, r4, #0x00010000 |
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
@ deassert SLFRSH
|
||||
@
|
||||
bic r4, r4, #0x00400000 |
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
@ assert E1PIN
|
||||
@
|
||||
orr r4, r4, #0x00008000 |
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
nop |
||||
nop |
||||
#endif |
||||
|
||||
@ Step 4d
|
||||
@ fetch platform value of mdcnfg
|
||||
@
|
||||
ldr r2, =CFG_MDCNFG_VAL |
||||
|
||||
@ disable all sdram banks
|
||||
@
|
||||
bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) |
||||
bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) |
||||
|
||||
@ program banks 0/1 for bus width
|
||||
@
|
||||
bic r2, r2, #MDCNFG_DWID0 @0=32-bit
|
||||
|
||||
@ write initial value of mdcnfg, w/o enabling sdram banks
|
||||
@
|
||||
str r2, [r1, #MDCNFG_OFFSET] |
||||
|
||||
@ Step 4e
|
||||
@ pause for 200 uSecs
|
||||
@
|
||||
ldr r3, =OSCR @ reset the OS Timer Count to zero
|
||||
mov r2, #0 |
||||
str r2, [r3] |
||||
ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
|
||||
1: |
||||
ldr r2, [r3] |
||||
cmp r4, r2 |
||||
bgt 1b |
||||
|
||||
/* Why is this here??? */ |
||||
mov r0, #0x78 @turn everything off
|
||||
mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
|
||||
|
||||
@ Step 4f
|
||||
@ Access memory *not yet enabled* for CBR refresh cycles (8)
|
||||
@ - CBR is generated for all banks
|
||||
|
||||
ldr r2, =CFG_DRAM_BASE |
||||
str r2, [r2] |
||||
str r2, [r2] |
||||
str r2, [r2] |
||||
str r2, [r2] |
||||
str r2, [r2] |
||||
str r2, [r2] |
||||
str r2, [r2] |
||||
str r2, [r2] |
||||
|
||||
@ Step 4g
|
||||
@get memory controller base address
|
||||
@
|
||||
ldr r1, =MEMC_BASE |
||||
|
||||
@fetch current mdcnfg value
|
||||
@
|
||||
ldr r3, [r1, #MDCNFG_OFFSET] |
||||
|
||||
@enable sdram bank 0 if installed (must do for any populated bank)
|
||||
@
|
||||
orr r3, r3, #MDCNFG_DE0 |
||||
|
||||
@write back mdcnfg, enabling the sdram bank(s)
|
||||
@
|
||||
str r3, [r1, #MDCNFG_OFFSET] |
||||
|
||||
@ Step 4h
|
||||
@ write mdmrs
|
||||
@
|
||||
ldr r2, =CFG_MDMRS_VAL |
||||
str r2, [r1, #MDMRS_OFFSET] |
||||
|
||||
@ Done Memory Init
|
||||
|
||||
/*SET_LED 6 */ |
||||
|
||||
@********************************************************************
|
||||
@ Disable (mask) all interrupts at the interrupt controller
|
||||
@
|
||||
|
||||
@ clear the interrupt level register (use IRQ, not FIQ)
|
||||
@
|
||||
mov r1, #0 |
||||
ldr r2, =ICLR |
||||
str r1, [r2] |
||||
|
||||
@ Set interrupt mask register
|
||||
@
|
||||
ldr r1, =CFG_ICMR_VAL |
||||
ldr r2, =ICMR |
||||
str r1, [r2] |
||||
|
||||
@ ********************************************************************
|
||||
@ Disable the peripheral clocks, and set the core clock
|
||||
@
|
||||
|
||||
@ Turn Off ALL on-chip peripheral clocks for re-configuration
|
||||
@
|
||||
ldr r1, =CKEN |
||||
mov r2, #0 |
||||
str r2, [r1] |
||||
|
||||
@ set core clocks
|
||||
@
|
||||
ldr r2, =CFG_CCCR_VAL |
||||
ldr r1, =CCCR |
||||
str r2, [r1] |
||||
|
||||
#ifdef ENABLE32KHZ |
||||
@ enable the 32Khz oscillator for RTC and PowerManager
|
||||
@
|
||||
ldr r1, =OSCC |
||||
mov r2, #OSCC_OON |
||||
str r2, [r1] |
||||
|
||||
@ NOTE: spin here until OSCC.OOK get set,
|
||||
@ meaning the PLL has settled.
|
||||
@
|
||||
60: |
||||
ldr r2, [r1] |
||||
ands r2, r2, #1 |
||||
beq 60b |
||||
#endif |
||||
|
||||
@ Turn on needed clocks
|
||||
@
|
||||
ldr r1, =CKEN |
||||
ldr r2, =CFG_CKEN_VAL |
||||
str r2, [r1] |
||||
|
||||
/*SET_LED 7 */ |
||||
|
||||
/* Is this needed???? */ |
||||
#define NODEBUG |
||||
#ifdef NODEBUG |
||||
/*Disable software and data breakpoints */ |
||||
mov r0,#0 |
||||
mcr p15,0,r0,c14,c8,0 /* ibcr0 */ |
||||
mcr p15,0,r0,c14,c9,0 /* ibcr1 */ |
||||
mcr p15,0,r0,c14,c4,0 /* dbcon */ |
||||
|
||||
/*Enable all debug functionality */ |
||||
mov r0,#0x80000000 |
||||
mcr p14,0,r0,c10,c0,0 /* dcsr */ |
||||
|
||||
#endif |
||||
|
||||
mov pc, r10 |
||||
|
||||
@ End memsetup
|
@ -0,0 +1,76 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm-arm/mach-types.h> |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* memory and cpu-speed are setup before relocation */ |
||||
/* so we do _nothing_ here */ |
||||
|
||||
/* arch number of Lubbock-Board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_PLEB2; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0xa0000100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
setenv("stdout", "serial"); |
||||
setenv("stderr", "serial"); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int dram_init (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
||||
gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
||||
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
||||
gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
||||
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,55 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/pxa/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
@ -0,0 +1,250 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* Configuration settings for the PLEB 2 board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram |
||||
* so we MUST NOT initialize critical regs like mem-timing ... |
||||
*/ |
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */ |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_PXA250 1 /* This is an PXA255 CPU */ |
||||
#define CONFIG_PLEB2 1 /* on an PLEB2 Board */ |
||||
#undef CONFIG_LCD |
||||
#undef CONFIG_MMC |
||||
#define BOARD_LATE_INIT 1 |
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
/* None - PLEB 2 doesn't have any of this.
|
||||
#define CONFIG_DRIVER_LAN91C96 |
||||
#define CONFIG_LAN91C96_BASE 0x0C000000 */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */ |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b |
||||
#define CONFIG_NETMASK 255.255.0.0 |
||||
#define CONFIG_IPADDR 192.168.0.21 |
||||
#define CONFIG_SERVERIP 192.168.0.250 |
||||
#define CONFIG_BOOTCOMMAND "bootm 40000" |
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200" |
||||
|
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_HUSH_PARSER 1 |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT "$ " /* Monitor Command Prompt */ |
||||
#else |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#endif |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_DEVICE_NULLDEV 1 |
||||
|
||||
#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
|
||||
#define CFG_LOAD_ADDR 0xa2000000 /* default load address */ |
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ |
||||
#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ |
||||
|
||||
/* valid baudrates */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ |
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ |
||||
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ |
||||
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ |
||||
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ |
||||
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ |
||||
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ |
||||
#define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */ |
||||
|
||||
/* Not entirely sure about this - DS/CHC */ |
||||
#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ |
||||
#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ |
||||
|
||||
#define CFG_DRAM_BASE PHYS_SDRAM_1 |
||||
#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE |
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
|
||||
/*
|
||||
* GPIO settings |
||||
*/ |
||||
#define CFG_GPSR0_VAL 0x00000000 /* Don't set anything */ |
||||
#define CFG_GPSR1_VAL 0x00000080 |
||||
#define CFG_GPSR2_VAL 0x00000000 |
||||
|
||||
#define CFG_GPCR0_VAL 0x00000000 /* Don't clear anything */ |
||||
#define CFG_GPCR1_VAL 0x00000000 |
||||
#define CFG_GPCR2_VAL 0x00000000 |
||||
|
||||
#define CFG_GPDR0_VAL 0x00000000 |
||||
#define CFG_GPDR1_VAL 0x000007C3 |
||||
#define CFG_GPDR2_VAL 0x00000000 |
||||
|
||||
/* Edge detect registers (these are set by the kernel) */ |
||||
#define CFG_GRER0_VAL 0x00000000 |
||||
#define CFG_GRER1_VAL 0x00000000 |
||||
#define CFG_GRER2_VAL 0x00000000 |
||||
#define CFG_GFER0_VAL 0x00000000 |
||||
#define CFG_GFER1_VAL 0x00000000 |
||||
#define CFG_GFER2_VAL 0x00000000 |
||||
|
||||
#define CFG_GAFR0_L_VAL 0x00000000 |
||||
#define CFG_GAFR0_U_VAL 0x00000000 |
||||
#define CFG_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */ |
||||
#define CFG_GAFR1_U_VAL 0x00000000 |
||||
#define CFG_GAFR2_L_VAL 0x00000000 |
||||
#define CFG_GAFR2_U_VAL 0x00000000 |
||||
|
||||
#define CFG_PSSR_VAL 0x20 |
||||
#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ |
||||
#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ |
||||
#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ |
||||
|
||||
/*
|
||||
* Memory settings |
||||
*/ |
||||
#define CFG_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */ |
||||
#define CFG_MSC1_VAL 0x00000000 |
||||
#define CFG_MSC2_VAL 0x00000000 |
||||
|
||||
#define CFG_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM. |
||||
tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */ |
||||
|
||||
#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual |
||||
bits set in memsetup.S */ |
||||
#define CFG_MDMRS_VAL 0x00000000 |
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces |
||||
*/ |
||||
#define CFG_MECR_VAL 0x00000000 /* Hangover from Lubbock. |
||||
Needs calculating. (DS/CHC) */ |
||||
#define CFG_MCMEM0_VAL 0x00010504 |
||||
#define CFG_MCMEM1_VAL 0x00010504 |
||||
#define CFG_MCATT0_VAL 0x00010504 |
||||
#define CFG_MCATT1_VAL 0x00010504 |
||||
#define CFG_MCIO0_VAL 0x00004715 |
||||
#define CFG_MCIO1_VAL 0x00004715 |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
||||
|
||||
/* timeout values are in ticks */ |
||||
/* FIXME */ |
||||
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ |
||||
|
||||
/* Flash protection */ |
||||
#define CFG_FLASH_PROTECTION 1 |
||||
|
||||
/* FIXME */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ |
||||
#define CFG_ENV_SECT_SIZE 0x20000 |
||||
|
||||
/* Option added to get around byte ordering issues in the flash driver */ |
||||
#define CFG_LITTLE_ENDIAN 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue