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@ -179,7 +179,7 @@ int board_early_init_r (void) |
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ulong temp, i; |
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ulong reg_val; |
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volatile ulong *reg_ptr; |
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reg_ptr = |
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(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); |
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@ -300,7 +300,7 @@ int board_early_init_r (void) |
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, |
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0x7C0F2000); |
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__asm__ __volatile__ ("sync"); |
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/*
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* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. |
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* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) |
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@ -312,7 +312,7 @@ int board_early_init_r (void) |
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/* Make sure that OCN_BAR2 decoder is set (to allow following
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* immediate read from SDRAM) |
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*/ |
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temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); |
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__asm__ __volatile__ ("sync"); |
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@ -327,11 +327,11 @@ int board_early_init_r (void) |
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* and enable all HLP banks and not just HLP 0 as is being done for |
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* Taiga Rev. 2. |
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*/ |
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env_init (); |
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#ifndef DISABLE_PBM |
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/*
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* For IBM processors we have to set Address-Only commands generated |
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* by PBM that are different from ones set after reset. |
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@ -475,10 +475,10 @@ int board_early_init_r (void) |
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for (i = 0; i < 32; i++) { |
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*reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */ |
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/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ |
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*reg_ptr++ = 0;
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*reg_ptr++ = 0; |
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/* offset = 16MB, address translation is enabled to allow byte swapping */ |
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reg_val += 0x01000000; |
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} |
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@ -507,7 +507,7 @@ int board_early_init_r (void) |
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#endif /* !DISABLE_PBM */ |
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#ifdef ENABLE_PCI_CSR_BAR |
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#ifdef ENABLE_PCI_CSR_BAR |
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/* open if required access to Tsi108 CSRs from the PCI/X bus */ |
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/* enable BAR0 on the PCI/X bus */ |
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reg_val = in32(CFG_TSI108_CSR_BASE + |
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@ -528,7 +528,7 @@ int board_early_init_r (void) |
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/*
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* Finally enable PCI/X Bus Master and Memory Space access |
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*/ |
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reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); |
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reg_val |= 0x06; |
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out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); |
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@ -555,7 +555,7 @@ int board_early_init_r (void) |
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* Ensure that Machine Check exception is enabled |
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* We need it to support PCI Bus probing (configuration reads) |
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*/ |
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reg_val = mfmsr (); |
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mtmsr(reg_val | MSR_ME); |
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@ -631,7 +631,7 @@ int misc_init_r (void) |
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* thing done with regards to enabling diabling the cache. |
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* So this seems like a good place to print all this information |
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*/ |
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printf ("CACHE: "); |
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switch (get_cpu_type()) { |
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case CPU_7447A: |
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