powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases

Previously we used an alias the pci node to determine which node to
fixup or delete.  Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.

Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

arch/powerpc/include/asm/fsl_pci.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -29,8 +29,8 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);
 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
 void fsl_pci_config_unlock(struct pci_controller *hose);
-void ft_fsl_pci_setup(void *blob, const char *pci_alias,
-			struct pci_controller *hose);
+void ft_fsl_pci_setup(void *blob, const char *pci_compat,
+			struct pci_controller *hose, unsigned long ctrl_addr);
 
 /*
  * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
@@ -202,4 +202,82 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	x.pci_num = num; \
 }
 
+#define __FT_FSL_PCI_SETUP(blob, compat, num) \
+	ft_fsl_pci_setup(blob, compat, &pci##num##_hose, \
+			 CONFIG_SYS_PCI##num##_ADDR)
+
+#define __FT_FSL_PCI_DEL(blob, compat, num) \
+	ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCI##num##_ADDR)
+
+#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
+	ft_fsl_pci_setup(blob, compat, &pcie##num##_hose, \
+			 CONFIG_SYS_PCIE##num##_ADDR)
+
+#define __FT_FSL_PCIE_DEL(blob, compat, num) \
+	ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCIE##num##_ADDR)
+
+#ifdef CONFIG_PCI1
+#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
+#else
+#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 1)
+#endif
+
+#ifdef CONFIG_PCI2
+#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
+#else
+#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 2)
+#endif
+
+#ifdef CONFIG_PCIE1
+#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
+#else
+#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 1)
+#endif
+
+#ifdef CONFIG_PCIE2
+#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
+#else
+#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 2)
+#endif
+
+#ifdef CONFIG_PCIE3
+#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
+#else
+#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 3)
+#endif
+
+#ifdef CONFIG_PCIE4
+#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
+#else
+#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 4)
+#endif
+
+#if defined(CONFIG_FSL_CORENET)
+#define FSL_PCIE_COMPAT	"fsl,p4080-pcie"
+#define FT_FSL_PCI_SETUP \
+	FT_FSL_PCIE1_SETUP; \
+	FT_FSL_PCIE2_SETUP; \
+	FT_FSL_PCIE3_SETUP; \
+	FT_FSL_PCIE4_SETUP;
+#elif defined(CONFIG_MPC85xx)
+#define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
+#define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"
+#define FT_FSL_PCI_SETUP \
+	FT_FSL_PCI1_SETUP; \
+	FT_FSL_PCI2_SETUP; \
+	FT_FSL_PCIE1_SETUP; \
+	FT_FSL_PCIE2_SETUP; \
+	FT_FSL_PCIE3_SETUP;
+#elif defined(CONFIG_MPC86xx)
+#define FSL_PCI_COMPAT	"fsl,mpc8610-pci"
+#define FSL_PCIE_COMPAT	"fsl,mpc8641-pcie"
+#define FT_FSL_PCI_SETUP \
+	FT_FSL_PCI1_SETUP; \
+	FT_FSL_PCIE1_SETUP; \
+	FT_FSL_PCIE2_SETUP;
+#else
+#error FT_FSL_PCI_SETUP not defined
+#endif
+
+
 #endif

board/atum8548/atum8548.c

@@ -292,14 +292,6 @@ void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCI2
-	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 }
 #endif

board/freescale/mpc8536ds/mpc8536ds.c

@@ -396,26 +396,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#else
-	ft_fsl_pci_setup(blob, "pci0", NULL);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#else
-	ft_fsl_pci_setup(blob, "pci1", NULL);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#else
-	ft_fsl_pci_setup(blob, "pci2", NULL);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
-#else
-	ft_fsl_pci_setup(blob, "pci3", NULL);
-#endif
+	FT_FSL_PCI_SETUP;
+
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
 #endif

board/freescale/mpc8544ds/mpc8544ds.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -360,19 +360,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
+	FT_FSL_PCI_SETUP;
 
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE3
-	ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
-#endif
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
 #endif

board/freescale/mpc8548cds/mpc8548cds.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007, 200 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
@@ -388,11 +388,6 @@ int last_stage_init(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_pci_setup(void *blob, bd_t *bd)
 {
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 }
 #endif

board/freescale/mpc8568mds/mpc8568mds.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
@@ -426,11 +426,6 @@ void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 }
 #endif

board/freescale/mpc8569mds/mpc8569mds.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor.
+ * Copyright 2009-2010 Freescale Semiconductor.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
@@ -635,9 +635,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+	FT_FSL_PCI_SETUP;
+
 	fdt_board_fixup_esdhc(blob, bd);
 	fdt_board_fixup_qe_uart(blob, bd);
 	fdt_board_fixup_qe_usb(blob, bd);

board/freescale/mpc8572ds/mpc8572ds.c

@@ -345,15 +345,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-#ifdef CONFIG_PCIE3
-	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+	FT_FSL_PCI_SETUP;
+
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
 #endif

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -309,15 +309,7 @@ ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 }
 #endif
 

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -253,12 +253,7 @@ ft_board_setup(void *blob, bd_t *bd)
 
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 
 	/*
 	 * Warn if it looks like the device tree doesn't match u-boot.

board/freescale/p1022ds/p1022ds.c

@@ -322,23 +322,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
-#else
-	ft_fsl_pci_setup(blob, "pci0", NULL);
-#endif
-
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#else
-	ft_fsl_pci_setup(blob, "pci1", NULL);
-#endif
-
-#ifdef CONFIG_PCIE3
-	ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
-#else
-	ft_fsl_pci_setup(blob, "pci2", NULL);
-#endif
+	FT_FSL_PCI_SETUP;
 
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);

board/freescale/p1_p2_rdb/pci.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -100,16 +100,5 @@ void pci_init_board(void)
 
 void ft_pci_board_setup(void *blob)
 {
-/* According to h/w manual, PCIE2 is at lower address(0x9000)
- * than PCIE1(0xa000).
- * Hence PCIE2 is made to occupy the pci1 position in dts to
- * keep the addresses sorted there.
- * Generally the case with all FSL SOCs.
- */
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 }

board/freescale/p2020ds/p2020ds.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -366,15 +366,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-#ifdef CONFIG_PCIE3
-	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+	FT_FSL_PCI_SETUP;
+
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
 #endif

board/sbc8548/sbc8548.c

@@ -398,11 +398,9 @@ int last_stage_init(void)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
+
+#ifdef CONFIG_FSL_PCI_INIT
+	FT_FSL_PCI_SETUP;
 #endif
 }
 #endif

board/sbc8641d/sbc8641d.c

@@ -308,12 +308,7 @@ void ft_board_setup (void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 }
 #endif
 

board/tqc/tqm85xx/tqm85xx.c

@@ -687,12 +687,7 @@ void ft_board_setup (void *blob, bd_t *bd)
 {
 	ft_cpu_setup (blob, bd);
 
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 }
 #endif /* CONFIG_OF_BOARD_SETUP */
 

board/xes/common/fsl_8xxx_pci.c

@@ -398,18 +398,6 @@ void pci_init_board(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_pci_setup(void *blob, bd_t *bd)
 {
-	/* TODO - make node name (eg pci0) dynamic */
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE3
-	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 }
 #endif /* CONFIG_OF_BOARD_SETUP */

drivers/pci/fsl_pci_init.c

@@ -510,18 +510,25 @@ void fsl_pci_config_unlock(struct pci_controller *hose)
 #include <libfdt.h>
 #include <fdt_support.h>
 
-void ft_fsl_pci_setup(void *blob, const char *pci_alias,
-			struct pci_controller *hose)
+void ft_fsl_pci_setup(void *blob, const char *pci_compat,
+			struct pci_controller *hose, unsigned long ctrl_addr)
 {
-	int off = fdt_path_offset(blob, pci_alias);
+	int off;
 	u32 bus_range[2];
+	phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
+
+	/* convert ctrl_addr to true physical address */
+	p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
+	p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
+
+	off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
 
 	if (off < 0)
 		return;
 
 	/* We assume a cfg_addr not being set means we didn't setup the controller */
 	if ((hose == NULL) || (hose->cfg_addr == NULL)) {
-		fdt_del_node_and_alias(blob, pci_alias);
+		fdt_del_node(blob, off);
 	} else {
 		bus_range[0] = 0;
 		bus_range[1] = hose->last_busno - hose->first_busno;