Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add new board specific commands for TQM5200/STK52XX

Browse Source 
- Sound commands (beep, wav, sound)
- Test commands (led, can, backlight, rs232)
Patch by Martin Krause, 02 May 2005
master
Wolfgang Denk 19 years ago
parent df3c7c8f52
commit 6617aae9b9
9 changed files with 1338 additions and 15 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 7
      CHANGELOG
  2. 2
      board/cmc_pu2/cmc_pu2.c
  3. 1
      board/o2dnt/flash.c
  4. 2
      board/tqm5200/Makefile
  5. 1221
      board/tqm5200/cmd_stk52xx.c
  6. 4
      common/cmd_eeprom.c
  7. 3
      include/configs/TQM5200.h
  8. 4
      include/configs/o2dnt.h
  9. 109
      include/mpc5xxx.h

7
CHANGELOG
Unescape View File

@ -2,7 +2,12 @@
Changes for U-Boot 1.1.4:
======================================================================
* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz
* Add new board specific commands for TQM5200/STK52XX
- Sound commands (beep, wav, sound)
- Test commands (led, can, backlight, rs232)
Patch by Martin Krause, 02 May 2005
* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz
because of a bug in the AT91RM9200 CPU PLL
Patch by Martin Krause, 22 Apr 2005

2
board/cmc_pu2/cmc_pu2.c
Unescape View File

@ -138,7 +138,7 @@ int hw_detect (void)
pio->PIO_ODR = AT91C_PIO_PB12;
pio->PIO_PPUDR = AT91C_PIO_PB12;
pio->PIO_PER = AT91C_PIO_PB12;
/* configure PB13 as input without pull up */
pio->PIO_ODR = AT91C_PIO_PB13;
pio->PIO_PPUDR = AT91C_PIO_PB13;

1
board/o2dnt/flash.c
Unescape View File

@ -585,4 +585,3 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
return ret;
}

2
board/tqm5200/Makefile
Unescape View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
#OBJS := $(BOARD).o flash.o
OBJS := $(BOARD).o
OBJS := $(BOARD).o cmd_stk52xx.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)

1221
board/tqm5200/cmd_stk52xx.c
View File

File diff suppressed because it is too large Load Diff

4
common/cmd_eeprom.c
Unescape View File

@ -28,10 +28,10 @@
* FRAM devices read and write data at bus speed. In particular, there is no
* write delay. Also, there is no limit imposed on the numer of bytes that can
* be transferred with a single read or write.
*
*
* Use the following configuration options to ensure no unneeded performance
* degradation (typical for EEPROM) is incured for FRAM memory:
*
*
* #define CFG_I2C_FRAM
* #undef CFG_EEPROM_PAGE_WRITE_DELAY_MS
*

3
include/configs/TQM5200.h
Unescape View File

@ -169,7 +169,8 @@
CFG_CMD_PING | \
CFG_CMD_POST_DIAG | \
CFG_CMD_REGINFO | \
CFG_CMD_SNTP )
CFG_CMD_SNTP | \
CFG_CMD_BSP)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

4
include/configs/o2dnt.h
Unescape View File

@ -225,8 +225,8 @@
/*
* GPIO configuration
*/
//#define CFG_GPS_PORT_CONFIG 0x10002004
#define CFG_GPS_PORT_CONFIG 0x00002004 //no CAN
/*#define CFG_GPS_PORT_CONFIG 0x10002004 */
#define CFG_GPS_PORT_CONFIG 0x00002004 /* no CAN */
/*
* Miscellaneous configurable options

109
include/mpc5xxx.h
Unescape View File

@ -91,6 +91,7 @@
#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
#define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00)
#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
#define MPC5XXX_SPI (CFG_MBAR + 0x0f00)
#define MPC5XXX_USB (CFG_MBAR + 0x1000)
#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
@ -381,17 +382,18 @@ struct mpc5xxx_psc {
volatile u8 ctur; /* PSC + 0x18 */
volatile u8 reserved5[3];
volatile u8 ctlr; /* PSC + 0x1c */
volatile u8 reserved6[19];
volatile u8 reserved6[3];
volatile u16 ccr; /* PSC + 0x20 */
volatile u8 reserved7[14];
volatile u8 ivr; /* PSC + 0x30 */
volatile u8 reserved7[3];
volatile u8 ip; /* PSC + 0x34 */
volatile u8 reserved8[3];
volatile u8 op1; /* PSC + 0x38 */
volatile u8 ip; /* PSC + 0x34 */
volatile u8 reserved9[3];
volatile u8 op0; /* PSC + 0x3c */
volatile u8 op1; /* PSC + 0x38 */
volatile u8 reserved10[3];
volatile u8 sicr; /* PSC + 0x40 */
volatile u8 op0; /* PSC + 0x3c */
volatile u8 reserved11[3];
volatile u32 sicr; /* PSC + 0x40 */
volatile u8 ircr1; /* PSC + 0x44 */
volatile u8 reserved12[3];
volatile u8 ircr2; /* PSC + 0x44 */
@ -599,6 +601,101 @@ struct mpc5xxx_i2c {
volatile u32 mdr; /* I2Cn + 0x10 */
};
struct mpc5xxx_spi {
volatile u8 cr1; /* SPI + 0x0F00 */
volatile u8 cr2; /* SPI + 0x0F01 */
volatile u8 reserved1[2];
volatile u8 brr; /* SPI + 0x0F04 */
volatile u8 sr; /* SPI + 0x0F05 */
volatile u8 reserved2[3];
volatile u8 dr; /* SPI + 0x0F09 */
volatile u8 reserved3[3];
volatile u8 pdr; /* SPI + 0x0F0D */
volatile u8 reserved4[2];
volatile u8 ddr; /* SPI + 0x0F10 */
};
struct mpc5xxx_gpt {
volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */
volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */
volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */
volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */
};
struct mpc5xxx_gpt_0_7 {
struct mpc5xxx_gpt gpt0;
struct mpc5xxx_gpt gpt1;
struct mpc5xxx_gpt gpt2;
struct mpc5xxx_gpt gpt3;
struct mpc5xxx_gpt gpt4;
struct mpc5xxx_gpt gpt5;
struct mpc5xxx_gpt gpt6;
struct mpc5xxx_gpt gpt7;
};
struct mscan_buffer {
volatile u8 idr[0x8]; /* 0x00 */
volatile u8 dsr[0x10]; /* 0x08 */
volatile u8 dlr; /* 0x18 */
volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
volatile u16 rsrv1; /* 0x1A */
volatile u8 tsrh; /* 0x1C */
volatile u8 tsrl; /* 0x1D */
volatile u16 rsrv2; /* 0x1E */
};
struct mpc5xxx_mscan {
volatile u8 canctl0; /* MSCAN + 0x00 */
volatile u8 canctl1; /* MSCAN + 0x01 */
volatile u16 rsrv1; /* MSCAN + 0x02 */
volatile u8 canbtr0; /* MSCAN + 0x04 */
volatile u8 canbtr1; /* MSCAN + 0x05 */
volatile u16 rsrv2; /* MSCAN + 0x06 */
volatile u8 canrflg; /* MSCAN + 0x08 */
volatile u8 canrier; /* MSCAN + 0x09 */
volatile u16 rsrv3; /* MSCAN + 0x0A */
volatile u8 cantflg; /* MSCAN + 0x0C */
volatile u8 cantier; /* MSCAN + 0x0D */
volatile u16 rsrv4; /* MSCAN + 0x0E */
volatile u8 cantarq; /* MSCAN + 0x10 */
volatile u8 cantaak; /* MSCAN + 0x11 */
volatile u16 rsrv5; /* MSCAN + 0x12 */
volatile u8 cantbsel; /* MSCAN + 0x14 */
volatile u8 canidac; /* MSCAN + 0x15 */
volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
volatile u8 canrxerr; /* MSCAN + 0x1C */
volatile u8 cantxerr; /* MSCAN + 0x1D */
volatile u16 rsrv7; /* MSCAN + 0x1E */
volatile u8 canidar0; /* MSCAN + 0x20 */
volatile u8 canidar1; /* MSCAN + 0x21 */
volatile u16 rsrv8; /* MSCAN + 0x22 */
volatile u8 canidar2; /* MSCAN + 0x24 */
volatile u8 canidar3; /* MSCAN + 0x25 */
volatile u16 rsrv9; /* MSCAN + 0x26 */
volatile u8 canidmr0; /* MSCAN + 0x28 */
volatile u8 canidmr1; /* MSCAN + 0x29 */
volatile u16 rsrv10; /* MSCAN + 0x2A */
volatile u8 canidmr2; /* MSCAN + 0x2C */
volatile u8 canidmr3; /* MSCAN + 0x2D */
volatile u16 rsrv11; /* MSCAN + 0x2E */
volatile u8 canidar4; /* MSCAN + 0x30 */
volatile u8 canidar5; /* MSCAN + 0x31 */
volatile u16 rsrv12; /* MSCAN + 0x32 */
volatile u8 canidar6; /* MSCAN + 0x34 */
volatile u8 canidar7; /* MSCAN + 0x35 */
volatile u16 rsrv13; /* MSCAN + 0x36 */
volatile u8 canidmr4; /* MSCAN + 0x38 */
volatile u8 canidmr5; /* MSCAN + 0x39 */
volatile u16 rsrv14; /* MSCAN + 0x3A */
volatile u8 canidmr6; /* MSCAN + 0x3C */
volatile u8 canidmr7; /* MSCAN + 0x3D */
volatile u16 rsrv15; /* MSCAN + 0x3E */
struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
};
/* function prototypes */
void loadtask(int basetask, int tasks);

Write Preview
Loading…
Cancel
Save