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@ -19,29 +19,6 @@ static struct cpu_type cpu_type_list[] = { |
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#ifndef CONFIG_SYS_DCACHE_OFF |
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#define SECTION_SHIFT_L0 39UL |
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#define SECTION_SHIFT_L1 30UL |
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#define SECTION_SHIFT_L2 21UL |
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#define BLOCK_SIZE_L0 0x8000000000 |
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#define BLOCK_SIZE_L1 0x40000000 |
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#define BLOCK_SIZE_L2 0x200000 |
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#define NUM_OF_ENTRY 512 |
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#define TCR_EL2_PS_40BIT (2 << 16) |
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#define LAYERSCAPE_VA_BITS (40) |
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#define LAYERSCAPE_TCR (TCR_TG0_4K | \ |
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TCR_EL2_PS_40BIT | \
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TCR_SHARED_NON | \
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TCR_ORGN_NC | \
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TCR_IRGN_NC | \
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TCR_T0SZ(LAYERSCAPE_VA_BITS)) |
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#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \ |
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TCR_EL2_PS_40BIT | \
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TCR_SHARED_OUTER | \
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TCR_ORGN_WBWA | \
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TCR_IRGN_WBWA | \
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TCR_T0SZ(LAYERSCAPE_VA_BITS)) |
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#ifdef CONFIG_FSL_LSCH3 |
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#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 |
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#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 |
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@ -101,174 +78,261 @@ static struct cpu_type cpu_type_list[] = { |
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#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ |
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#endif |
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struct sys_mmu_table { |
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u64 virt_addr; |
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u64 phys_addr; |
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u64 size; |
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u64 memory_type; |
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u64 attribute; |
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}; |
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struct table_info { |
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u64 *ptr; |
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u64 table_base; |
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u64 entry_size; |
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}; |
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static const struct sys_mmu_table early_mmu_table[] = { |
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#define EARLY_PGTABLE_SIZE 0x5000 |
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static struct mm_region early_map[] = { |
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#ifdef CONFIG_FSL_LSCH3 |
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, |
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CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_CCSR_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, |
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CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, |
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CONFIG_SYS_FSL_OCRAM_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, |
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CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE}, |
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CONFIG_SYS_FSL_QSPI_SIZE1, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, |
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/* For IFC Region #1, only the first 4MB is cache-enabled */ |
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{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, |
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CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE }, |
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CONFIG_SYS_FSL_IFC_SIZE1_1, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, |
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CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, |
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CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, |
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MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, |
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CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, |
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CONFIG_SYS_FSL_IFC_SIZE1, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, |
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CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, |
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CONFIG_SYS_FSL_DRAM_SIZE1, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS |
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}, |
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/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ |
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{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, |
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CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, |
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MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, |
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CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_DCSR_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, |
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CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, |
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CONFIG_SYS_FSL_DRAM_SIZE2, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS |
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}, |
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#elif defined(CONFIG_FSL_LSCH2) |
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, |
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CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_CCSR_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, |
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CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, |
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CONFIG_SYS_FSL_OCRAM_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, |
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CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_DCSR_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, |
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CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, |
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CONFIG_SYS_FSL_QSPI_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, |
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CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, |
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CONFIG_SYS_FSL_IFC_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, |
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CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, |
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CONFIG_SYS_FSL_DRAM_SIZE1, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS |
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}, |
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, |
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CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, |
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CONFIG_SYS_FSL_DRAM_SIZE2, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS |
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}, |
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#endif |
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{}, /* list terminator */ |
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}; |
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static const struct sys_mmu_table final_mmu_table[] = { |
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static struct mm_region final_map[] = { |
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#ifdef CONFIG_FSL_LSCH3 |
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, |
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CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_CCSR_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, |
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CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, |
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CONFIG_SYS_FSL_OCRAM_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, |
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CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, |
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CONFIG_SYS_FSL_DRAM_SIZE1, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS |
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}, |
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{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, |
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CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE}, |
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CONFIG_SYS_FSL_QSPI_SIZE1, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, |
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CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_QSPI_SIZE2, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, |
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CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, |
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CONFIG_SYS_FSL_IFC_SIZE2, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, |
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CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_DCSR_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, |
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CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_MC_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, |
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CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_NI_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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/* For QBMAN portal, only the first 64MB is cache-enabled */ |
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{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, |
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CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS }, |
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CONFIG_SYS_FSL_QBMAN_SIZE_1, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS |
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}, |
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{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, |
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CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, |
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CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, |
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MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, |
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CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_PCIE1_PHYS_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, |
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CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_PCIE2_PHYS_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, |
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CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_PCIE3_PHYS_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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#ifdef CONFIG_LS2080A |
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{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, |
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CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_PCIE4_PHYS_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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#endif |
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{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, |
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CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_WRIOP1_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, |
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CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_AIOP1_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, |
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CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_PEBUF_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, |
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CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, |
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CONFIG_SYS_FSL_DRAM_SIZE2, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS |
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}, |
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#elif defined(CONFIG_FSL_LSCH2) |
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{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, |
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CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_BOOTROM_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, |
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CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
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CONFIG_SYS_FSL_CCSR_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, |
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CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, |
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CONFIG_SYS_FSL_OCRAM_SIZE, |
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE |
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}, |
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, |
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CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, |
|
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|
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
|
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|
|
CONFIG_SYS_FSL_DCSR_SIZE, |
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|
|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
|
|
|
|
}, |
|
|
|
|
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, |
|
|
|
|
CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
|
|
|
|
CONFIG_SYS_FSL_QSPI_SIZE, |
|
|
|
|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
|
|
|
|
}, |
|
|
|
|
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, |
|
|
|
|
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, |
|
|
|
|
CONFIG_SYS_FSL_IFC_SIZE, |
|
|
|
|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
|
|
|
|
}, |
|
|
|
|
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, |
|
|
|
|
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, |
|
|
|
|
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, |
|
|
|
|
CONFIG_SYS_FSL_DRAM_SIZE1, |
|
|
|
|
PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
|
|
|
|
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS |
|
|
|
|
}, |
|
|
|
|
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, |
|
|
|
|
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
|
|
|
|
CONFIG_SYS_FSL_QBMAN_SIZE, |
|
|
|
|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
|
|
|
|
}, |
|
|
|
|
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, |
|
|
|
|
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, |
|
|
|
|
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, |
|
|
|
|
CONFIG_SYS_FSL_DRAM_SIZE2, |
|
|
|
|
PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
|
|
|
|
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS |
|
|
|
|
}, |
|
|
|
|
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, |
|
|
|
|
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
|
|
|
|
CONFIG_SYS_PCIE1_PHYS_SIZE, |
|
|
|
|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
|
|
|
|
}, |
|
|
|
|
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, |
|
|
|
|
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
|
|
|
|
CONFIG_SYS_PCIE2_PHYS_SIZE, |
|
|
|
|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
|
|
|
|
}, |
|
|
|
|
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, |
|
|
|
|
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, |
|
|
|
|
CONFIG_SYS_PCIE3_PHYS_SIZE, |
|
|
|
|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
|
|
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
|
|
|
|
}, |
|
|
|
|
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, |
|
|
|
|
CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, |
|
|
|
|
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, |
|
|
|
|
CONFIG_SYS_FSL_DRAM_SIZE3, |
|
|
|
|
PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
|
|
|
|
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS |
|
|
|
|
}, |
|
|
|
|
#endif |
|
|
|
|
}; |
|
|
|
|
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
|
|
|
|
{}, /* space holder for secure mem */ |
|
|
|
|
#endif |
|
|
|
|
{}, |
|
|
|
|
}; |
|
|
|
|
#endif /* !CONFIG_SYS_DCACHE_OFF */ |
|
|
|
|
|
|
|
|
|
int fsl_qoriq_core_to_cluster(unsigned int core); |
|
|
|
|
u32 cpu_mask(void); |
|
|
|
|