Tom Rini
10 years ago
commit
67ee22b068
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* Authors: Priyanka Jain <Priyanka.Jain@freescale.com> |
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* Wang Dongsheng <dongsheng.wang@freescale.com> |
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* |
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* This file is copied and modified from the original t1040qds/diu.c. |
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* Encoder can be used in T104x and LSx Platform. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <stdio_dev.h> |
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#include <i2c.h> |
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#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F |
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#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 |
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#define I2C_DVI_PLL_DIVIDER_REG 0x34 |
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#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 |
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#define I2C_DVI_PLL_FILTER_REG 0x36 |
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#define I2C_DVI_TEST_PATTERN_REG 0x48 |
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#define I2C_DVI_POWER_MGMT_REG 0x49 |
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#define I2C_DVI_LOCK_STATE_REG 0x4D |
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#define I2C_DVI_SYNC_POLARITY_REG 0x56 |
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/*
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* Set VSYNC/HSYNC to active high. This is polarity of sync signals |
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* from DIU->DVI. The DIU default is active igh, so DVI is set to |
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* active high. |
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*/ |
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#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 |
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#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 |
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#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 |
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#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 |
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#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 |
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#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 |
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#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 |
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/* Clear test pattern */ |
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#define I2C_DVI_TEST_PATTERN_VAL 0x18 |
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/* Exit Power-down mode */ |
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#define I2C_DVI_POWER_MGMT_VAL 0xC0 |
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/* Monitor polarity is handled via DVI Sync Polarity Register */ |
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#define I2C_DVI_SYNC_POLARITY_VAL 0x00 |
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/* Programming of HDMI Chrontel CH7301 connector */ |
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int diu_set_dvi_encoder(unsigned int pixclock) |
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{ |
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int ret; |
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u8 temp; |
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temp = I2C_DVI_TEST_PATTERN_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, |
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&temp, 1); |
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if (ret) { |
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puts("I2C: failed to select proper dvi test pattern\n"); |
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return ret; |
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} |
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temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, |
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1, &temp, 1); |
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if (ret) { |
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puts("I2C: failed to select dvi input data format\n"); |
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return ret; |
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} |
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/* Set Sync polarity register */ |
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temp = I2C_DVI_SYNC_POLARITY_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, |
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&temp, 1); |
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if (ret) { |
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puts("I2C: failed to select dvi syc polarity\n"); |
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return ret; |
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} |
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/* Set PLL registers based on pixel clock rate*/ |
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if (pixclock > 65000000) { |
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temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
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I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); |
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if (ret) { |
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puts("I2C: failed to select dvi pll charge_cntl\n"); |
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return ret; |
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} |
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temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
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I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); |
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if (ret) { |
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puts("I2C: failed to select dvi pll divider\n"); |
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return ret; |
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} |
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temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
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I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); |
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if (ret) { |
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puts("I2C: failed to select dvi pll filter\n"); |
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return ret; |
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} |
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} else { |
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temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
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I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); |
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if (ret) { |
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puts("I2C: failed to select dvi pll charge_cntl\n"); |
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return ret; |
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} |
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temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
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I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); |
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if (ret) { |
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puts("I2C: failed to select dvi pll divider\n"); |
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return ret; |
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} |
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temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
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I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); |
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if (ret) { |
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puts("I2C: failed to select dvi pll filter\n"); |
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return ret; |
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} |
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} |
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temp = I2C_DVI_POWER_MGMT_VAL; |
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, |
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&temp, 1); |
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if (ret) { |
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puts("I2C: failed to select dvi power mgmt\n"); |
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return ret; |
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} |
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udelay(500); |
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return 0; |
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} |
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@ -0,0 +1,13 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __DIU_HDMI_CH7301__ |
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#define __DIU_HDMI_CH7301__ |
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/* Programming of HDMI Chrontel CH7301 connector */ |
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int diu_set_dvi_encoder(unsigned int pixclock); |
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#endif |
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@ -0,0 +1,84 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* Author: Priyanka Jain <Priyanka.Jain@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/io.h> |
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#include <common.h> |
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#include <command.h> |
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#include <fsl_diu_fb.h> |
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#include <linux/ctype.h> |
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#include <video_fb.h> |
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#include "../common/diu_ch7301.h" |
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#include "cpld.h" |
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#include "t104xrdb.h" |
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/*
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* DIU Area Descriptor |
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* |
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* Note that we need to byte-swap the value before it's written to the AD |
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* register. So even though the registers don't look like they're in the same |
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* bit positions as they are on the MPC8610, the same value is written to the |
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* AD register on the MPC8610 and on the P1022. |
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*/ |
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#define AD_BYTE_F 0x10000000 |
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#define AD_ALPHA_C_SHIFT 25 |
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#define AD_BLUE_C_SHIFT 23 |
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#define AD_GREEN_C_SHIFT 21 |
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#define AD_RED_C_SHIFT 19 |
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#define AD_PIXEL_S_SHIFT 16 |
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#define AD_COMP_3_SHIFT 12 |
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#define AD_COMP_2_SHIFT 8 |
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#define AD_COMP_1_SHIFT 4 |
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#define AD_COMP_0_SHIFT 0 |
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void diu_set_pixel_clock(unsigned int pixclock) |
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{ |
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unsigned long speed_ccb, temp; |
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u32 pixval; |
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int ret; |
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speed_ccb = get_bus_freq(0); |
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temp = 1000000000 / pixclock; |
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temp *= 1000; |
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pixval = speed_ccb / temp; |
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/* Program HDMI encoder */ |
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ret = diu_set_dvi_encoder(temp); |
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if (ret) { |
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puts("Failed to set DVI encoder\n"); |
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return; |
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} |
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/* Program pixel clock */ |
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out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, |
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((pixval << PXCK_BITS_START) & PXCK_MASK)); |
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/* enable clock*/ |
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out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | |
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((pixval << PXCK_BITS_START) & PXCK_MASK)); |
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} |
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int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) |
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{ |
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u32 pixel_format; |
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u8 sw; |
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/*Configure Display ouput port as HDMI*/ |
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sw = CPLD_READ(sfp_ctl_status); |
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CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP)); |
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pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | |
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(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | |
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(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | |
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(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | |
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(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); |
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printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres); |
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return fsl_diu_init(xres, yres, pixel_format, 0); |
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} |
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