Introduce a generic common Ethernet Hardware init function common to all Amlogic GX SoCs with support for the Internal PHY enable for GXL SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>master
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/*
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* Copyright (C) 2016 BayLibre, SAS |
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* Author: Neil Armstrong <narmstrong@baylibre.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __MESON_ETH_H__ |
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#define __MESON_ETH_H__ |
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#include <phy.h> |
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enum { |
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/* Use GXL Internal RMII PHY */ |
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MESON_GXL_USE_INTERNAL_RMII_PHY = 1, |
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}; |
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/* Configure the Ethernet MAC with the requested interface mode
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* with some optional flags. |
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*/ |
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void meson_gx_eth_init(phy_interface_t mode, unsigned int flags); |
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#endif /* __MESON_ETH_H__ */ |
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/*
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* Copyright (C) 2016 BayLibre, SAS |
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* Author: Neil Armstrong <narmstrong@baylibre.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <asm/io.h> |
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#include <asm/arch/gxbb.h> |
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#include <asm/arch/eth.h> |
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#include <phy.h> |
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/* Configure the Ethernet MAC with the requested interface mode
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* with some optional flags. |
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*/ |
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void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) |
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{ |
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switch (mode) { |
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case PHY_INTERFACE_MODE_RGMII: |
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case PHY_INTERFACE_MODE_RGMII_ID: |
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case PHY_INTERFACE_MODE_RGMII_RXID: |
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case PHY_INTERFACE_MODE_RGMII_TXID: |
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/* Set RGMII mode */ |
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setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | |
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GXBB_ETH_REG_0_TX_PHASE(1) | |
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GXBB_ETH_REG_0_TX_RATIO(4) | |
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GXBB_ETH_REG_0_PHY_CLK_EN | |
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GXBB_ETH_REG_0_CLK_EN); |
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break; |
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case PHY_INTERFACE_MODE_RMII: |
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/* Set RMII mode */ |
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out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK | |
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GXBB_ETH_REG_0_CLK_EN); |
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/* Use GXL RMII Internal PHY */ |
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if (IS_ENABLED(CONFIG_MESON_GXL) && |
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(flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) { |
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writel(GXBB_ETH_REG_2, 0x10110181); |
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writel(GXBB_ETH_REG_3, 0xe40908ff); |
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} |
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break; |
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default: |
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printf("Invalid Ethernet interface mode\n"); |
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return; |
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} |
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/* Enable power and clock gate */ |
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setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); |
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clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); |
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} |
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