commit
694976afa5
@ -0,0 +1,56 @@ |
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#
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# Copyright 2004 Freescale Semiconductor.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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ifneq ($(OBJTREE),$(SRCTREE)) |
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$(shell mkdir -p $(obj)../common) |
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endif |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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SOBJS := init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(OBJS) $(SOBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,420 @@ |
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/*
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* Copyright 2007 |
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* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com |
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* |
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* Copyright 2007 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <pci.h> |
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#include <asm/processor.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/immap_fsl_pci.h> |
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#include <asm/io.h> |
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#include <spd.h> |
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#include <miiphy.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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extern void ddr_enable_ecc(unsigned int dram_size); |
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#endif |
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extern long int spd_sdram(void); |
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long int fixed_sdram(void); |
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int board_early_init_f (void) |
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{ |
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return 0; |
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} |
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int checkboard (void) |
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{ |
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
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volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
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volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); |
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if ((uint)&gur->porpllsr != 0xe00e0000) { |
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printf("immap size error %x\n",&gur->porpllsr); |
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} |
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printf ("Board: ATUM8548\n"); |
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lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ |
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lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ |
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ecm->eedr = 0xffffffff; /* Clear ecm errors */ |
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ecm->eeer = 0xffffffff; /* Enable ecm errors */ |
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return 0; |
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} |
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#if !defined(CONFIG_SPD_EEPROM) |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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long int fixed_sdram (void) |
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{ |
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volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); |
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ddr->cs0_bnds = CFG_DDR_CS0_BNDS; |
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ddr->cs0_config = CFG_DDR_CS0_CONFIG; |
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ddr->timing_cfg_0 = CFG_DDR_TIMING_0; |
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ddr->timing_cfg_1 = CFG_DDR_TIMING_1; |
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ddr->timing_cfg_2 = CFG_DDR_TIMING_2; |
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ddr->sdram_mode = CFG_DDR_MODE; |
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ddr->sdram_interval = CFG_DDR_INTERVAL; |
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#if defined (CONFIG_DDR_ECC) |
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ddr->err_disable = 0x0000000D; |
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ddr->err_sbe = 0x00ff0000; |
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#endif |
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asm("sync;isync;msync"); |
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udelay(500); |
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#if defined (CONFIG_DDR_ECC) |
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/* Enable ECC checking */ |
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ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); |
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#else |
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ddr->sdram_cfg = CFG_DDR_CONTROL; |
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#endif |
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asm("sync; isync; msync"); |
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udelay(500); |
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return CFG_SDRAM_SIZE * 1024 * 1024; |
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} |
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#endif /* !defined(CONFIG_SPD_EEPROM) */ |
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long int |
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initdram(int board_type) |
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{ |
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long dram_size = 0; |
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puts("Initializing\n"); |
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#if defined(CONFIG_SPD_EEPROM) |
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puts("spd_sdram\n"); |
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dram_size = spd_sdram (); |
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#else |
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puts("fixed_sdram\n"); |
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dram_size = fixed_sdram (); |
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#endif |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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/*
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* Initialize and enable DDR ECC. |
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*/ |
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ddr_enable_ecc(dram_size); |
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#endif |
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puts(" DDR: "); |
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return dram_size; |
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} |
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#if defined(CFG_DRAM_TEST) |
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int |
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testdram(void) |
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{ |
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uint *pstart = (uint *) CFG_MEMTEST_START; |
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uint *pend = (uint *) CFG_MEMTEST_END; |
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uint *p; |
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printf("Testing DRAM from 0x%08x to 0x%08x\n", |
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CFG_MEMTEST_START, |
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CFG_MEMTEST_END); |
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printf("DRAM test phase 1:\n"); |
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for (p = pstart; p < pend; p++) { |
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printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p); |
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*p = 0xaaaaaaaa; |
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} |
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for (p = pstart; p < pend; p++) { |
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if (*p != 0xaaaaaaaa) { |
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printf ("DRAM test fails at: %08x\n", (uint) p); |
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return 1; |
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} |
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} |
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printf("DRAM test phase 2:\n"); |
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for (p = pstart; p < pend; p++) |
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*p = 0x55555555; |
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for (p = pstart; p < pend; p++) { |
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if (*p != 0x55555555) { |
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printf ("DRAM test fails at: %08x\n", (uint) p); |
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return 1; |
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} |
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} |
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printf("DRAM test passed.\n"); |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_PCI1 |
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static struct pci_controller pci1_hose; |
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#endif |
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#ifdef CONFIG_PCI2 |
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static struct pci_controller pci2_hose; |
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#endif |
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#ifdef CONFIG_PCIE1 |
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static struct pci_controller pcie1_hose; |
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#endif |
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int first_free_busno=0; |
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void |
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pci_init_board(void) |
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{ |
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
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uint devdisr = gur->devdisr; |
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; |
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; |
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debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", |
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devdisr, io_sel, host_agent); |
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/* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */ |
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gur->clkocr |= MPC85xx_ATUM_CLKOCR; |
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if (io_sel & 1) { |
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) |
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printf (" eTSEC1 is in sgmii mode.\n"); |
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) |
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printf (" eTSEC2 is in sgmii mode.\n"); |
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) |
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printf (" eTSEC3 is in sgmii mode.\n"); |
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) |
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printf (" eTSEC4 is in sgmii mode.\n"); |
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} |
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#ifdef CONFIG_PCIE1 |
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{ |
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; |
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extern void fsl_pci_init(struct pci_controller *hose); |
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struct pci_controller *hose = &pcie1_hose; |
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int pcie_ep = (host_agent == 5); |
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int pcie_configured = io_sel & 6; |
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ |
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printf ("\n PCIE1 connected to slot as %s (base address %x)", |
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pcie_ep ? "End Point" : "Root Complex", |
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(uint)pci); |
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if (pci->pme_msg_det) { |
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pci->pme_msg_det = 0xffffffff; |
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); |
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} |
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printf ("\n"); |
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/* inbound */ |
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pci_set_region(hose->regions + 0, |
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CFG_PCI_MEMORY_BUS, |
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CFG_PCI_MEMORY_PHYS, |
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CFG_PCI_MEMORY_SIZE, |
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PCI_REGION_MEM | PCI_REGION_MEMORY); |
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|
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/* outbound memory */ |
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pci_set_region(hose->regions + 1, |
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CFG_PCIE1_MEM_BASE, |
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CFG_PCIE1_MEM_PHYS, |
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CFG_PCIE1_MEM_SIZE, |
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PCI_REGION_MEM); |
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/* outbound io */ |
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pci_set_region(hose->regions + 2, |
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CFG_PCIE1_IO_BASE, |
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CFG_PCIE1_IO_PHYS, |
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CFG_PCIE1_IO_SIZE, |
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PCI_REGION_IO); |
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hose->region_count = 3; |
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#ifdef CFG_PCIE1_MEM_BASE2 |
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/* outbound memory */ |
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pci_set_region(hose->regions + 3, |
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CFG_PCIE1_MEM_BASE2, |
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CFG_PCIE1_MEM_PHYS2, |
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CFG_PCIE1_MEM_SIZE2, |
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PCI_REGION_MEM); |
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hose->region_count++; |
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#endif |
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hose->first_busno=first_free_busno; |
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
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fsl_pci_init(hose); |
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first_free_busno=hose->last_busno+1; |
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printf(" PCIE1 on bus %02x - %02x\n", |
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hose->first_busno,hose->last_busno); |
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} else { |
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printf (" PCIE1: disabled\n"); |
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} |
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|
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} |
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#else |
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ |
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#endif |
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|
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#ifdef CONFIG_PCI1 |
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{ |
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; |
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extern void fsl_pci_init(struct pci_controller *hose); |
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struct pci_controller *hose = &pci1_hose; |
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|
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uint pci_agent = (host_agent == 6); |
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uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ |
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uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ |
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ |
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uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ |
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|
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { |
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printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n", |
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(pci_32) ? 32 : 64, |
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(pci_speed == 33333000) ? "33" : |
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(pci_speed == 66666000) ? "66" : "unknown", |
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pci_clk_sel ? "sync" : "async", |
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pci_agent ? "agent" : "host", |
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pci_arb ? "arbiter" : "external-arbiter", |
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(uint)pci |
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); |
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|
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/* inbound */ |
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pci_set_region(hose->regions + 0, |
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CFG_PCI_MEMORY_BUS, |
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CFG_PCI_MEMORY_PHYS, |
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CFG_PCI_MEMORY_SIZE, |
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PCI_REGION_MEM | PCI_REGION_MEMORY); |
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|
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/* outbound memory */ |
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pci_set_region(hose->regions + 1, |
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CFG_PCI1_MEM_BASE, |
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CFG_PCI1_MEM_PHYS, |
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CFG_PCI1_MEM_SIZE, |
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PCI_REGION_MEM); |
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|
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/* outbound io */ |
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pci_set_region(hose->regions + 2, |
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CFG_PCI1_IO_BASE, |
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CFG_PCI1_IO_PHYS, |
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CFG_PCI1_IO_SIZE, |
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PCI_REGION_IO); |
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hose->region_count = 3; |
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hose->first_busno=first_free_busno; |
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
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|
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fsl_pci_init(hose); |
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first_free_busno=hose->last_busno+1; |
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printf ("PCI1 on bus %02x - %02x\n", |
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hose->first_busno,hose->last_busno); |
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} else { |
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printf (" PCI1: disabled\n"); |
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} |
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} |
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#else |
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ |
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#endif |
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|
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#ifdef CONFIG_PCI2 |
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{ |
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; |
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extern void fsl_pci_init(struct pci_controller *hose); |
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struct pci_controller *hose = &pci2_hose; |
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|
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if (!(devdisr & MPC85xx_DEVDISR_PCI2)) { |
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pci_set_region(hose->regions + 0, |
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CFG_PCI_MEMORY_BUS, |
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CFG_PCI_MEMORY_PHYS, |
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CFG_PCI_MEMORY_SIZE, |
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PCI_REGION_MEM | PCI_REGION_MEMORY); |
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|
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pci_set_region(hose->regions + 1, |
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CFG_PCI2_MEM_BASE, |
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CFG_PCI2_MEM_PHYS, |
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CFG_PCI2_MEM_SIZE, |
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PCI_REGION_MEM); |
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|
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pci_set_region(hose->regions + 2, |
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CFG_PCI2_IO_BASE, |
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CFG_PCI2_IO_PHYS, |
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CFG_PCI2_IO_SIZE, |
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PCI_REGION_IO); |
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hose->region_count = 3; |
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hose->first_busno=first_free_busno; |
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
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|
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fsl_pci_init(hose); |
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first_free_busno=hose->last_busno+1; |
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printf ("PCI2 on bus %02x - %02x\n", |
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hose->first_busno,hose->last_busno); |
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} else { |
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printf (" PCI2: disabled\n"); |
||||
} |
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} |
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#else |
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gur->devdisr |= MPC85xx_DEVDISR_PCI2; |
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#endif |
||||
} |
||||
|
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|
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int last_stage_init(void) |
||||
{ |
||||
int ic = icache_status (); |
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printf ("icache_status: %d\n", ic); |
||||
return 0; |
||||
} |
||||
|
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#if defined(CONFIG_OF_BOARD_SETUP) |
||||
|
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void |
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ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
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int node, tmp[2]; |
||||
const char *path; |
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|
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ft_cpu_setup(blob, bd); |
||||
|
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node = fdt_path_offset(blob, "/aliases"); |
||||
tmp[0] = 0; |
||||
if (node >= 0) { |
||||
#ifdef CONFIG_PCI1 |
||||
path = fdt_getprop(blob, node, "pci0", NULL); |
||||
if (path) { |
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; |
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do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
||||
} |
||||
#endif |
||||
#ifdef CONFIG_PCI2 |
||||
path = fdt_getprop(blob, node, "pci1", NULL); |
||||
if (path) { |
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tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno; |
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
||||
} |
||||
#endif |
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#ifdef CONFIG_PCIE1 |
||||
path = fdt_getprop(blob, node, "pci2", NULL); |
||||
if (path) { |
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; |
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
||||
} |
||||
#endif |
||||
} |
||||
} |
||||
#endif |
@ -0,0 +1,33 @@ |
||||
#
|
||||
# Copyright 2004, 2007 Freescale Semiconductor.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# atum8548 board
|
||||
# TEXT_BASE = 0xfff80000
|
||||
# TEXT_BASE = 0xfffff000
|
||||
ifndef TEXT_BASE |
||||
TEXT_BASE = 0xfff80000
|
||||
endif |
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
|
@ -0,0 +1,235 @@ |
||||
/* |
||||
* Copyright 2007 |
||||
* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
|
||||
* Copyright 2004, 2007 Freescale Semiconductor. |
||||
* Copyright 2002,2003, Motorola Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
#define LAWAR_TRGT_PCI1 0x00000000 |
||||
#define LAWAR_TRGT_PCI2 0x00100000 |
||||
#define LAWAR_TRGT_PCIE 0x00200000 |
||||
#define LAWAR_TRGT_DDR 0x00f00000 |
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long (2f-1f)/16 |
||||
|
||||
1: |
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, guarded |
||||
* Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, MAS2_G) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, MAS2_G) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, MAS2_G) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, MAS2_G) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* TLB 1 Initializations */ |
||||
/* |
||||
* TLB 0, 1: 128M Non-cacheable, guarded |
||||
* 0xf8000000 128M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x4000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x4000000, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 1G Non-cacheable, guarded |
||||
* 0x80000000 1G PCI1/PCIE 8,9,a,b |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3, 4: 512M Non-cacheable, guarded |
||||
* 0xc0000000 1G PCI2 |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 1M PCI1 IO |
||||
* 0xe210_0000 1M PCI2 IO |
||||
* 0xe300_0000 1M PCIe IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
2: |
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCIe MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff PCI2 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe10f_ffff PCI1 IO 1M |
||||
* 0xe280_0000 0xe20f_ffff PCI2 IO 1M |
||||
* 0xe300_0000 0xe30f_ffff PCIe IO 1M |
||||
* 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
* LAW 0 is reserved for boot mapping |
||||
*/ |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
|
||||
.long (4f-3f)/8 |
||||
3: |
||||
.long 0
|
||||
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN |
||||
|
||||
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) |
||||
|
||||
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) |
||||
|
||||
.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) |
||||
|
||||
.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) |
||||
|
||||
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M) |
||||
|
||||
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) |
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) |
||||
|
||||
4: |
||||
entry_end |
@ -0,0 +1,147 @@ |
||||
/* |
||||
* Copyright 2007 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/mpc85xx/start.o (.bootpg) |
||||
board/atum8548/init.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc85xx/start.o (.text) |
||||
board/atum8548/init.o (.text) |
||||
cpu/mpc85xx/traps.o (.text) |
||||
cpu/mpc85xx/interrupts.o (.text) |
||||
cpu/mpc85xx/cpu_init.o (.text) |
||||
cpu/mpc85xx/cpu.o (.text) |
||||
cpu/mpc85xx/speed.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,55 @@ |
||||
#
|
||||
# (C) Copyright 2004-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
|
||||
# Added support for Wind River SBC8560 board
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o
|
||||
SOBJS := init.o
|
||||
#SOBJS :=
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(OBJS) $(SOBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,32 @@ |
||||
#
|
||||
# Copyright 2004, 2007 Freescale Semiconductor.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# sbc8548 board
|
||||
#
|
||||
ifndef TEXT_BASE |
||||
TEXT_BASE = 0xfff80000
|
||||
endif |
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
|
@ -0,0 +1,241 @@ |
||||
/* |
||||
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> |
||||
* Copyright 2007 Embedded Specialties, Inc. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright 2002,2003, Motorola Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xe4010000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff800000 16M TLB for 8MB FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Cacheable, non-guarded |
||||
* 0x0 256M DDR SDRAM |
||||
*/ |
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
/* |
||||
* TLB 4: 64M Non-cacheable, guarded |
||||
* 0xe0000000 1M CCSRBAR |
||||
* 0xe2000000 16M PCI1 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Cacheable, non-guarded |
||||
* 0xf0000000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 16M Cacheable, non-guarded |
||||
* 0xf8000000 1M 7-segment LED display |
||||
* 0xf8100000 1M User switches |
||||
* 0xf8300000 1M Board revision |
||||
* 0xf8b00000 1M EEPROM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_EPLD_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x0fff_ffff DDR 256M |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf8b0_0000 0xf80f_ffff EEPROM 1M |
||||
* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M |
||||
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
* The defines below are 1-off of the actual LAWAR0 usage. |
||||
* So LAWAR3 define uses the LAWAR4 register in the ECM. |
||||
*/ |
||||
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
|
||||
law_entry: |
||||
entry_start |
||||
.long 4
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
entry_end |
@ -0,0 +1,569 @@ |
||||
/*
|
||||
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> |
||||
* Copyright 2007 Embedded Specialties, Inc. |
||||
* |
||||
* Copyright 2004, 2007 Freescale Semiconductor. |
||||
* |
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/immap_fsl_pci.h> |
||||
#include <spd.h> |
||||
#include <miiphy.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
extern void ddr_enable_ecc(unsigned int dram_size); |
||||
#endif |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
extern long int spd_sdram(void); |
||||
|
||||
void local_bus_init(void); |
||||
void sdram_init(void); |
||||
long int fixed_sdram (void); |
||||
|
||||
int board_early_init_f (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); |
||||
|
||||
printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", |
||||
(volatile)(*(u_char *)CFG_BD_REV) >> 4); |
||||
|
||||
/*
|
||||
* Initialize local bus. |
||||
*/ |
||||
local_bus_init (); |
||||
|
||||
/*
|
||||
* Fix CPU2 errata: A core hang possible while executing a |
||||
* msync instruction and a snoopable transaction from an I/O |
||||
* master tagged to make quick forward progress is present. |
||||
*/ |
||||
ecm->eebpcr |= (1 << 16); |
||||
|
||||
/*
|
||||
* Hack TSEC 3 and 4 IO voltages. |
||||
*/ |
||||
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ |
||||
|
||||
ecm->eedr = 0xffffffff; /* clear ecm errors */ |
||||
ecm->eeer = 0xffffffff; /* enable ecm errors */ |
||||
return 0; |
||||
} |
||||
|
||||
long int |
||||
initdram(int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
|
||||
puts("Initializing\n"); |
||||
|
||||
#if defined(CONFIG_DDR_DLL) |
||||
{ |
||||
/*
|
||||
* Work around to stabilize DDR DLL MSYNC_IN. |
||||
* Errata DDR9 seems to have been fixed. |
||||
* This is now the workaround for Errata DDR11: |
||||
* Override DLL = 1, Course Adj = 1, Tap Select = 0 |
||||
*/ |
||||
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
|
||||
gur->ddrdllcr = 0x81000000; |
||||
asm("sync;isync;msync"); |
||||
udelay(200); |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
dram_size = spd_sdram (); |
||||
#else |
||||
dram_size = fixed_sdram (); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
/*
|
||||
* Initialize and enable DDR ECC. |
||||
*/ |
||||
ddr_enable_ecc(dram_size); |
||||
#endif |
||||
/*
|
||||
* SDRAM Initialization |
||||
*/ |
||||
sdram_init(); |
||||
|
||||
puts(" DDR: "); |
||||
return dram_size; |
||||
} |
||||
|
||||
/*
|
||||
* Initialize Local Bus |
||||
*/ |
||||
void |
||||
local_bus_init(void) |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
|
||||
uint clkdiv; |
||||
uint lbc_hz; |
||||
sys_info_t sysinfo; |
||||
|
||||
get_sys_info(&sysinfo); |
||||
clkdiv = (lbc->lcrr & 0x0f) * 2; |
||||
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
||||
|
||||
gur->lbiuiplldcr1 = 0x00078080; |
||||
if (clkdiv == 16) { |
||||
gur->lbiuiplldcr0 = 0x7c0f1bf0; |
||||
} else if (clkdiv == 8) { |
||||
gur->lbiuiplldcr0 = 0x6c0f1bf0; |
||||
} else if (clkdiv == 4) { |
||||
gur->lbiuiplldcr0 = 0x5c0f1bf0; |
||||
} |
||||
|
||||
lbc->lcrr |= 0x00030000; |
||||
|
||||
asm("sync;isync;msync"); |
||||
|
||||
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ |
||||
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ |
||||
} |
||||
|
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus. |
||||
*/ |
||||
void |
||||
sdram_init(void) |
||||
{ |
||||
#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) |
||||
|
||||
uint idx; |
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; |
||||
uint lsdmr_common; |
||||
|
||||
puts(" SDRAM: "); |
||||
|
||||
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
||||
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers |
||||
*/ |
||||
lbc->or3 = CFG_OR3_PRELIM; |
||||
asm("msync"); |
||||
|
||||
lbc->br3 = CFG_BR3_PRELIM; |
||||
asm("msync"); |
||||
|
||||
lbc->lbcr = CFG_LBC_LBCR; |
||||
asm("msync"); |
||||
|
||||
|
||||
lbc->lsrt = CFG_LBC_LSRT; |
||||
lbc->mrtpr = CFG_LBC_MRTPR; |
||||
asm("msync"); |
||||
|
||||
/*
|
||||
* MPC8548 uses "new" 15-16 style addressing. |
||||
*/ |
||||
lsdmr_common = CFG_LBC_LSDMR_COMMON; |
||||
lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; |
||||
|
||||
/*
|
||||
* Issue PRECHARGE ALL command. |
||||
*/ |
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; |
||||
asm("sync;msync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
|
||||
/*
|
||||
* Issue 8 AUTO REFRESH commands. |
||||
*/ |
||||
for (idx = 0; idx < 8; idx++) { |
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; |
||||
asm("sync;msync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
} |
||||
|
||||
/*
|
||||
* Issue 8 MODE-set command. |
||||
*/ |
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; |
||||
asm("sync;msync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
|
||||
/*
|
||||
* Issue NORMAL OP command. |
||||
*/ |
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; |
||||
asm("sync;msync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(200); /* Overkill. Must wait > 200 bus cycles */ |
||||
|
||||
#endif /* enable SDRAM init */ |
||||
} |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int |
||||
testdram(void) |
||||
{ |
||||
uint *pstart = (uint *) CFG_MEMTEST_START; |
||||
uint *pend = (uint *) CFG_MEMTEST_END; |
||||
uint *p; |
||||
|
||||
printf("Testing DRAM from 0x%08x to 0x%08x\n", |
||||
CFG_MEMTEST_START, |
||||
CFG_MEMTEST_END); |
||||
|
||||
printf("DRAM test phase 1:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("DRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("DRAM test phase 2:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("DRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("DRAM test passed.\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed_sdram init -- doesn't use serial presence detect. |
||||
* assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. |
||||
************************************************************************/ |
||||
long int fixed_sdram (void) |
||||
{ |
||||
#define CFG_DDR_CONTROL 0xc300c000 |
||||
|
||||
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); |
||||
|
||||
ddr->cs0_bnds = 0x0000007f; |
||||
ddr->cs1_bnds = 0x008000ff; |
||||
ddr->cs2_bnds = 0x00000000; |
||||
ddr->cs3_bnds = 0x00000000; |
||||
ddr->cs0_config = 0x80010101; |
||||
ddr->cs1_config = 0x80010101; |
||||
ddr->cs2_config = 0x00000000; |
||||
ddr->cs3_config = 0x00000000; |
||||
ddr->ext_refrec = 0x00000000; |
||||
ddr->timing_cfg_0 = 0x00220802; |
||||
ddr->timing_cfg_1 = 0x38377322; |
||||
ddr->timing_cfg_2 = 0x0fa044C7; |
||||
ddr->sdram_cfg = 0x4300C000; |
||||
ddr->sdram_cfg_2 = 0x24401000; |
||||
ddr->sdram_mode = 0x23C00542; |
||||
ddr->sdram_mode_2 = 0x00000000; |
||||
ddr->sdram_interval = 0x05080100; |
||||
ddr->sdram_md_cntl = 0x00000000; |
||||
ddr->sdram_data_init = 0x00000000; |
||||
ddr->sdram_clk_cntl = 0x03800000; |
||||
asm("sync;isync;msync"); |
||||
udelay(500); |
||||
|
||||
#if defined (CONFIG_DDR_ECC) |
||||
/* Enable ECC checking */ |
||||
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); |
||||
#else |
||||
ddr->sdram_cfg = CFG_DDR_CONTROL; |
||||
#endif |
||||
|
||||
return CFG_SDRAM_SIZE * 1024 * 1024; |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) |
||||
/* For some reason the Tundra PCI bridge shows up on itself as a
|
||||
* different device. Work around that by refusing to configure it. |
||||
*/ |
||||
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } |
||||
|
||||
static struct pci_config_table pci_sbc8548_config_table[] = { |
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, |
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, |
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, |
||||
mpc85xx_config_via_usbide, {0,0,0}}, |
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, |
||||
mpc85xx_config_via_usb, {0,0,0}}, |
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, |
||||
mpc85xx_config_via_usb2, {0,0,0}}, |
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, |
||||
mpc85xx_config_via_power, {0,0,0}}, |
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, |
||||
mpc85xx_config_via_ac97, {0,0,0}}, |
||||
{}, |
||||
}; |
||||
|
||||
static struct pci_controller pci1_hose = { |
||||
config_table: pci_sbc8548_config_table}; |
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
#ifdef CONFIG_PCI2 |
||||
static struct pci_controller pci2_hose; |
||||
#endif /* CONFIG_PCI2 */ |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
static struct pci_controller pcie1_hose; |
||||
#endif /* CONFIG_PCIE1 */ |
||||
|
||||
int first_free_busno=0; |
||||
|
||||
void |
||||
pci_init_board(void) |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
||||
|
||||
#ifdef CONFIG_PCI1 |
||||
{ |
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; |
||||
extern void fsl_pci_init(struct pci_controller *hose); |
||||
struct pci_controller *hose = &pci1_hose; |
||||
struct pci_config_table *table; |
||||
|
||||
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ |
||||
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ |
||||
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ |
||||
|
||||
uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); |
||||
|
||||
uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ |
||||
|
||||
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { |
||||
printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", |
||||
(pci_32) ? 32 : 64, |
||||
(pci_speed == 33333000) ? "33" : |
||||
(pci_speed == 66666000) ? "66" : "unknown", |
||||
pci_clk_sel ? "sync" : "async", |
||||
pci_agent ? "agent" : "host", |
||||
pci_arb ? "arbiter" : "external-arbiter" |
||||
); |
||||
|
||||
|
||||
/* inbound */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI_MEMORY_BUS, |
||||
CFG_PCI_MEMORY_PHYS, |
||||
CFG_PCI_MEMORY_SIZE, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
|
||||
/* outbound memory */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI1_MEM_BASE, |
||||
CFG_PCI1_MEM_PHYS, |
||||
CFG_PCI1_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* outbound io */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCI1_IO_BASE, |
||||
CFG_PCI1_IO_PHYS, |
||||
CFG_PCI1_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
hose->region_count = 3; |
||||
|
||||
/* relocate config table pointers */ |
||||
hose->config_table = \
|
||||
(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); |
||||
for (table = hose->config_table; table && table->vendor; table++) |
||||
table->config_device += gd->reloc_off; |
||||
|
||||
hose->first_busno=first_free_busno; |
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
||||
|
||||
fsl_pci_init(hose); |
||||
first_free_busno=hose->last_busno+1; |
||||
printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); |
||||
#ifdef CONFIG_PCIX_CHECK |
||||
if (!(gur->pordevsr & PORDEVSR_PCI)) { |
||||
/* PCI-X init */ |
||||
if (CONFIG_SYS_CLK_FREQ < 66000000) |
||||
printf("PCI-X will only work at 66 MHz\n"); |
||||
|
||||
reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
||||
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; |
||||
pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); |
||||
} |
||||
#endif |
||||
} else { |
||||
printf (" PCI: disabled\n"); |
||||
} |
||||
} |
||||
#else |
||||
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCI2 |
||||
{ |
||||
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ |
||||
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ |
||||
if (pci_dual) { |
||||
printf (" PCI2: 32 bit, 66 MHz, %s\n", |
||||
pci2_clk_sel ? "sync" : "async"); |
||||
} else { |
||||
printf (" PCI2: disabled\n"); |
||||
} |
||||
} |
||||
#else |
||||
gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ |
||||
#endif /* CONFIG_PCI2 */ |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
{ |
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; |
||||
extern void fsl_pci_init(struct pci_controller *hose); |
||||
struct pci_controller *hose = &pcie1_hose; |
||||
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); |
||||
|
||||
int pcie_configured = io_sel >= 1; |
||||
|
||||
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ |
||||
printf ("\n PCIE connected to slot as %s (base address %x)", |
||||
pcie_ep ? "End Point" : "Root Complex", |
||||
(uint)pci); |
||||
|
||||
if (pci->pme_msg_det) { |
||||
pci->pme_msg_det = 0xffffffff; |
||||
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); |
||||
} |
||||
printf ("\n"); |
||||
|
||||
/* inbound */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI_MEMORY_BUS, |
||||
CFG_PCI_MEMORY_PHYS, |
||||
CFG_PCI_MEMORY_SIZE, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
/* outbound memory */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCIE1_MEM_BASE, |
||||
CFG_PCIE1_MEM_PHYS, |
||||
CFG_PCIE1_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* outbound io */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCIE1_IO_BASE, |
||||
CFG_PCIE1_IO_PHYS, |
||||
CFG_PCIE1_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = 3; |
||||
|
||||
hose->first_busno=first_free_busno; |
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
||||
|
||||
fsl_pci_init(hose); |
||||
printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); |
||||
|
||||
first_free_busno=hose->last_busno+1; |
||||
|
||||
} else { |
||||
printf (" PCIE: disabled\n"); |
||||
} |
||||
} |
||||
#else |
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ |
||||
#endif |
||||
|
||||
} |
||||
|
||||
int last_stage_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) |
||||
void |
||||
ft_pci_setup(void *blob, bd_t *bd) |
||||
{ |
||||
int node, tmp[2]; |
||||
const char *path; |
||||
|
||||
node = fdt_path_offset(blob, "/aliases"); |
||||
tmp[0] = 0; |
||||
if (node >= 0) { |
||||
#ifdef CONFIG_PCI1 |
||||
path = fdt_getprop(blob, node, "pci0", NULL); |
||||
if (path) { |
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; |
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
||||
} |
||||
#endif |
||||
#ifdef CONFIG_PCIE1 |
||||
path = fdt_getprop(blob, node, "pci1", NULL); |
||||
if (path) { |
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; |
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
||||
} |
||||
#endif |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) |
||||
void |
||||
ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
ft_cpu_setup(blob, bd); |
||||
#ifdef CONFIG_PCI |
||||
ft_pci_setup(blob, bd); |
||||
#endif |
||||
} |
||||
#endif |
||||
|
@ -0,0 +1,149 @@ |
||||
/* |
||||
* Copyright 2004, 2007 Freescale Semiconductor. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/mpc85xx/start.o (.bootpg) |
||||
board/sbc8548/init.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc85xx/start.o (.text) |
||||
board/sbc8548/init.o (.text) |
||||
cpu/mpc85xx/traps.o (.text) |
||||
cpu/mpc85xx/interrupts.o (.text) |
||||
cpu/mpc85xx/cpu_init.o (.text) |
||||
cpu/mpc85xx/cpu.o (.text) |
||||
drivers/net/tsec.o (.text) |
||||
cpu/mpc85xx/speed.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,29 @@ |
||||
Building U-Boot |
||||
--------------- |
||||
|
||||
The ATUM8548 code is known to build using ELDK 4.1. |
||||
|
||||
$ make ATUM8548_config |
||||
Configuring for ATUM8548 board... |
||||
$ make |
||||
|
||||
Using Flash |
||||
----------- |
||||
|
||||
The ATUM8548 board has one flash bank, of 128MB in size (2^23 = 0x08000000). |
||||
|
||||
The BDI2000 commands for copying u-boot into flash are |
||||
as follows: |
||||
|
||||
erase 0xFFF80000 0x4000 0x20 |
||||
prog 0xfff80000 uboot.bin bin |
||||
|
||||
Booting Linux |
||||
------------- |
||||
|
||||
U-boot/kermit commands for booting linux via NFS - assumming the proper |
||||
bootargs are set - are as follows: |
||||
|
||||
tftp 1000000 uImage.atum |
||||
tftp c00000 mpc8548atum.dtb |
||||
bootm 1000000 - c00000 |
@ -0,0 +1,27 @@ |
||||
Wind River SBC8548 reference board |
||||
=========================== |
||||
|
||||
Copyright 2007, Embedded Specialties, Inc. |
||||
Copyright 2007 Wind River Systemes, Inc. |
||||
----------------------------- |
||||
|
||||
1. Building U-Boot |
||||
------------------ |
||||
The SBC8548 code is known to build using ELDK 4.1. |
||||
|
||||
$ make sbc8548_config |
||||
Configuring for sbc8548 board... |
||||
|
||||
$ make |
||||
|
||||
|
||||
2. Switch and Jumper Settings |
||||
----------------------------- |
||||
All Jumpers & Switches are in their default positions. Please refer to |
||||
the board documentation for details. Some settings control CPU voltages |
||||
and settings may change with board revisions. |
||||
|
||||
3. Known limitations |
||||
-------------------- |
||||
PCI: |
||||
The code to support PCI is currently disabled and has not been verified. |
@ -0,0 +1,458 @@ |
||||
/*
|
||||
* Copyright 2007 |
||||
* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com |
||||
* |
||||
* Copyright 2004, 2007 Freescale Semiconductor. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* atum8548 board configuration file |
||||
* |
||||
* Please refer to doc/README.atum8548 for more info. |
||||
* |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* Debug Options, Disable in production
|
||||
#define ET_DEBUG 1 |
||||
#define CONFIG_PANIC_HANG 1 |
||||
#define DEBUG 1 |
||||
*/ |
||||
|
||||
/* CPLD Configuration Options */ |
||||
#define MPC85xx_ATUM_CLKOCR 0x80000002 |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
||||
#define CONFIG_MPC8548 1 /* MPC8548 specific */ |
||||
|
||||
#define CONFIG_PCI 1 /* enable any pci type devices */ |
||||
#define CONFIG_PCI1 1 /* PCI controller 1 */ |
||||
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
||||
#define CONFIG_PCI2 1 /* PCI controller 2 */ |
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
||||
|
||||
#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ |
||||
#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
||||
|
||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
||||
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
||||
|
||||
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
||||
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ |
||||
|
||||
/*
|
||||
* Only possible on E500 Version 2 or newer cores. |
||||
*/ |
||||
#define CONFIG_ENABLE_36BIT_PHYS 1 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
|
||||
#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */ |
||||
#define CONFIG_ENABLE_36BIT_PHYS 1 |
||||
#undef CFG_DRAM_TEST |
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00400000 |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
||||
|
||||
#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ |
||||
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) |
||||
#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) |
||||
#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* Determine DDR configuration from I2C interface. |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
||||
|
||||
#else |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
*/ |
||||
#define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */ |
||||
#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */ |
||||
#define CFG_DDR_CS0_CONFIG 0x80000102 |
||||
#define CFG_DDR_TIMING_0 0x00260802 |
||||
#define CFG_DDR_TIMING_1 0x38355322 |
||||
#define CFG_DDR_TIMING_2 0x039048c7 |
||||
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
||||
#define CFG_DDR_MODE 0x00000432 |
||||
#define CFG_DDR_INTERVAL 0x05150100 |
||||
#define DDR_SDRAM_CFG 0x43000000 |
||||
#endif |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
/*
|
||||
* Local Bus Definitions |
||||
*/ |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
* based on flash chip S29GL01GP |
||||
* One bank, 128M, using the CFI driver. |
||||
* Boot from BR0 bank at 0xf800_0000 |
||||
* |
||||
* BR0: |
||||
* Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0 |
||||
* Port Size = 16 bits = BRx[19:20] = 10 |
||||
* Use GPCM = BRx[24:26] = 000 |
||||
* Valid = BRx[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0 |
||||
* |
||||
* OR0: |
||||
* Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0 |
||||
* Reserved ORx[17:18] = 00 |
||||
* CSNT = ORx[20] = 1 |
||||
* ACS = half cycle delay = ORx[21:22] = 11 |
||||
* SCY = 6 = ORx[24:27] = 0110 |
||||
* TRLX = use relaxed timing = ORx[29] = 1 |
||||
* EAD = use external address latch delay = OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx |
||||
*/ |
||||
|
||||
#define CFG_BOOT_BLOCK 0xf8000000 /* boot TLB block */ |
||||
#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 128M */ |
||||
|
||||
#define CFG_BR0_PRELIM 0xf8001001 |
||||
|
||||
#define CFG_OR0_PRELIM 0xf8000E65 |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */ |
||||
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#define CFG_FLASH_CFI_DRIVER 1 |
||||
#define CFG_FLASH_CFI 1 |
||||
#define CFG_FLASH_EMPTY_INFO |
||||
|
||||
/*
|
||||
* Flash on the LocalBus |
||||
*/ |
||||
#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ |
||||
|
||||
/* Memory */ |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
||||
|
||||
#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x57 |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Memory space is mapped 1-1, but I/O space must start from 0. |
||||
*/ |
||||
#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
||||
|
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI1_IO_BASE 0x00000000 |
||||
#define CFG_PCI1_IO_PHYS 0xe2000000 |
||||
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ |
||||
|
||||
#ifdef CONFIG_PCI2 |
||||
#define CFG_PCI2_MEM_BASE 0xC0000000 |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI2_IO_BASE 0x00000000 |
||||
#define CFG_PCI2_IO_PHYS 0xe2800000 |
||||
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
#define CFG_PCIE1_MEM_BASE 0xa0000000 |
||||
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE |
||||
#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCIE1_IO_BASE 0x00000000 |
||||
#define CFG_PCIE1_IO_PHYS 0xe3000000 |
||||
#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
||||
#endif |
||||
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP) |
||||
#define PCI_ENET0_IOADDR 0xe0000000 |
||||
#define PCI_ENET0_MEMADDR 0xe0000000 |
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
||||
#endif |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
|
||||
/* PCI view of System Memory */ |
||||
#define CFG_PCI_MEMORY_BUS 0x00000000 |
||||
#define CFG_PCI_MEMORY_PHYS 0x00000000 |
||||
#define CFG_PCI_MEMORY_SIZE 0x80000000 |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_TSEC1 1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC0" |
||||
#define CONFIG_TSEC2 1 |
||||
#define CONFIG_TSEC2_NAME "eTSEC1" |
||||
#define CONFIG_TSEC3 1 |
||||
#define CONFIG_TSEC3_NAME "eTSEC2" |
||||
#define CONFIG_TSEC4 1 |
||||
#define CONFIG_TSEC4_NAME "eTSEC3" |
||||
#undef CONFIG_MPC85XX_FEC |
||||
|
||||
#define TSEC1_PHY_ADDR 0 |
||||
#define TSEC2_PHY_ADDR 1 |
||||
#define TSEC3_PHY_ADDR 2 |
||||
#define TSEC4_PHY_ADDR 3 |
||||
|
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define TSEC3_PHYIDX 0 |
||||
#define TSEC4_PHYIDX 0 |
||||
#define TSEC1_FLAGS TSEC_GIGABIT |
||||
#define TSEC2_FLAGS TSEC_GIGABIT |
||||
#define TSEC3_FLAGS TSEC_GIGABIT |
||||
#define TSEC4_FLAGS TSEC_GIGABIT |
||||
|
||||
/* Options are: eTSEC[0-3] */ |
||||
#define CONFIG_ETHPRIME "eTSEC2" |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_CMD_PCI |
||||
#endif |
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
/* The mac addresses for all ethernet interface */ |
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
||||
#define CONFIG_HAS_ETH2 |
||||
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
||||
#define CONFIG_HAS_ETH3 |
||||
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
||||
#endif |
||||
|
||||
#define CONFIG_IPADDR 10.101.43.142 |
||||
|
||||
#define CONFIG_HOSTNAME atum |
||||
#define CONFIG_ROOTPATH /nfsroot |
||||
#define CONFIG_BOOTFILE /tftpboot/uImage.atum |
||||
#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */ |
||||
|
||||
#define CONFIG_SERVERIP 10.101.43.10 |
||||
#define CONFIG_GATEWAYIP 10.101.45.1 |
||||
#define CONFIG_NETMASK 255.255.248.0 |
||||
|
||||
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $dtbaddr $dtbfile;" \
|
||||
"bootm $loadaddr - $dtbaddr" |
||||
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $dtbaddr $dtbfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $dtbaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,569 @@ |
||||
/*
|
||||
* Copyright 2007 Wind River Systems <www.windriver.com> |
||||
* Copyright 2007 Embedded Specialties, Inc. |
||||
* Copyright 2004, 2007 Freescale Semiconductor. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* sbc8548 board configuration file |
||||
* |
||||
* Please refer to doc/README.sbc85xx for more info. |
||||
* |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
||||
#define CONFIG_MPC8548 1 /* MPC8548 specific */ |
||||
#define CONFIG_SBC8548 1 /* SBC8548 board specific */ |
||||
|
||||
#undef CONFIG_PCI /* enable any pci type devices */ |
||||
#undef CONFIG_PCI1 /* PCI controller 1 */ |
||||
#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ |
||||
#undef CONFIG_RIO |
||||
#undef CONFIG_PCI2 |
||||
#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */ |
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
||||
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
||||
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
||||
|
||||
|
||||
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
||||
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ |
||||
|
||||
/*
|
||||
* Only possible on E500 Version 2 or newer cores. |
||||
*/ |
||||
#define CONFIG_ENABLE_36BIT_PHYS 1 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00400000 |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
||||
|
||||
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) |
||||
#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) |
||||
#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
||||
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
||||
|
||||
/*
|
||||
* Make sure required options are set |
||||
*/ |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ |
||||
#endif |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
* Two banks, one 8MB the other 64MB, using the CFI driver. |
||||
* Boot from BR0/OR0 bank at 0xff80_0000 |
||||
* Alternate BR6/OR6 bank at 0xfb80_0000 |
||||
* |
||||
* BR0: |
||||
* Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 |
||||
* Port Size = 8 bits = BRx[19:20] = 01 |
||||
* Use GPCM = BRx[24:26] = 000 |
||||
* Valid = BRx[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 |
||||
* |
||||
* BR6: |
||||
* Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 |
||||
* Port Size = 32 bits = BRx[19:20] = 11 |
||||
* Use GPCM = BRx[24:26] = 000 |
||||
* Valid = BRx[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 |
||||
* |
||||
* OR0: |
||||
* Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 |
||||
* XAM = OR0[17:18] = 11 |
||||
* CSNT = OR0[20] = 1 |
||||
* ACS = half cycle delay = OR0[21:22] = 11 |
||||
* SCY = 6 = OR0[24:27] = 0110 |
||||
* TRLX = use relaxed timing = OR0[29] = 1 |
||||
* EAD = use external address latch delay = OR0[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 |
||||
* |
||||
* OR6: |
||||
* Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 |
||||
* XAM = OR6[17:18] = 11 |
||||
* CSNT = OR6[20] = 1 |
||||
* ACS = half cycle delay = OR6[21:22] = 11 |
||||
* SCY = 6 = OR6[24:27] = 0110 |
||||
* TRLX = use relaxed timing = OR6[29] = 1 |
||||
* EAD = use external address latch delay = OR6[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6 |
||||
*/ |
||||
|
||||
#define CFG_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ |
||||
#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ |
||||
|
||||
#define CFG_BR0_PRELIM 0xff800801 |
||||
#define CFG_BR6_PRELIM 0xfb801801 |
||||
|
||||
#define CFG_OR0_PRELIM 0xff806e65 |
||||
#define CFG_OR6_PRELIM 0xfc006e65 |
||||
|
||||
#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} |
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_FLASH_EMPTY_INFO |
||||
|
||||
/* CS5 = Local bus peripherals controlled by the EPLD */ |
||||
|
||||
#define CFG_BR5_PRELIM 0xf8000801 |
||||
#define CFG_OR5_PRELIM 0xff006e65 |
||||
#define CFG_EPLD_BASE 0xf8000000 |
||||
#define CFG_LED_DISP_BASE 0xf8000000 |
||||
#define CFG_USER_SWITCHES_BASE 0xf8100000 |
||||
#define CFG_BD_REV 0xf8300000 |
||||
#define CFG_EEPROM_BASE 0xf8b00000 |
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
/*
|
||||
* Base Register 3 and Option Register 3 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR3, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port-size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
||||
* |
||||
*/ |
||||
|
||||
#define CFG_BR3_PRELIM 0xf0001861 |
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
||||
* |
||||
* For OR3, need: |
||||
* 64MB mask for AM, OR3[0:7] = 1111 1100 |
||||
* XAM, OR3[17:18] = 11 |
||||
* 10 columns OR3[19-21] = 011 |
||||
* 12 rows OR3[23-25] = 011 |
||||
* EAD set for extra time OR[31] = 0 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 |
||||
*/ |
||||
|
||||
#define CFG_OR3_PRELIM 0xfc006cc0 |
||||
|
||||
#define CFG_LBC_LCRR 0x00000002 /* LB clock ratio reg */ |
||||
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ |
||||
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
||||
#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) |
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) |
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) |
||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
/*
|
||||
* Common settings for all Local Bus SDRAM commands. |
||||
* At run time, either BSMA1516 (for CPU 1.1) |
||||
* or BSMA1617 (for CPU 1.0) (old) |
||||
* is OR'ed in too. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ |
||||
| CFG_LBC_LSDMR_PRETOACT7 \
|
||||
| CFG_LBC_LSDMR_ACTTORW7 \
|
||||
| CFG_LBC_LSDMR_BL8 \
|
||||
| CFG_LBC_LSDMR_WRC4 \
|
||||
| CFG_LBC_LSDMR_CL3 \
|
||||
| CFG_LBC_LSDMR_RFEN \
|
||||
) |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
||||
|
||||
#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK 400000000 /* get_bus_freq(0) */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Memory space is mapped 1-1, but I/O space must start from 0. |
||||
*/ |
||||
#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
||||
|
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI1_IO_BASE 0x00000000 |
||||
#define CFG_PCI1_IO_PHYS 0xe2000000 |
||||
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ |
||||
|
||||
#ifdef CONFIG_PCI2 |
||||
#define CFG_PCI2_MEM_BASE 0xa0000000 |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI2_IO_BASE 0x00000000 |
||||
#define CFG_PCI2_IO_PHYS 0xe2800000 |
||||
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCIE1 |
||||
#define CFG_PCIE1_MEM_BASE 0xa0000000 |
||||
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE |
||||
#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCIE1_IO_BASE 0x00000000 |
||||
#define CFG_PCIE1_IO_PHYS 0xe3000000 |
||||
#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_RIO |
||||
/*
|
||||
* RapidIO MMU |
||||
*/ |
||||
#define CFG_RIO_MEM_BASE 0xC0000000 |
||||
#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_LEGACY |
||||
#define BRIDGE_ID 17 |
||||
#define VIA_ID 2 |
||||
#else |
||||
#define BRIDGE_ID 28 |
||||
#define VIA_ID 4 |
||||
#endif |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
|
||||
/* PCI view of System Memory */ |
||||
#define CFG_PCI_MEMORY_BUS 0x00000000 |
||||
#define CFG_PCI_MEMORY_PHYS 0x00000000 |
||||
#define CFG_PCI_MEMORY_SIZE 0x80000000 |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_TSEC1 1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC0" |
||||
#define CONFIG_TSEC2 1 |
||||
#define CONFIG_TSEC2_NAME "eTSEC1" |
||||
#define CONFIG_TSEC3 1 |
||||
#define CONFIG_TSEC3_NAME "eTSEC2" |
||||
#define CONFIG_TSEC4 |
||||
#define CONFIG_TSEC4_NAME "eTSEC3" |
||||
#undef CONFIG_MPC85XX_FEC |
||||
|
||||
#define TSEC1_PHY_ADDR 0 |
||||
#define TSEC2_PHY_ADDR 1 |
||||
#define TSEC3_PHY_ADDR 2 |
||||
#define TSEC4_PHY_ADDR 3 |
||||
|
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define TSEC3_PHYIDX 0 |
||||
#define TSEC4_PHYIDX 0 |
||||
#define TSEC1_FLAGS TSEC_GIGABIT |
||||
#define TSEC2_FLAGS TSEC_GIGABIT |
||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
|
||||
/* Options are: eTSEC[0-3] */ |
||||
#define CONFIG_ETHPRIME "eTSEC0" |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_ELF |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_CMD_PCI |
||||
#endif |
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
/* The mac addresses for all ethernet interface */ |
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_ETHADDR 02:E0:0C:00:00:FD |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD |
||||
#define CONFIG_HAS_ETH2 |
||||
#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD |
||||
#define CONFIG_HAS_ETH3 |
||||
#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD |
||||
#endif |
||||
|
||||
#define CONFIG_IPADDR 192.168.0.55 |
||||
|
||||
#define CONFIG_HOSTNAME sbc8548 |
||||
#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx |
||||
#define CONFIG_BOOTFILE /uImage |
||||
#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ |
||||
|
||||
#define CONFIG_SERVERIP 192.168.0.2 |
||||
#define CONFIG_GATEWAYIP 192.168.0.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
|
||||
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=uRamdisk\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=sbc8548.dtb\0" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue