Wolfgang Denk
15 years ago
commit
6a1f7e54c2
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/*
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* (C) Copyright 2009 Samsung Electronics |
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* Minkyu Kang <mk7.kang@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/gpio.h> |
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#define CON_MASK(x) (0xf << ((x) << 2)) |
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#define CON_SFR(x, v) ((v) << ((x) << 2)) |
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#define DAT_MASK(x) (0x1 << (x)) |
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#define DAT_SET(x) (0x1 << (x)) |
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#define PULL_MASK(x) (0x3 << ((x) << 1)) |
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#define PULL_MODE(x, v) ((v) << ((x) << 1)) |
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#define DRV_MASK(x) (0x3 << ((x) << 1)) |
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#define DRV_SET(x, m) ((m) << ((x) << 1)) |
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#define RATE_MASK(x) (0x1 << (x + 16)) |
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#define RATE_SET(x) (0x1 << (x + 16)) |
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void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg) |
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{ |
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unsigned int value; |
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value = readl(&bank->con); |
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value &= ~CON_MASK(gpio); |
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value |= CON_SFR(gpio, cfg); |
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writel(value, &bank->con); |
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} |
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void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en) |
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{ |
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unsigned int value; |
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gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); |
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value = readl(&bank->dat); |
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value &= ~DAT_MASK(gpio); |
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if (en) |
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value |= DAT_SET(gpio); |
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writel(value, &bank->dat); |
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} |
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void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio) |
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{ |
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gpio_cfg_pin(bank, gpio, GPIO_INPUT); |
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} |
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void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en) |
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{ |
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unsigned int value; |
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value = readl(&bank->dat); |
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value &= ~DAT_MASK(gpio); |
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if (en) |
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value |= DAT_SET(gpio); |
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writel(value, &bank->dat); |
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} |
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unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio) |
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{ |
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unsigned int value; |
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value = readl(&bank->dat); |
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return !!(value & DAT_MASK(gpio)); |
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} |
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void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) |
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{ |
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unsigned int value; |
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value = readl(&bank->pull); |
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value &= ~PULL_MASK(gpio); |
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switch (mode) { |
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case GPIO_PULL_DOWN: |
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case GPIO_PULL_UP: |
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value |= PULL_MODE(gpio, mode); |
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break; |
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default: |
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return; |
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} |
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writel(value, &bank->pull); |
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} |
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void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) |
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{ |
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unsigned int value; |
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value = readl(&bank->drv); |
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value &= ~DRV_MASK(gpio); |
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switch (mode) { |
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case GPIO_DRV_1X: |
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case GPIO_DRV_2X: |
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case GPIO_DRV_3X: |
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case GPIO_DRV_4X: |
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value |= DRV_SET(gpio, mode); |
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break; |
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default: |
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return; |
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} |
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writel(value, &bank->drv); |
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} |
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void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) |
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{ |
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unsigned int value; |
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value = readl(&bank->drv); |
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value &= ~RATE_MASK(gpio); |
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switch (mode) { |
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case GPIO_DRV_FAST: |
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case GPIO_DRV_SLOW: |
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value |= RATE_SET(gpio); |
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break; |
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default: |
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return; |
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} |
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writel(value, &bank->drv); |
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} |
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@ -0,0 +1,53 @@ |
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/*
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* Copyright (C) 2010 Samsung Electronics |
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* Naveen Krishna Ch <ch.naveen@samsung.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/smc.h> |
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/*
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* s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the |
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* band width control and bank control registers |
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* srom_bank - SROM Bank 0 to 5 |
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* smc_bw_conf - SMC Band witdh reg configuration value |
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* smc_bc_conf - SMC Bank Control reg configuration value |
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*/ |
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void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf) |
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{ |
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u32 tmp; |
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struct s5pc1xx_smc *srom; |
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if (cpu_is_s5pc100()) |
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srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE; |
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else |
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srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE; |
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/* Configure SMC_BW register to handle proper SROMC bank */ |
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tmp = srom->bw; |
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tmp &= ~(0xF << (srom_bank * 4)); |
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tmp |= smc_bw_conf; |
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srom->bw = tmp; |
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/* Configure SMC_BC register */ |
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srom->bc[srom_bank] = smc_bc_conf; |
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} |
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@ -0,0 +1,53 @@ |
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/*
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* (C) Copyright 2010 Samsung Electronics |
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* Naveen Krishna Ch <ch.naveen@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* Note: This file contains the register description for Memory subsystem |
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* (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. |
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* |
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* Only SROMC is defined as of now |
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*/ |
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#ifndef __ASM_ARCH_SMC_H_ |
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#define __ASM_ARCH_SMC_H_ |
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#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) |
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#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ |
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/* 1-> Byte base address*/ |
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#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) |
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#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) |
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#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ |
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#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ |
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#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ |
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#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ |
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#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ |
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#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ |
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#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ |
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#ifndef __ASSEMBLY__ |
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struct s5pc1xx_smc { |
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unsigned int bw; |
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unsigned int bc[6]; |
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}; |
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#endif /* __ASSEMBLY__ */ |
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ |
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void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); |
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#endif /* __ASM_ARCH_SMC_H_ */ |
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