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@ -105,6 +105,7 @@ |
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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#define CONFIG_PPC4xx_EMAC |
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#undef CONFIG_EXT_PHY |
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#define CONFIG_NET_MULTI 1 |
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@ -398,6 +399,7 @@ |
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* I2C EEPROM (CAT24WC16) for environment |
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*/ |
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#define CONFIG_HARD_I2C /* I2c with hardware support */ |
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#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
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#define CONFIG_SYS_I2C_SLAVE 0x7F |
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@ -410,16 +412,6 @@ |
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/* last 4 bits of the address */ |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CONFIG_SYS_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ |
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/* have only 8kB, 16kB is save here */ |
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* ... */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
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#endif |
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/*
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* Init Memory Controller: |
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* |
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@ -570,17 +562,6 @@ |
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#define DIMM_READ_ADDR 0xAB |
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#define DIMM_WRITE_ADDR 0xAA |
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#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ |
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#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ |
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#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ |
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#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ |
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#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ |
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#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ |
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#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ |
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#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ |
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#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ |
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#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ |
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/* Defines for CPC0_PLLMR1 Register fields */ |
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#define PLL_ACTIVE 0x80000000 |
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#define CPC0_PLLMR1_SSCS 0x80000000 |
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