Merge branch 'master' of /home/wd/git/u-boot/custodians

Makefile

@@ -1488,9 +1488,9 @@ v5fx30teval_flash_config: unconfig
 	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
 	@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
 	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
-		> $(obj)/board/avnet/v5fx30teval/config.tmp
+		> $(obj)board/avnet/v5fx30teval/config.tmp
 	@echo "TEXT_BASE := 0xFF1C0000" \
-		>> $(obj)/board/avnet/v5fx30teval/config.tmp
+		>> $(obj)board/avnet/v5fx30teval/config.tmp
 	@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
 
 VOH405_config:	unconfig

README.imx31

@@ -0,0 +1,13 @@
+i.MX31 specific Configuration Options:
+--------------------------------------
+
+- Timer precision:
+		CONFIG_MX31_TIMER_HIGH_PRECISION
+
+		Enable higher precision timer. The low-precision timer
+		(default) provides approximately 4% error, whereas the
+		high-precision timer is about 0.4% accurate. The extra
+		accuracy is achieved at the cost of higher computational
+		overhead, which, in places where time is measured, should
+		not be critical, so, it should be safe to enable this
+		option.

board/amcc/taihu/taihu.c

@@ -78,15 +78,6 @@ int checkboard(void)
 	return 0;
 }
 
-/*************************************************************************
- *  phys_size_t initdram
- *
- ************************************************************************/
-phys_size_t initdram(int board)
-{
-	return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
-}
-
 static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
 {
 	char stat;

board/atmel/at91rm9200dk/at91rm9200dk.c

@@ -47,7 +47,7 @@ int board_init (void)
 	/* so we do _nothing_ here */
 
 	/* arch number of AT91RM9200DK-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200;
+	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200DK;
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 

board/avnet/v5fx30teval/.gitignore

@@ -0,0 +1 @@
+/config.tmp

board/dave/PPChameleonEVB/PPChameleonEVB.c

@@ -203,31 +203,6 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-phys_size_t initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-#if 0 /* test-only */
-	for (;;) {
-		NAND_DISABLE_CE(1);
-		udelay(100);
-		NAND_ENABLE_CE(1);
-		udelay(100);
-	}
-#endif
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
 int testdram (void)
 {
 	/* TODO: XXX XXX XXX */

board/esd/pci405/pci405.c

@@ -357,37 +357,6 @@ int checkboard (void)
 }
 
 /* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
-#if 0 /* test-only: all PCI405 version must report 16mb */
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-#else
-	return (16*1024*1024);
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
 int wpeeprom(int wp)
 {
 	int wp_state = wp;

board/quad100hd/quad100hd.c

@@ -86,8 +86,3 @@ int checkboard(void)
 
 	return 0;
 }
-
-phys_size_t initdram(int board_type)
-{
-	return CFG_SDRAM_SIZE;
-}

board/xilinx/ml507/.gitignore

@@ -0,0 +1 @@
+/config.tmp

board/xilinx/ppc440-generic/.gitignore

@@ -0,0 +1 @@
+/config.tmp

board/xilinx/ppc440-generic/config.mk

@@ -22,4 +22,4 @@
 # MA 02111-1307 USA
 #
 
-sinclude $(obj)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp

board/zeus/zeus.c

@@ -190,29 +190,6 @@ int checkboard(void)
 	return (0);
 }
 
-static u32 detect_sdram_size(void)
-{
-	u32 val;
-	u32 size;
-
-	mfsdram(mem_mb0cf, val);
-	size = (4 << 20) << ((val & 0x000e0000) >> 17);
-
-	/*
-	 * Check if 2nd bank is enabled too
-	 */
-	mfsdram(mem_mb1cf, val);
-	if (val & 1)
-		size += (4 << 20) << ((val & 0x000e0000) >> 17);
-
-	return size;
-}
-
-phys_size_t initdram (int board_type)
-{
-	return detect_sdram_size();
-}
-
 static int default_env_var(char *buf, char *var)
 {
 	char *ptr;

config.mk

@@ -44,15 +44,6 @@ PLATFORM_RELFLAGS =
 PLATFORM_CPPFLAGS =
 PLATFORM_LDFLAGS =
 
-ifeq ($(ARCH),arm)
-ifeq ($(CROSS_COMPILE),powerpc-netbsd-)
-PLATFORM_CPPFLAGS+= -D__ARM__
-endif
-ifeq ($(CROSS_COMPILE),powerpc-openbsd-)
-PLATFORM_CPPFLAGS+= -D__ARM__
-endif
-endif
-
 #########################################################################
 
 CONFIG_SHELL	:= $(shell if [ -x "$$BASH" ]; then echo $$BASH; \

cpu/arm1136/mx31/interrupts.c

@@ -38,6 +38,9 @@
 #define GPTCR_CLKSOURCE_32 (4<<6)  /* Clock source */
 #define GPTCR_TEN       (1)     /* Timer enable */
 
+static ulong timestamp;
+static ulong lastinc;
+
 /* nothing really to do with interrupts, just starts up a counter. */
 int interrupt_init (void)
 {
@@ -54,14 +57,27 @@ int interrupt_init (void)
 
 void reset_timer_masked (void)
 {
-	GPTCR = 0;
-	GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */
+	/* reset time */
+	lastinc = GPTCNT; /* capture current incrementer value time */
+	timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
 }
 
 ulong get_timer_masked (void)
 {
-	ulong val = GPTCNT;
-	return val;
+	ulong now = GPTCNT; /* current tick value */
+
+	if (now >= lastinc)	/* normal mode (non roll) */
+		/* move stamp forward with absolut diff ticks */
+		timestamp += (now - lastinc);
+	else			/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	lastinc = now;
+	return timestamp;
 }
 
 ulong get_timer (ulong base)

cpu/arm920t/at91rm9200/i2c.c

@@ -203,4 +203,14 @@ void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
 	i2c_write(i2c_addr, reg, 1, &val, 1);
 }
 
+int i2c_set_bus_speed(unsigned int speed)
+{
+	return -1;
+}
+
+unsigned int i2c_get_bus_speed(void)
+{
+	return CFG_I2C_SPEED;
+}
+
 #endif /* CONFIG_HARD_I2C */

cpu/arm920t/imx/interrupts.c

@@ -60,7 +60,7 @@ void reset_timer (void)
 
 ulong get_timer (ulong base)
 {
-	return get_timer_masked ();
+	return get_timer_masked() - base;
 }
 
 void set_timer (ulong t)

cpu/arm920t/imx/serial.c

@@ -52,6 +52,8 @@ struct imx_serial {
 	volatile uint32_t uts;
 };
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void serial_setbrg (void)
 {
 	serial_init();
@@ -67,6 +69,9 @@ extern void imx_gpio_mode(int gpio_mode);
 int serial_init (void)
 {
 	volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
+	unsigned int ufcr_rfdiv;
+	unsigned int refclk;
+
 #ifdef CONFIG_IMX_SERIAL1
 	imx_gpio_mode(PC11_PF_UART1_TXD);
 	imx_gpio_mode(PC12_PF_UART1_RXD);
@@ -95,11 +100,33 @@ int serial_init (void)
 	/* Configure FIFOs */
 	base->ufcr = 0xa81;
 
+	/* set the baud rate.
+	 *
+	 * baud * 16   x
+	 * --------- = -
+	 *  refclk     y
+	 *
+	 * x - 1 = UBIR
+	 * y - 1 = UBMR
+	 *
+	 * each register is 16 bits wide. refclk max is 96 MHz
+	 *
+	 */
+
+	ufcr_rfdiv = ((base->ufcr) & UFCR_RFDIV) >> 7;
+	if (ufcr_rfdiv == 6)
+		ufcr_rfdiv = 7;
+	else
+		ufcr_rfdiv = 6 - ufcr_rfdiv;
+
+	refclk = get_PERCLK1();
+	refclk /= ufcr_rfdiv;
+
 	/* Set the numerator value minus one of the BRM ratio */
-	base->ubir = (CONFIG_BAUDRATE / 100) - 1;
+	base->ubir = (gd->baudrate / 100) - 1;
 
 	/* Set the denominator value minus one of the BRM ratio	*/
-	base->ubmr = 10000 - 1;
+	base->ubmr = (refclk/(16 * 100)) - 1;
 
 	/* Set to 8N1 */
 	base->ucr2 &= ~UCR2_PREN;
@@ -117,22 +144,21 @@ int serial_init (void)
 
 	/* Clear status flags */
 	base->usr2 |= USR2_ADET  |
-	          USR2_DTRF  |
-	          USR2_IDLE  |
-	          USR2_IRINT |
-	          USR2_WAKE  |
-	          USR2_RTSF  |
-	          USR2_BRCD  |
-	          USR2_ORE   |
-	          USR2_RDR;
+		      USR2_DTRF  |
+		      USR2_IDLE  |
+		      USR2_IRINT |
+		      USR2_WAKE  |
+		      USR2_RTSF  |
+		      USR2_BRCD  |
+		      USR2_ORE;
 
 	/* Clear status flags */
 	base->usr1 |= USR1_PARITYERR |
-	          USR1_RTSD      |
-	          USR1_ESCF      |
-	          USR1_FRAMERR   |
-	          USR1_AIRINT    |
-	          USR1_AWAKE;
+		      USR1_RTSD      |
+		      USR1_ESCF      |
+		      USR1_FRAMERR   |
+		      USR1_AIRINT    |
+		      USR1_AWAKE;
 	return (0);
 }
 

cpu/arm920t/start.S

@@ -315,7 +315,8 @@ cpu_init_crit:
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CONFIG_STACKSIZE)
+	sub	r2, r2, #(CFG_MALLOC_LEN)
 	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r3}			@ get pc, cpsr
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
@@ -348,7 +349,8 @@ cpu_init_crit:
 
 	.macro get_bad_stack
 	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CONFIG_STACKSIZE)
+	sub	r13, r13, #(CFG_MALLOC_LEN)
 	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]			@ save caller lr / spsr

cpu/arm926ejs/davinci/dp83848.c

@@ -64,29 +64,16 @@ int dp83848_get_link_speed(int phy_addr)
 		return(0);
 
 	/* Speed doesn't matter, there is no setting for it in EMAC... */
-	if (tmp & DP83848_SPEED) {
-		if (tmp & DP83848_DUPLEX) {
-			/* set DM644x EMAC for Full Duplex  */
-			emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
-		} else {
-			/*set DM644x EMAC for Half Duplex  */
-			emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
-		}
-
-		return(1);
+	if (tmp & DP83848_DUPLEX) {
+		/* set DM644x EMAC for Full Duplex  */
+		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+			EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
 	} else {
-		if (tmp & DP83848_DUPLEX) {
-			/* set DM644x EMAC for Full Duplex  */
-			emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
-		} else {
-			/*set DM644x EMAC for Half Duplex  */
-			emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
-		}
-
-		return(1);
+		/*set DM644x EMAC for Half Duplex  */
+		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
 	}
 
-	return(0);
+	return(1);
 }
 
 

cpu/ppc4xx/sdram.c

@@ -209,15 +209,15 @@ phys_size_t initdram(int board_type)
 		udelay(10000);
 
 		if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+			phys_size_t size = mb0cf[i].size;
+
 			/*
 			 * OK, size detected.  Enable second bank if
 			 * defined (assumes same type as bank 0)
 			 */
 #ifdef CONFIG_SDRAM_BANK1
-			u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
-
 			mtsdram(mem_mcopt1, 0x00000000);
-			mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
+			mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
 			mtsdram(mem_mcopt1, 0x80800000);
 			udelay(10000);
 
@@ -230,13 +230,19 @@ phys_size_t initdram(int board_type)
 			    mb0cf[i].size) {
 				mtsdram(mem_mb1cf, 0);
 				mtsdram(mem_mcopt1, 0);
+			} else {
+				/*
+				 * We have two identical banks, so the size
+				 * is twice the bank size
+				 */
+				size = 2 * size;
 			}
 #endif
 
 			/*
 			 * OK, size detected -> all done
 			 */
-			return mb0cf[i].size;
+			return size;
 		}
 	}
 

cpu/pxa/mmc.c

@@ -575,8 +575,8 @@ mmc_init(int verbose)
 			break;
 		}
 
-		/* Select 3.2-3.3 and 3.3-3.4V */
-		resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0020, 0,
+		/* Select 3.2-3.3V and 3.3-3.4V */
+		resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0030, 0x0000,
 				MMC_CMDAT_R3 | (retries < 2 ? 0
 					: MMC_CMDAT_INIT));
 		if (resp[0] & 0x80000000) {

doc/README.mx31

@@ -0,0 +1,19 @@
+
+U-Boot for Freescale i.MX31
+
+This file contains information for the port of U-Boot to the Freescale
+i.MX31 SoC.
+
+1. CONFIGURATION OPTIONS/SETTINGS
+---------------------------------
+
+1.1 Configuration of MC13783 SPI bus
+------------------------------------
+The power management companion chip MC13783 is connected to the
+i.MX31 via an SPI bus. Use the following configuration options
+to setup the bus and chip select used for a particular board.
+
+CONFIG_MC13783_SPI_BUS	-- defines the SPI bus the MC13783 is connected to.
+			   Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3.
+CONFIG_MC13783_SPI_CS	-- define the chip select the MC13783 s connected to.
+

drivers/rtc/mc13783-rtc.c

@@ -34,7 +34,8 @@ int rtc_get(struct rtc_time *rtc)
 
 	if (!slave) {
 		/* FIXME: Verify the max SCK rate */
-		slave = spi_setup_slave(1, 0, 1000000,
+		slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
+				CONFIG_MC13783_SPI_CS, 1000000,
 				SPI_MODE_2 | SPI_CS_HIGH);
 		if (!slave)
 			return -1;
@@ -83,7 +84,8 @@ int rtc_set(struct rtc_time *rtc)
 
 	if (!slave) {
 		/* FIXME: Verify the max SCK rate */
-		slave = spi_setup_slave(1, 0, 1000000,
+		slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
+				CONFIG_MC13783_SPI_CS, 1000000,
 				SPI_MODE_2 | SPI_CS_HIGH);
 		if (!slave)
 			return -1;

include/configs/imx31_litekit.h

@@ -69,6 +69,9 @@
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
 
 #define CONFIG_RTC_MC13783	1
+/* MC13783 connected to CSPI2 and SS0 */
+#define CONFIG_MC13783_SPI_BUS	1
+#define CONFIG_MC13783_SPI_CS	0
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE

include/configs/mx31ads.h

@@ -66,6 +66,9 @@
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
 
 #define CONFIG_RTC_MC13783	1
+/* MC13783 connected to CSPI2 and SS0 */
+#define CONFIG_MC13783_SPI_BUS	1
+#define CONFIG_MC13783_SPI_CS	0
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE

include/configs/omap1510.h

@@ -482,7 +482,7 @@
 /*  CNTL_TIMER register bits */
 #define MPUTIM_FREE		(1<<6)
 #define MPUTIM_CLOCK_ENABLE	(1<<5)
-#define MPUTIM_PTV_MASK		(0x7<<PTV_BIT)
+#define MPUTIM_PTV_MASK		(0x7<<MPUTIM_PTV_BIT)
 #define MPUTIM_PTV_BIT		2
 #define MPUTIM_AR		(1<<1)
 #define MPUTIM_ST		(1<<0)

include/configs/omap730.h

@@ -150,7 +150,7 @@
 /* MPU_CNTL_TIMER register bits */
 #define MPUTIM_FREE               (1<<6)
 #define MPUTIM_CLOCK_ENABLE       (1<<5)
-#define MPUTIM_PTV_MASK           (0x7<<PTV_BIT)
+#define MPUTIM_PTV_MASK           (0x7<<MPUTIM_PTV_BIT)
 #define MPUTIM_PTV_BIT            2
 #define MPUTIM_AR                 (1<<1)
 #define MPUTIM_ST                 (1<<0)

include/configs/quad100hd.h

@@ -82,7 +82,6 @@
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  */
 #define CONFIG_SDRAM_BANK0  1
-#define CFG_SDRAM_SIZE      0x02000000      /* 32 MB */
 
 /* FIX! SDRAM timings used in datasheet */
 #define CFG_SDRAM_CL            3       /* CAS latency */

include/configs/zeus.h

@@ -309,6 +309,12 @@
 #define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
 #endif
 
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
 /* ENVIRONMENT VARS */
 
 #define CONFIG_PREBOOT		"echo;echo Welcome to Bulletendpoints board v1.1;echo"