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arm: zynq: Add support for DLC20 board

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Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).

Boards have mix of Winbond/ST QSPIs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
lime2-spi
Michal Simek 6 years ago
parent 0e4c1dd290
commit 6bfe3fffac
4 changed files with 458 additions and 0 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 1
      arch/arm/dts/Makefile
  2. 103
      arch/arm/dts/zynq-dlc20-rev1.0.dts
  3. 280
      board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
  4. 74
      configs/zynq_dlc20_rev1_0_defconfig

1
arch/arm/dts/Makefile
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@ -135,6 +135,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cse-nand.dtb \
zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-dlc20-rev1.0.dtb \
zynq-microzed.dtb \
zynq-minized.dtb \
zynq-picozed.dtb \

103
arch/arm/dts/zynq-dlc20-rev1.0.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
model = "Zynq DLC20 Rev1.0";
compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20",
"xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
spi0 = &qspi;
mmc0 = &sdhci0;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x20000000>;
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
usb_phy0: phy0@e0002000 {
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&clkc {
ps-clk-frequency = <33333333>; /* U7 */
};
&gem0 {
status = "okay"; /* MIO16-MIO27, MDIO MIO52/53 */
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@7 { /* rtl8211e - U25 */
reg = <1>;
};
};
&i2c0 {
status = "okay"; /* MIO14/15 */
clock-frequency = <400000>;
/* U46 - m24c08 */
eeprom: eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
is-dual = <0>;
num-cs = <1>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
flash@0 {
/* Rev1.0 W25Q128FWSIG, RevC N25Q128A */
compatible = "n25q128a11", "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
};
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */
non-removable;
bus-width = <4>;
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay"; /* MIO8/9 */
};
&usb0 {
status = "okay"; /* MIO28-MIO39 */
dr_mode = "device";
usb-phy = <&usb_phy0>;
};
&watchdog0 {
reset-on-timeout;
};

280
board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*/
#include <asm/arch/ps7_init_gpl.h>
static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
EMIT_MASKPOLL(0xF800010C, 0x00000001U),
EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
EMIT_MASKPOLL(0xF800010C, 0x00000002U),
EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
EMIT_MASKPOLL(0xF800010C, 0x00000004U),
EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_EXIT(),
};
static unsigned long ps7_clock_init_data_3_0[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00000A01U),
EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U),
EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_EXIT(),
};
static unsigned long ps7_ddr_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159AU),
EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0FF66666U),
EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00029000U),
EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029000U),
EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00029000U),
EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00029000U),
EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x00000080U),
EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x00000080U),
EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000080U),
EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000080U),
EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F9U),
EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F9U),
EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F9U),
EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F9U),
EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000C0U),
EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000C0U),
EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000C0U),
EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000C0U),
EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
EMIT_MASKPOLL(0xF8006054, 0x00000007U),
EMIT_EXIT(),
};
static unsigned long ps7_mio_init_data_3_0[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U),
EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U),
EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U),
EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001200U),
EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000200U),
EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x000002E0U),
EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x000012E1U),
EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001200U),
EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001200U),
EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001200U),
EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001200U),
EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001240U),
EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001240U),
EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00001201U),
EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001200U),
EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001200U),
EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001218U),
EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_EXIT(),
};
static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0xF8F00200, 1),
EMIT_MASKDELAY(0xF8F00200, 1),
EMIT_MASKDELAY(0xF8F00200, 1),
EMIT_MASKDELAY(0xF8F00200, 1),
EMIT_MASKDELAY(0xF8F00200, 1),
EMIT_MASKDELAY(0xF8F00200, 1),
EMIT_EXIT(),
};
static unsigned long ps7_post_config_3_0[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_EXIT(),
};
int ps7_post_config(void)
{
int ret = -1;
ret = ps7_config(ps7_post_config_3_0);
if (ret != PS7_INIT_SUCCESS)
return ret;
return PS7_INIT_SUCCESS;
}
int ps7_init(void)
{
int ret;
ret = ps7_config(ps7_mio_init_data_3_0);
if (ret != PS7_INIT_SUCCESS)
return ret;
ret = ps7_config(ps7_pll_init_data_3_0);
if (ret != PS7_INIT_SUCCESS)
return ret;
ret = ps7_config(ps7_clock_init_data_3_0);
if (ret != PS7_INIT_SUCCESS)
return ret;
ret = ps7_config(ps7_ddr_init_data_3_0);
if (ret != PS7_INIT_SUCCESS)
return ret;
ret = ps7_config(ps7_peripherals_init_data_3_0);
if (ret != PS7_INIT_SUCCESS)
return ret;
return PS7_INIT_SUCCESS;
}

74
configs/zynq_dlc20_rev1_0_defconfig
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CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_IDENT_STRING=" Xilinx Zynq DLC20 Rev1.0"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_FPGA_LOADMK=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-dlc20-rev1.0"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C0=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
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