Add documentation for the "serdes" hwconfig option, which is used to specify the status of SerDes banks two and three for the SERDES8 erratum work-around. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>master
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Overview |
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The P4080DS is a Freescale reference board that hosts the eight-core P4080 SOC. |
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SerDes hwconfig configuration |
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----------------------------- |
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The P4080 RCW includes three sets of bits the specify which SerDes lanes |
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should be powered down: SRDS_LPD_B1 (for bank one), SRDS_LPD_B2 (for bank two), |
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and SRDS_LPD_B3 (for bank three). Each of these contains four bits, one for |
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each lane in the bank. SerDes Erratum SERDES8 requires that SRDS_LPD_B2 and |
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SRDS_LPD_B3 be set to 0b1111. This forces banks two and three to be powered |
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down at reset. |
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To re-enable these banks in U-Boot, two hwconfig are available: |
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"fsl_srds_lpd_b2" and "fsl_srds_lpd_b3". The value passed via fsl_srds_lpd_b2 |
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is written into SRDS_LPD_B2, and the value passed via fsl_srds_lpd_b3 is into |
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SRDS_LPD_B3. Each bit represents one of each bank, and a value of '1' |
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indicates that the lane should be powered down. |
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For example, to indicate that both SerDes banks 2 and 3 are powered down, add |
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the following to hwconfig: |
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serdes:fsl_srds_lpd_b2=0xf,fsl_srds_lpd_b3=0xf |
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The "0xf" is a mask that corresponds to the 4 lanes A-D. The most significant |
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bit corresponds to lane A. To indicate that just lane A of bank 3 is to be |
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powered down, use: |
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serdes:fsl_srds_lpd_b3=8 |
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These options should be specified only if U-Boot does not automatically power |
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on the correct lanes. |
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