There are some functions like sdram_size_mb can be re-used for different rockchip SoCs, just put them into common file. Add board_get_usable_ram_top() for ram_top init base on SDRAM_MAX_SIZE. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Added SDRAM_MAX_SIZE definition for RK3036: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> fixup: 3036 fix for sdram_commonmaster
Kever Yang
7 years ago
committed by
Philipp Tomsich
parent
be8da534e2
commit
6d1970fa8a
@ -0,0 +1,58 @@ |
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/*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_SDRAM_COMMON_H |
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#define _ASM_ARCH_SDRAM_COMMON_H |
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/*
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* sys_reg bitfield struct |
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* [31] row_3_4_ch1 |
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* [30] row_3_4_ch0 |
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* [29:28] chinfo |
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* [27] rank_ch1 |
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* [26:25] col_ch1 |
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* [24] bk_ch1 |
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* [23:22] cs0_row_ch1 |
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* [21:20] cs1_row_ch1 |
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* [19:18] bw_ch1 |
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* [17:16] dbw_ch1; |
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* [15:13] ddrtype |
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* [12] channelnum |
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* [11] rank_ch0 |
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* [10:9] col_ch0 |
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* [8] bk_ch0 |
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* [7:6] cs0_row_ch0 |
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* [5:4] cs1_row_ch0 |
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* [3:2] bw_ch0 |
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* [1:0] dbw_ch0 |
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*/ |
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#define SYS_REG_DDRTYPE_SHIFT 13 |
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#define SYS_REG_DDRTYPE_MASK 7 |
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#define SYS_REG_NUM_CH_SHIFT 12 |
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#define SYS_REG_NUM_CH_MASK 1 |
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#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) |
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#define SYS_REG_ROW_3_4_MASK 1 |
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#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) |
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#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) |
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#define SYS_REG_RANK_MASK 1 |
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#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) |
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#define SYS_REG_COL_MASK 3 |
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#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) |
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#define SYS_REG_BK_MASK 1 |
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#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) |
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#define SYS_REG_CS0_ROW_MASK 3 |
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#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) |
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#define SYS_REG_CS1_ROW_MASK 3 |
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#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) |
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#define SYS_REG_BW_MASK 3 |
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#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) |
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#define SYS_REG_DBW_MASK 3 |
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/* Get sdram size decode from reg */ |
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size_t rockchip_sdram_size(phys_addr_t reg); |
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/* Called by U-Boot board_init_r for Rockchip SoCs */ |
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int dram_init(void); |
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#endif |
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@ -0,0 +1,83 @@ |
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/*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <ram.h> |
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#include <asm/io.h> |
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#include <asm/arch/sdram_common.h> |
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#include <dm/uclass-internal.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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size_t rockchip_sdram_size(phys_addr_t reg) |
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{ |
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u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; |
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size_t chipsize_mb = 0; |
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size_t size_mb = 0; |
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u32 ch; |
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u32 sys_reg = readl(reg); |
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u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) |
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& SYS_REG_NUM_CH_MASK); |
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debug("%s %x %x\n", __func__, (u32)reg, sys_reg); |
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for (ch = 0; ch < ch_num; ch++) { |
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rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & |
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SYS_REG_RANK_MASK); |
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col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); |
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bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); |
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cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & |
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SYS_REG_CS0_ROW_MASK); |
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cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & |
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SYS_REG_CS1_ROW_MASK); |
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bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & |
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SYS_REG_BW_MASK)); |
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row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & |
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SYS_REG_ROW_3_4_MASK; |
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chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); |
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if (rank > 1) |
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chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); |
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if (row_3_4) |
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chipsize_mb = chipsize_mb * 3 / 4; |
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size_mb += chipsize_mb; |
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debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", |
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rank, col, bk, cs0_row, bw, row_3_4); |
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} |
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return (size_t)size_mb << 20; |
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} |
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int dram_init(void) |
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{ |
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struct ram_info ram; |
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struct udevice *dev; |
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int ret; |
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ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
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if (ret) { |
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debug("DRAM init failed: %d\n", ret); |
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return ret; |
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} |
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ret = ram_get_info(dev, &ram); |
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if (ret) { |
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debug("Cannot get DRAM size: %d\n", ret); |
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return ret; |
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} |
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gd->ram_size = ram.size; |
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debug("SDRAM base=%lx, size=%lx\n", |
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(unsigned long)ram.base, (unsigned long)ram.size); |
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return 0; |
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} |
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ulong board_get_usable_ram_top(ulong total_size) |
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{ |
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unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; |
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return (gd->ram_top > top) ? top : gd->ram_top; |
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} |
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