Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>master
parent
80ba61fd82
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6d33c6acfa
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,25 @@ |
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xFF800000
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@ -0,0 +1,467 @@ |
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/*
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* (C) Copyright 2000-2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/immap.h> |
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#ifndef CFG_FLASH_CFI |
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typedef unsigned short FLASH_PORT_WIDTH; |
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typedef volatile unsigned short FLASH_PORT_WIDTHV; |
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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#define FLASH_CYCLE1 0x5555 |
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#define FLASH_CYCLE2 0x2aaa |
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#define SYNC __asm__("nop") |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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ulong flash_get_size(FPWV * addr, flash_info_t * info); |
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int flash_get_offsets(ulong base, flash_info_t * info); |
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int write_word(flash_info_t * info, FPWV * dest, u16 data); |
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void inline spin_wheel(void); |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; |
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ulong flash_init(void) |
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{ |
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ulong size = 0; |
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ulong fbase = 0; |
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fbase = (ulong) CFG_FLASH_BASE; |
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flash_get_size((FPWV *) fbase, &flash_info[0]); |
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flash_get_offsets((ulong) fbase, &flash_info[0]); |
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fbase += flash_info[0].size; |
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size += flash_info[0].size; |
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/* Protect monitor and environment sectors */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_MONITOR_BASE, |
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CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); |
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return size; |
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} |
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int flash_get_offsets(ulong base, flash_info_t * info) |
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{ |
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int j, k; |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { |
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info->start[0] = base; |
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for (k = 0, j = 0; j < CFG_SST_SECT; j++, k++) { |
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info->start[k + 1] = info->start[k] + CFG_SST_SECTSZ; |
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info->protect[k] = 0; |
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} |
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} |
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return ERR_OK; |
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} |
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void flash_print_info(flash_info_t * info) |
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{ |
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int i; |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_SST: |
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printf("SST "); |
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break; |
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default: |
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printf("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_SST6401B: |
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printf("SST39VF6401B\n"); |
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break; |
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default: |
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printf("Unknown Chip Type\n"); |
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return; |
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} |
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if (info->size > 0x100000) { |
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int remainder; |
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printf(" Size: %ld", info->size >> 20); |
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remainder = (info->size % 0x100000); |
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if (remainder) { |
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remainder >>= 10; |
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remainder = (int)((float) |
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(((float)remainder / (float)1024) * |
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10000)); |
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printf(".%d ", remainder); |
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} |
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printf("MB in %d Sectors\n", info->sector_count); |
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} else |
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printf(" Size: %ld KB in %d Sectors\n", |
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info->size >> 10, info->sector_count); |
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printf(" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf("\n "); |
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printf(" %08lX%s", |
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info->start[i], info->protect[i] ? " (RO)" : " "); |
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} |
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printf("\n"); |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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ulong flash_get_size(FPWV * addr, flash_info_t * info) |
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{ |
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u16 value; |
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addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ |
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addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ |
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addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ |
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switch (addr[0] & 0xffff) { |
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case (u8) SST_MANUFACT: |
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info->flash_id = FLASH_MAN_SST; |
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value = addr[1]; |
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break; |
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default: |
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printf("Unknown Flash\n"); |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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*addr = (FPW) 0x00F000F0; |
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return (0); /* no or unknown flash */ |
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} |
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switch (value) { |
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case (u16) SST_ID_xF6401B: |
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info->flash_id += FLASH_SST6401B; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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break; |
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} |
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info->sector_count = 0; |
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info->size = 0; |
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info->sector_count = CFG_SST_SECT; |
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info->size = CFG_SST_SECT * CFG_SST_SECTSZ; |
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/* reset ID mode */ |
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*addr = (FPWV) 0x00F000F0; |
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if (info->sector_count > CFG_MAX_FLASH_SECT) { |
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printf("** ERROR: sector count %d > max (%d) **\n", |
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info->sector_count, CFG_MAX_FLASH_SECT); |
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info->sector_count = CFG_MAX_FLASH_SECT; |
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} |
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return (info->size); |
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} |
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int flash_erase(flash_info_t * info, int s_first, int s_last) |
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{ |
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FPWV *addr; |
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int flag, prot, sect, count; |
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ulong type, start, last; |
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int rcode = 0, flashtype = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) |
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printf("- missing\n"); |
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else |
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printf("- no sectors to erase\n"); |
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return 1; |
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} |
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type = (info->flash_id & FLASH_VENDMASK); |
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switch (type) { |
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case FLASH_MAN_SST: |
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flashtype = 1; |
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break; |
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default: |
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type = (info->flash_id & FLASH_VENDMASK); |
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printf("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) |
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printf("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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else |
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printf("\n"); |
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flag = disable_interrupts(); |
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start = get_timer(0); |
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last = start; |
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if ((s_last - s_first) == (CFG_SST_SECT - 1)) { |
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if (prot == 0) { |
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addr = (FPWV *) info->start[0]; |
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addr[FLASH_CYCLE1] = 0x00AA; /* unlock */ |
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addr[FLASH_CYCLE2] = 0x0055; /* unlock */ |
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addr[FLASH_CYCLE1] = 0x0080; /* erase mode */ |
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addr[FLASH_CYCLE1] = 0x00AA; /* unlock */ |
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addr[FLASH_CYCLE2] = 0x0055; /* unlock */ |
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*addr = 0x0030; /* erase chip */ |
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count = 0; |
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start = get_timer(0); |
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while ((*addr & 0x0080) != 0x0080) { |
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if (count++ > 0x10000) { |
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spin_wheel(); |
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count = 0; |
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} |
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if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { |
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printf("Timeout\n"); |
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*addr = 0x00F0; /* reset to read mode */ |
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return 1; |
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} |
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} |
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*addr = 0x00F0; /* reset to read mode */ |
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printf("\b. done\n"); |
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if (flag) |
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enable_interrupts(); |
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return 0; |
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} else if (prot == CFG_SST_SECT) { |
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return 1; |
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} |
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} |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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addr = (FPWV *) (info->start[sect]); |
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printf("."); |
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/* arm simple, non interrupt dependent timer */ |
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start = get_timer(0); |
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switch (flashtype) { |
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case 1: |
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{ |
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FPWV *base; /* first address in bank */ |
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flag = disable_interrupts(); |
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base = (FPWV *) (CFG_FLASH_BASE); /* First sector */ |
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base[FLASH_CYCLE1] = 0x00AA; /* unlock */ |
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base[FLASH_CYCLE2] = 0x0055; /* unlock */ |
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base[FLASH_CYCLE1] = 0x0080; /* erase mode */ |
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base[FLASH_CYCLE1] = 0x00AA; /* unlock */ |
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base[FLASH_CYCLE2] = 0x0055; /* unlock */ |
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*addr = 0x0050; /* erase sector */ |
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if (flag) |
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enable_interrupts(); |
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while ((*addr & 0x0080) != 0x0080) { |
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if (get_timer(start) > |
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CFG_FLASH_ERASE_TOUT) { |
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printf("Timeout\n"); |
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*addr = 0x00F0; /* reset to read mode */ |
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rcode = 1; |
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break; |
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} |
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} |
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*addr = 0x00F0; /* reset to read mode */ |
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break; |
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} |
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} /* switch (flashtype) */ |
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} |
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} |
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printf(" done\n"); |
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if (flag) |
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enable_interrupts(); |
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return rcode; |
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} |
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int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
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{ |
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ulong wp, count; |
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u16 data; |
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int rc, port_width; |
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if (info->flash_id == FLASH_UNKNOWN) |
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return 4; |
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/* get lower word aligned address */ |
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wp = addr; |
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port_width = sizeof(FPW); |
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/* handle unaligned start bytes */ |
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if (wp & 1) { |
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data = *((FPWV *) wp); |
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data = (data << 8) | *src; |
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if ((rc = write_word(info, (FPWV *) wp, data)) != 0) |
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return (rc); |
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wp++; |
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cnt -= 1; |
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src++; |
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} |
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while (cnt >= 2) { |
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/*
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* handle word aligned part |
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*/ |
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count = 0; |
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data = *((FPWV *) src); |
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if ((rc = write_word(info, (FPWV *) wp, data)) != 0) |
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return (rc); |
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wp += 2; |
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src += 2; |
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cnt -= 2; |
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if (count++ > 0x800) { |
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spin_wheel(); |
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count = 0; |
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} |
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} |
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/* handle word aligned part */ |
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if (cnt) { |
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/* handle word aligned part */ |
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count = 0; |
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data = *((FPWV *) wp); |
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data = (data & 0x00FF) | (*src << 8); |
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if ((rc = write_word(info, (FPWV *) wp, data)) != 0) |
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return (rc); |
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wp++; |
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src++; |
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cnt -= 1; |
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if (count++ > 0x800) { |
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spin_wheel(); |
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count = 0; |
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} |
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} |
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if (cnt == 0) |
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return ERR_OK; |
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return ERR_OK; |
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} |
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/*-----------------------------------------------------------------------
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* Write a word to Flash |
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* A word is 16 bits, whichever the bus width of the flash bank |
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* (not an individual chip) is. |
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* |
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* returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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int write_word(flash_info_t * info, FPWV * dest, u16 data) |
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{ |
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ulong start; |
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int flag; |
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int res = 0; /* result, assume success */ |
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FPWV *base; /* first address in flash bank */ |
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/* Check if Flash is (sufficiently) erased */ |
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if ((*dest & (u8) data) != (u8) data) { |
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return (2); |
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} |
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base = (FPWV *) (CFG_FLASH_BASE); |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ |
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base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ |
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base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */ |
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*dest = data; /* start programming the data */ |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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start = get_timer(0); |
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/* data polling for D7 */ |
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while (res == 0 |
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&& (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) { |
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if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
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*dest = (u8) 0x00F000F0; /* reset bank */ |
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res = 1; |
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} |
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} |
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*dest++ = (u8) 0x00F000F0; /* reset bank */ |
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return (res); |
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} |
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void inline spin_wheel(void) |
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{ |
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static int p = 0; |
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static char w[] = "\\/-"; |
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printf("\010%c", w[p]); |
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(++p == 3) ? (p = 0) : 0; |
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} |
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#endif |
@ -0,0 +1,140 @@ |
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/*
|
||||
* (C) Copyright 2000-2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
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* Hayden Fraser (Hayden.Fraser@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
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* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
||||
#include <common.h> |
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#include <asm/immap.h> |
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|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: "); |
||||
puts("Freescale MCF5253 DEMO\n"); |
||||
return 0; |
||||
}; |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
u32 dramsize = 0; |
||||
|
||||
/*
|
||||
* Check to see if the SDRAM has already been initialized |
||||
* by a run control tool |
||||
*/ |
||||
if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { |
||||
u32 RC, temp; |
||||
|
||||
RC = (CFG_CLK / 1000000) >> 1; |
||||
RC = (RC * 15) >> 4; |
||||
|
||||
/* Initialize DRAM Control Register: DCR */ |
||||
mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); |
||||
__asm__("nop"); |
||||
|
||||
mbar_writeLong(MCFSIM_DACR0, 0x00003224); |
||||
__asm__("nop"); |
||||
|
||||
/* Initialize DMR0 */ |
||||
dramsize = (CFG_SDRAM_SIZE << 20); |
||||
temp = (dramsize - 1) & 0xFFFC0000; |
||||
mbar_writeLong(MCFSIM_DMR0, temp | 1); |
||||
__asm__("nop"); |
||||
|
||||
mbar_writeLong(MCFSIM_DACR0, 0x0000322c); |
||||
__asm__("nop"); |
||||
|
||||
/* Write to this block to initiate precharge */ |
||||
*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5; |
||||
__asm__("nop"); |
||||
|
||||
/* Set RE bit in DACR */ |
||||
mbar_writeLong(MCFSIM_DACR0, |
||||
mbar_readLong(MCFSIM_DACR0) | 0x8000); |
||||
__asm__("nop"); |
||||
|
||||
/* Wait for at least 8 auto refresh cycles to occur */ |
||||
udelay(500); |
||||
|
||||
/* Finish the configuration by issuing the MRS */ |
||||
mbar_writeLong(MCFSIM_DACR0, |
||||
mbar_readLong(MCFSIM_DACR0) | 0x0040); |
||||
__asm__("nop"); |
||||
|
||||
*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5; |
||||
} |
||||
|
||||
return dramsize; |
||||
} |
||||
|
||||
int testdram(void) |
||||
{ |
||||
/* TODO: XXX XXX XXX */ |
||||
printf("DRAM test not implemented!\n"); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_IDE |
||||
#include <ata.h> |
||||
int ide_preinit(void) |
||||
{ |
||||
return (0); |
||||
} |
||||
|
||||
void ide_set_reset(int idereset) |
||||
{ |
||||
volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR; |
||||
long period; |
||||
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ |
||||
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ |
||||
{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ |
||||
{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ |
||||
{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ |
||||
{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ |
||||
}; |
||||
|
||||
if (idereset) { |
||||
ata->cr = 0; /* control reset */ |
||||
udelay(100); |
||||
} else { |
||||
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); |
||||
|
||||
#define CALC_TIMING(t) (t + period - 1) / period |
||||
period = 1000000000 / (CFG_CLK / 2); /* period in ns */ |
||||
|
||||
/*ata->ton = CALC_TIMING (180); */ |
||||
ata->t1 = CALC_TIMING(piotms[2][0]); |
||||
ata->t2w = CALC_TIMING(piotms[2][1]); |
||||
ata->t2r = CALC_TIMING(piotms[2][1]); |
||||
ata->ta = CALC_TIMING(piotms[2][8]); |
||||
ata->trd = CALC_TIMING(piotms[2][7]); |
||||
ata->t4 = CALC_TIMING(piotms[2][3]); |
||||
ata->t9 = CALC_TIMING(piotms[2][6]); |
||||
|
||||
ata->cr = 0x40; /* IORDY enable */ |
||||
udelay(2000); |
||||
ata->cr |= 0x01; /* IORDY enable */ |
||||
} |
||||
} |
||||
#endif /* CONFIG_CMD_IDE */ |
@ -0,0 +1,144 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(m68k) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mcf52x2/start.o (.text) |
||||
lib_m68k/traps.o (.text) |
||||
cpu/mcf52x2/interrupts.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .; |
||||
common/environment.o (.text) |
||||
|
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
|
||||
.reloc : |
||||
{ |
||||
__got_start = .; |
||||
*(.got) |
||||
__got_end = .; |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
_sbss = .; |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
_ebss = .; |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,252 @@ |
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
||||
* Hayden Fraser (Hayden.Fraser@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _M5253DEMO_H |
||||
#define _M5253DEMO_H |
||||
|
||||
#define CONFIG_MCF52x2 /* define processor family */ |
||||
#define CONFIG_M5253 /* define processor type */ |
||||
#define CONFIG_M5253DEMO /* define board type */ |
||||
|
||||
#define CONFIG_MCFTMR |
||||
|
||||
#define CONFIG_MCFUART |
||||
#define CFG_UART_PORT (0) |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
||||
|
||||
#undef CONFIG_WATCHDOG /* disable watchdog */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash |
||||
*/ |
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM |
||||
# define CFG_ENV_OFFSET 0x4000 |
||||
# define CFG_ENV_SECT_SIZE 0x1000 |
||||
# define CFG_ENV_IS_IN_FLASH 1 |
||||
#else |
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) |
||||
# define CFG_ENV_SECT_SIZE 0x1000 |
||||
# define CFG_ENV_IS_IN_FLASH 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_LOADB |
||||
#define CONFIG_CMD_LOADS |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_MISC |
||||
#define CONFIG_CMD_PING |
||||
|
||||
#ifdef CONFIG_CMD_IDE |
||||
/* ATA */ |
||||
# define CONFIG_DOS_PARTITION |
||||
# define CONFIG_MAC_PARTITION |
||||
# define CONFIG_IDE_RESET 1 |
||||
# define CONFIG_IDE_PREINIT 1 |
||||
# define CONFIG_ATAPI |
||||
# undef CONFIG_LBA48 |
||||
|
||||
# define CFG_IDE_MAXBUS 1 |
||||
# define CFG_IDE_MAXDEVICE 2 |
||||
|
||||
# define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800) |
||||
# define CFG_ATA_IDE0_OFFSET 0 |
||||
|
||||
# define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
||||
# define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ |
||||
# define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ |
||||
# define CFG_ATA_STRIDE 4 /* Interval between registers */ |
||||
# define _IO_BASE 0 |
||||
#endif |
||||
|
||||
#define CONFIG_DRIVER_DM9000 |
||||
#ifdef CONFIG_DRIVER_DM9000 |
||||
# define CONFIG_DM9000_BASE ((CFG_CSAR1 << 16) | 0x300) |
||||
# define DM9000_IO CONFIG_DM9000_BASE |
||||
# define DM9000_DATA (CONFIG_DM9000_BASE + 4) |
||||
# undef CONFIG_DM9000_DEBUG |
||||
|
||||
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 |
||||
# define CONFIG_IPADDR 10.82.121.249 |
||||
# define CONFIG_NETMASK 255.255.252.0 |
||||
# define CONFIG_SERVERIP 10.82.120.80 |
||||
# define CONFIG_GATEWAYIP 10.82.123.254 |
||||
# define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
|
||||
# define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=10000\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr) ${u-boot}\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off 0 2ffff;" \
|
||||
"era 0 2ffff;" \
|
||||
"cp.b ${loadaddr} 0 ${filesize};" \
|
||||
"save\0" \
|
||||
"" |
||||
#endif |
||||
|
||||
#define CONFIG_HOSTNAME M5253DEMO |
||||
|
||||
#define CFG_PROMPT "=> " |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 |
||||
|
||||
#define CFG_MEMTEST_START 0x400 |
||||
#define CFG_MEMTEST_END 0x380000 |
||||
|
||||
#define CFG_HZ 1000 |
||||
|
||||
#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ |
||||
#define CFG_FAST_CLK |
||||
#ifdef CFG_FAST_CLK |
||||
# define CFG_PLLCR 0x1243E054 |
||||
# define CFG_CLK 140000000 |
||||
#else |
||||
# define CFG_PLLCR 0x135a4140 |
||||
# define CFG_CLK 70000000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
#define CFG_MBAR 0x10000000 /* Register Base Addrs */ |
||||
#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */ |
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0x20000000 |
||||
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ |
||||
|
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM |
||||
# define CFG_MONITOR_BASE 0x20000 |
||||
#else |
||||
# define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN 0x40000 |
||||
#define CFG_MALLOC_LEN (256 << 10) |
||||
#define CFG_BOOTPARAMS_LEN (64*1024) |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization ?? |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) |
||||
|
||||
/* FLASH organization */ |
||||
#define CFG_FLASH_BASE (CFG_CSAR0 << 16) |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ |
||||
#define CFG_FLASH_ERASE_TOUT 1000 |
||||
|
||||
#define FLASH_SST6401B 0x200 |
||||
#define SST_ID_xF6401B 0x236D236D |
||||
|
||||
#undef CFG_FLASH_CFI |
||||
#ifdef CFG_FLASH_CFI |
||||
/*
|
||||
* Unable to use CFI driver, due to incompatible sector erase command by SST. |
||||
* Amd/Atmel use 0x30 for sector erase, SST use 0x50. |
||||
* 0x30 is block erase in SST |
||||
*/ |
||||
# define CFG_FLASH_CFI_DRIVER 1 |
||||
# define CFG_FLASH_SIZE 0x800000 |
||||
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
# define CONFIG_FLASH_CFI_LEGACY |
||||
#else |
||||
# define CFG_SST_SECT 2048 |
||||
# define CFG_SST_SECTSZ 0x1000 |
||||
# define CFG_FLASH_WRITE_TOUT 500 |
||||
#endif |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_CACHELINE_SIZE 16 |
||||
|
||||
/* Port configuration */ |
||||
#define CFG_FECI2C 0xF0 |
||||
|
||||
#define CFG_CSAR0 0xFF80 |
||||
#define CFG_CSMR0 0x007F0021 |
||||
#define CFG_CSCR0 0x1D80 |
||||
|
||||
#define CFG_CSAR1 0xE000 |
||||
#define CFG_CSMR1 0x00000001 |
||||
#define CFG_CSCR1 0x3DD8 |
||||
|
||||
#define CFG_CSAR2 0 |
||||
#define CFG_CSMR2 0 |
||||
#define CFG_CSCR2 0 |
||||
|
||||
#define CFG_CSAR3 0 |
||||
#define CFG_CSMR3 0 |
||||
#define CFG_CSCR3 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Port configuration |
||||
*/ |
||||
#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
||||
#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ |
||||
#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ |
||||
#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ |
||||
#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ |
||||
#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ |
||||
#define CFG_GPIO1_LED 0x00400000 /* user led */ |
||||
|
||||
#endif /* _M5253DEMO_H */ |
Loading…
Reference in new issue