Tom Rini
7 years ago
commit
6f008a2e16
@ -0,0 +1,69 @@ |
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/* |
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* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
||||
* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
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* |
||||
* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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/dts-v1/; |
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#include "sun8i-r40.dtsi" |
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|
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/ { |
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model = "Banana Pi BPI-M2-Ultra"; |
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compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; |
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|
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aliases { |
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serial0 = &uart0; |
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}; |
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|
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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}; |
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|
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&i2c0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c0_pins>; |
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status = "okay"; |
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}; |
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|
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&uart0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&uart0_pb_pins>; |
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status = "okay"; |
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}; |
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@ -0,0 +1,183 @@ |
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/* |
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* Copyright 2016 Chen-Yu Tsai |
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* |
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* Chen-Yu Tsai <wens@csie.org> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
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* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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|
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-parent = <&gic>; |
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|
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aliases { |
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}; |
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|
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chosen { |
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}; |
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|
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clocks { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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|
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osc24M: osc24M_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <24000000>; |
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}; |
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|
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osc32k: osc32k_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <32768>; |
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clock-output-names = "osc32k"; |
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}; |
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}; |
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|
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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cpu0: cpu@0 { |
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compatible = "arm,cortex-a7"; |
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device_type = "cpu"; |
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reg = <0>; |
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}; |
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|
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cpu@1 { |
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compatible = "arm,cortex-a7"; |
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device_type = "cpu"; |
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reg = <1>; |
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}; |
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|
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cpu@2 { |
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compatible = "arm,cortex-a7"; |
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device_type = "cpu"; |
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reg = <2>; |
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}; |
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|
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cpu@3 { |
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compatible = "arm,cortex-a7"; |
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device_type = "cpu"; |
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reg = <3>; |
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}; |
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}; |
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|
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memory@40000000 { |
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device_type = "memory"; |
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reg = <0x40000000 0x80000000>; |
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}; |
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|
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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|
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pio: pinctrl@1c20800 { |
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compatible = "allwinner,sun8i-r40-pinctrl"; |
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reg = <0x01c20800 0x400>; |
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
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/* apb should be replaced once CCU is implemented */ |
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clocks = <&osc24M>, <&osc24M>, <&osc32k>; |
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clock-names = "apb", "hosc", "losc"; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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#gpio-cells = <3>; |
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|
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i2c0_pins: i2c0_pins { |
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pins = "PB0", "PB1"; |
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function = "i2c0"; |
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bias-pull-up; |
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}; |
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|
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uart0_pb_pins: uart0_pb_pins { |
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pins = "PB22", "PB23"; |
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function = "uart0"; |
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bias-pull-up; |
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}; |
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}; |
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|
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uart0: serial@1c28000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x01c28000 0x400>; |
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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clocks = <&osc24M>; |
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status = "disabled"; |
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}; |
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|
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i2c0: i2c@1c2ac00 { |
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compatible = "allwinner,sun6i-a31-i2c"; |
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reg = <0x01c2ac00 0x400>; |
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&osc24M>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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|
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gic: interrupt-controller@1c81000 { |
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
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reg = <0x01c81000 0x1000>, |
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<0x01c82000 0x1000>, |
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<0x01c84000 0x2000>, |
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<0x01c86000 0x2000>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
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}; |
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}; |
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|
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timer { |
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compatible = "arm,armv7-timer"; |
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
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clock-frequency = <24000000>; |
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arm,cpu-registers-not-fw-configured; |
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}; |
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}; |
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@ -0,0 +1,83 @@ |
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/* |
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* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
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* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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/dts-v1/; |
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#include "sun8i-v3s.dtsi" |
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#include "sunxi-common-regulators.dtsi" |
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|
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/ { |
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model = "Lichee Pi Zero"; |
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compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; |
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|
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aliases { |
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serial0 = &uart0; |
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}; |
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|
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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}; |
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|
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&mmc0 { |
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pinctrl-0 = <&mmc0_pins_a>; |
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pinctrl-names = "default"; |
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broken-cd; |
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bus-width = <4>; |
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vmmc-supply = <®_vcc3v3>; |
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status = "okay"; |
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}; |
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|
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&uart0 { |
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pinctrl-0 = <&uart0_pins_a>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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|
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&usb_otg { |
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dr_mode = "otg"; |
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status = "okay"; |
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}; |
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|
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&usbphy { |
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usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; |
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status = "okay"; |
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}; |
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@ -0,0 +1,284 @@ |
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/* |
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* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
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|
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#include <dt-bindings/clock/sun8i-v3s-ccu.h> |
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#include <dt-bindings/reset/sun8i-v3s-ccu.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/pinctrl/sun4i-a10.h> |
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|
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-parent = <&gic>; |
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|
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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cpu@0 { |
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compatible = "arm,cortex-a7"; |
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device_type = "cpu"; |
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reg = <0>; |
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clocks = <&ccu CLK_CPU>; |
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}; |
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}; |
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|
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timer { |
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compatible = "arm,armv7-timer"; |
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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|
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clocks { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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|
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osc24M: osc24M_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <24000000>; |
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clock-output-names = "osc24M"; |
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}; |
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|
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osc32k: osc32k_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <32768>; |
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clock-output-names = "osc32k"; |
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}; |
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}; |
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|
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
||||
#size-cells = <1>; |
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ranges; |
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|
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mmc0: mmc@01c0f000 { |
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compatible = "allwinner,sun7i-a20-mmc"; |
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reg = <0x01c0f000 0x1000>; |
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clocks = <&ccu CLK_BUS_MMC0>, |
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<&ccu CLK_MMC0>, |
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<&ccu CLK_MMC0_OUTPUT>, |
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<&ccu CLK_MMC0_SAMPLE>; |
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clock-names = "ahb", |
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"mmc", |
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"output", |
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"sample"; |
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resets = <&ccu RST_BUS_MMC0>; |
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reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
||||
|
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mmc1: mmc@01c10000 { |
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compatible = "allwinner,sun7i-a20-mmc"; |
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reg = <0x01c10000 0x1000>; |
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clocks = <&ccu CLK_BUS_MMC1>, |
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<&ccu CLK_MMC1>, |
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<&ccu CLK_MMC1_OUTPUT>, |
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<&ccu CLK_MMC1_SAMPLE>; |
||||
clock-names = "ahb", |
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"mmc", |
||||
"output", |
||||
"sample"; |
||||
resets = <&ccu RST_BUS_MMC1>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
mmc2: mmc@01c11000 { |
||||
compatible = "allwinner,sun7i-a20-mmc"; |
||||
reg = <0x01c11000 0x1000>; |
||||
clocks = <&ccu CLK_BUS_MMC2>, |
||||
<&ccu CLK_MMC2>, |
||||
<&ccu CLK_MMC2_OUTPUT>, |
||||
<&ccu CLK_MMC2_SAMPLE>; |
||||
clock-names = "ahb", |
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"mmc", |
||||
"output", |
||||
"sample"; |
||||
resets = <&ccu RST_BUS_MMC2>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
usb_otg: usb@01c19000 { |
||||
compatible = "allwinner,sun8i-h3-musb"; |
||||
reg = <0x01c19000 0x0400>; |
||||
clocks = <&ccu CLK_BUS_OTG>; |
||||
resets = <&ccu RST_BUS_OTG>; |
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
||||
interrupt-names = "mc"; |
||||
phys = <&usbphy 0>; |
||||
phy-names = "usb"; |
||||
extcon = <&usbphy 0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
usbphy: phy@01c19400 { |
||||
compatible = "allwinner,sun8i-v3s-usb-phy"; |
||||
reg = <0x01c19400 0x2c>, |
||||
<0x01c1a800 0x4>; |
||||
reg-names = "phy_ctrl", |
||||
"pmu0"; |
||||
clocks = <&ccu CLK_USB_PHY0>; |
||||
clock-names = "usb0_phy"; |
||||
resets = <&ccu RST_USB_PHY0>; |
||||
reset-names = "usb0_reset"; |
||||
status = "disabled"; |
||||
#phy-cells = <1>; |
||||
}; |
||||
|
||||
ccu: clock@01c20000 { |
||||
compatible = "allwinner,sun8i-v3s-ccu"; |
||||
reg = <0x01c20000 0x400>; |
||||
clocks = <&osc24M>, <&osc32k>; |
||||
clock-names = "hosc", "losc"; |
||||
#clock-cells = <1>; |
||||
#reset-cells = <1>; |
||||
}; |
||||
|
||||
rtc: rtc@01c20400 { |
||||
compatible = "allwinner,sun6i-a31-rtc"; |
||||
reg = <0x01c20400 0x54>; |
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
||||
}; |
||||
|
||||
pio: pinctrl@01c20800 { |
||||
compatible = "allwinner,sun8i-v3s-pinctrl"; |
||||
reg = <0x01c20800 0x400>; |
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; |
||||
clock-names = "apb", "hosc", "losc"; |
||||
gpio-controller; |
||||
#gpio-cells = <3>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
|
||||
uart0_pins_a: uart0@0 { |
||||
pins = "PB8", "PB9"; |
||||
function = "uart0"; |
||||
bias-pull-up; |
||||
}; |
||||
|
||||
mmc0_pins_a: mmc0@0 { |
||||
pins = "PF0", "PF1", "PF2", "PF3", |
||||
"PF4", "PF5"; |
||||
function = "mmc0"; |
||||
drive-strength = <30>; |
||||
bias-pull-up; |
||||
}; |
||||
}; |
||||
|
||||
timer@01c20c00 { |
||||
compatible = "allwinner,sun4i-a10-timer"; |
||||
reg = <0x01c20c00 0xa0>; |
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&osc24M>; |
||||
}; |
||||
|
||||
wdt0: watchdog@01c20ca0 { |
||||
compatible = "allwinner,sun6i-a31-wdt"; |
||||
reg = <0x01c20ca0 0x20>; |
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
||||
}; |
||||
|
||||
uart0: serial@01c28000 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28000 0x400>; |
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART0>; |
||||
resets = <&ccu RST_BUS_UART0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart1: serial@01c28400 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28400 0x400>; |
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART1>; |
||||
resets = <&ccu RST_BUS_UART1>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart2: serial@01c28800 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28800 0x400>; |
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART2>; |
||||
resets = <&ccu RST_BUS_UART2>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
gic: interrupt-controller@01c81000 { |
||||
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
||||
reg = <0x01c81000 0x1000>, |
||||
<0x01c82000 0x1000>, |
||||
<0x01c84000 0x2000>, |
||||
<0x01c86000 0x2000>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,128 @@ |
||||
/*
|
||||
* Sunxi platform timing controller register and constant defines |
||||
* |
||||
* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> |
||||
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _LCDC_H |
||||
#define _LCDC_H |
||||
|
||||
#include <fdtdec.h> |
||||
|
||||
struct sunxi_lcdc_reg { |
||||
u32 ctrl; /* 0x00 */ |
||||
u32 int0; /* 0x04 */ |
||||
u32 int1; /* 0x08 */ |
||||
u8 res0[0x04]; /* 0x0c */ |
||||
u32 tcon0_frm_ctrl; /* 0x10 */ |
||||
u32 tcon0_frm_seed[6]; /* 0x14 */ |
||||
u32 tcon0_frm_table[4]; /* 0x2c */ |
||||
u8 res1[4]; /* 0x3c */ |
||||
u32 tcon0_ctrl; /* 0x40 */ |
||||
u32 tcon0_dclk; /* 0x44 */ |
||||
u32 tcon0_timing_active; /* 0x48 */ |
||||
u32 tcon0_timing_h; /* 0x4c */ |
||||
u32 tcon0_timing_v; /* 0x50 */ |
||||
u32 tcon0_timing_sync; /* 0x54 */ |
||||
u32 tcon0_hv_intf; /* 0x58 */ |
||||
u8 res2[0x04]; /* 0x5c */ |
||||
u32 tcon0_cpu_intf; /* 0x60 */ |
||||
u32 tcon0_cpu_wr_dat; /* 0x64 */ |
||||
u32 tcon0_cpu_rd_dat0; /* 0x68 */ |
||||
u32 tcon0_cpu_rd_dat1; /* 0x6c */ |
||||
u32 tcon0_ttl_timing0; /* 0x70 */ |
||||
u32 tcon0_ttl_timing1; /* 0x74 */ |
||||
u32 tcon0_ttl_timing2; /* 0x78 */ |
||||
u32 tcon0_ttl_timing3; /* 0x7c */ |
||||
u32 tcon0_ttl_timing4; /* 0x80 */ |
||||
u32 tcon0_lvds_intf; /* 0x84 */ |
||||
u32 tcon0_io_polarity; /* 0x88 */ |
||||
u32 tcon0_io_tristate; /* 0x8c */ |
||||
u32 tcon1_ctrl; /* 0x90 */ |
||||
u32 tcon1_timing_source; /* 0x94 */ |
||||
u32 tcon1_timing_scale; /* 0x98 */ |
||||
u32 tcon1_timing_out; /* 0x9c */ |
||||
u32 tcon1_timing_h; /* 0xa0 */ |
||||
u32 tcon1_timing_v; /* 0xa4 */ |
||||
u32 tcon1_timing_sync; /* 0xa8 */ |
||||
u8 res3[0x44]; /* 0xac */ |
||||
u32 tcon1_io_polarity; /* 0xf0 */ |
||||
u32 tcon1_io_tristate; /* 0xf4 */ |
||||
u8 res4[0x108]; /* 0xf8 */ |
||||
u32 mux_ctrl; /* 0x200 */ |
||||
u8 res5[0x1c]; /* 0x204 */ |
||||
u32 lvds_ana0; /* 0x220 */ |
||||
u32 lvds_ana1; /* 0x224 */ |
||||
}; |
||||
|
||||
/*
|
||||
* LCDC register constants. |
||||
*/ |
||||
#define SUNXI_LCDC_X(x) (((x) - 1) << 16) |
||||
#define SUNXI_LCDC_Y(y) (((y) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) |
||||
#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) |
||||
#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) |
||||
#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) |
||||
#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) |
||||
#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) |
||||
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) |
||||
#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 |
||||
#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) |
||||
#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) |
||||
#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) |
||||
#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) |
||||
#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) |
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I |
||||
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) |
||||
#else |
||||
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ |
||||
#endif |
||||
#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) |
||||
#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) |
||||
#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) |
||||
#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20) |
||||
#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) |
||||
#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) |
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I |
||||
#define SUNXI_LCDC_LVDS_ANA0 0x40040320 |
||||
#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) |
||||
#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) |
||||
#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) |
||||
#else |
||||
#define SUNXI_LCDC_LVDS_ANA0 0x3f310000 |
||||
#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) |
||||
#endif |
||||
#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) |
||||
#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) |
||||
|
||||
void lcdc_init(struct sunxi_lcdc_reg * const lcdc); |
||||
void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth); |
||||
void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct display_timing *mode, |
||||
int clk_div, bool for_ext_vga_dac, |
||||
int depth, int dclk_phase); |
||||
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct display_timing *mode, |
||||
bool ext_hvsync, bool is_composite); |
||||
|
||||
#endif /* _LCDC_H */ |
||||
@ -0,0 +1,15 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_SUNXI=y |
||||
CONFIG_MACH_SUN8I_R40=y |
||||
CONFIG_DRAM_CLK=576 |
||||
CONFIG_DRAM_ZQ=3881979 |
||||
CONFIG_DRAM_ODT_EN=y |
||||
CONFIG_MMC0_CD_PIN="PH13" |
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2 |
||||
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra" |
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_I2C_SUPPORT=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
@ -0,0 +1,12 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_SUNXI=y |
||||
CONFIG_MACH_SUN8I_V3S=y |
||||
CONFIG_DRAM_CLK=360 |
||||
CONFIG_DRAM_ZQ=14779 |
||||
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero" |
||||
# CONFIG_CONSOLE_MUX is not set |
||||
CONFIG_SPL=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
# CONFIG_NETDEVICES is not set |
||||
@ -0,0 +1,8 @@ |
||||
#
|
||||
# (C) Copyright 2000-2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o ../videomodes.o
|
||||
@ -0,0 +1,209 @@ |
||||
/*
|
||||
* Timing controller driver for Allwinner SoCs. |
||||
* |
||||
* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be> |
||||
* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> |
||||
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#include <asm/arch/lcdc.h> |
||||
#include <asm/io.h> |
||||
|
||||
static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon) |
||||
{ |
||||
int delay; |
||||
|
||||
delay = mode->vfront_porch.typ + mode->vsync_len.typ + |
||||
mode->vback_porch.typ; |
||||
if (mode->flags & DISPLAY_FLAGS_INTERLACED) |
||||
delay /= 2; |
||||
if (tcon == 1) |
||||
delay -= 2; |
||||
|
||||
return (delay > 30) ? 30 : delay; |
||||
} |
||||
|
||||
void lcdc_init(struct sunxi_lcdc_reg * const lcdc) |
||||
{ |
||||
/* Init lcdc */ |
||||
writel(0, &lcdc->ctrl); /* Disable tcon */ |
||||
writel(0, &lcdc->int0); /* Disable all interrupts */ |
||||
|
||||
/* Disable tcon0 dot clock */ |
||||
clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE); |
||||
|
||||
/* Set all io lines to tristate */ |
||||
writel(0xffffffff, &lcdc->tcon0_io_tristate); |
||||
writel(0xffffffff, &lcdc->tcon1_io_tristate); |
||||
} |
||||
|
||||
void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth) |
||||
{ |
||||
setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); |
||||
#ifdef CONFIG_VIDEO_LCD_IF_LVDS |
||||
setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE); |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); |
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I |
||||
udelay(2); /* delay at least 1200 ns */ |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB); |
||||
udelay(2); /* delay at least 1200 ns */ |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC); |
||||
if (depth == 18) |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7)); |
||||
else |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf)); |
||||
#else |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); |
||||
udelay(2); /* delay at least 1200 ns */ |
||||
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1); |
||||
udelay(1); /* delay at least 120 ns */ |
||||
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2); |
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); |
||||
#endif |
||||
#endif |
||||
} |
||||
|
||||
void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct display_timing *mode, |
||||
int clk_div, bool for_ext_vga_dac, |
||||
int depth, int dclk_phase) |
||||
{ |
||||
int bp, clk_delay, total, val; |
||||
|
||||
#ifndef CONFIG_SUNXI_DE2 |
||||
/* Use tcon0 */ |
||||
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, |
||||
SUNXI_LCDC_CTRL_IO_MAP_TCON0); |
||||
#endif |
||||
|
||||
clk_delay = lcdc_get_clk_delay(mode, 0); |
||||
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE | |
||||
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl); |
||||
|
||||
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE | |
||||
SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk); |
||||
|
||||
writel(SUNXI_LCDC_X(mode->hactive.typ) | |
||||
SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active); |
||||
|
||||
bp = mode->hsync_len.typ + mode->hback_porch.typ; |
||||
total = mode->hactive.typ + mode->hfront_porch.typ + bp; |
||||
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) | |
||||
SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h); |
||||
|
||||
bp = mode->vsync_len.typ + mode->vback_porch.typ; |
||||
total = mode->vactive.typ + mode->vfront_porch.typ + bp; |
||||
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) | |
||||
SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v); |
||||
|
||||
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL |
||||
writel(SUNXI_LCDC_X(mode->hsync_len.typ) | |
||||
SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync); |
||||
|
||||
writel(0, &lcdc->tcon0_hv_intf); |
||||
writel(0, &lcdc->tcon0_cpu_intf); |
||||
#endif |
||||
#ifdef CONFIG_VIDEO_LCD_IF_LVDS |
||||
val = (depth == 18) ? 1 : 0; |
||||
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) | |
||||
SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf); |
||||
#endif |
||||
|
||||
if (depth == 18 || depth == 16) { |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]); |
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]); |
||||
writel(((depth == 18) ? |
||||
SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 : |
||||
SUNXI_LCDC_TCON0_FRM_CTRL_RGB565), |
||||
&lcdc->tcon0_frm_ctrl); |
||||
} |
||||
|
||||
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase); |
||||
if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW) |
||||
val |= SUNXI_LCDC_TCON_HSYNC_MASK; |
||||
if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW) |
||||
val |= SUNXI_LCDC_TCON_VSYNC_MASK; |
||||
|
||||
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
||||
if (for_ext_vga_dac) |
||||
val = 0; |
||||
#endif |
||||
writel(val, &lcdc->tcon0_io_polarity); |
||||
|
||||
writel(0, &lcdc->tcon0_io_tristate); |
||||
} |
||||
|
||||
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct display_timing *mode, |
||||
bool ext_hvsync, bool is_composite) |
||||
{ |
||||
int bp, clk_delay, total, val, yres; |
||||
|
||||
#ifndef CONFIG_SUNXI_DE2 |
||||
/* Use tcon1 */ |
||||
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, |
||||
SUNXI_LCDC_CTRL_IO_MAP_TCON1); |
||||
#endif |
||||
|
||||
clk_delay = lcdc_get_clk_delay(mode, 1); |
||||
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE | |
||||
((mode->flags & DISPLAY_FLAGS_INTERLACED) ? |
||||
SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) | |
||||
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl); |
||||
|
||||
yres = mode->vactive.typ; |
||||
if (mode->flags & DISPLAY_FLAGS_INTERLACED) |
||||
yres /= 2; |
||||
writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres), |
||||
&lcdc->tcon1_timing_source); |
||||
writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres), |
||||
&lcdc->tcon1_timing_scale); |
||||
writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres), |
||||
&lcdc->tcon1_timing_out); |
||||
|
||||
bp = mode->hsync_len.typ + mode->hback_porch.typ; |
||||
total = mode->hactive.typ + mode->hfront_porch.typ + bp; |
||||
writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) | |
||||
SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h); |
||||
|
||||
bp = mode->vsync_len.typ + mode->vback_porch.typ; |
||||
total = mode->vactive.typ + mode->vfront_porch.typ + bp; |
||||
if (!(mode->flags & DISPLAY_FLAGS_INTERLACED)) |
||||
total *= 2; |
||||
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) | |
||||
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v); |
||||
|
||||
writel(SUNXI_LCDC_X(mode->hsync_len.typ) | |
||||
SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon1_timing_sync); |
||||
|
||||
if (ext_hvsync) { |
||||
val = 0; |
||||
if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH) |
||||
val |= SUNXI_LCDC_TCON_HSYNC_MASK; |
||||
if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH) |
||||
val |= SUNXI_LCDC_TCON_VSYNC_MASK; |
||||
writel(val, &lcdc->tcon1_io_polarity); |
||||
|
||||
clrbits_le32(&lcdc->tcon1_io_tristate, |
||||
SUNXI_LCDC_TCON_VSYNC_MASK | |
||||
SUNXI_LCDC_TCON_HSYNC_MASK); |
||||
} |
||||
|
||||
#ifdef CONFIG_MACH_SUN5I |
||||
if (is_composite) |
||||
clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK, |
||||
SUNXI_LCDC_MUX_CTRL_SRC0(1)); |
||||
#endif |
||||
} |
||||
@ -0,0 +1,107 @@ |
||||
/*
|
||||
* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
||||
* |
||||
* Based on sun8i-h3-ccu.h, which is: |
||||
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ |
||||
#define _DT_BINDINGS_CLK_SUN8I_V3S_H_ |
||||
|
||||
#define CLK_CPU 14 |
||||
|
||||
#define CLK_BUS_CE 20 |
||||
#define CLK_BUS_DMA 21 |
||||
#define CLK_BUS_MMC0 22 |
||||
#define CLK_BUS_MMC1 23 |
||||
#define CLK_BUS_MMC2 24 |
||||
#define CLK_BUS_DRAM 25 |
||||
#define CLK_BUS_EMAC 26 |
||||
#define CLK_BUS_HSTIMER 27 |
||||
#define CLK_BUS_SPI0 28 |
||||
#define CLK_BUS_OTG 29 |
||||
#define CLK_BUS_EHCI0 30 |
||||
#define CLK_BUS_OHCI0 31 |
||||
#define CLK_BUS_VE 32 |
||||
#define CLK_BUS_TCON0 33 |
||||
#define CLK_BUS_CSI 34 |
||||
#define CLK_BUS_DE 35 |
||||
#define CLK_BUS_CODEC 36 |
||||
#define CLK_BUS_PIO 37 |
||||
#define CLK_BUS_I2C0 38 |
||||
#define CLK_BUS_I2C1 39 |
||||
#define CLK_BUS_UART0 40 |
||||
#define CLK_BUS_UART1 41 |
||||
#define CLK_BUS_UART2 42 |
||||
#define CLK_BUS_EPHY 43 |
||||
#define CLK_BUS_DBG 44 |
||||
|
||||
#define CLK_MMC0 45 |
||||
#define CLK_MMC0_SAMPLE 46 |
||||
#define CLK_MMC0_OUTPUT 47 |
||||
#define CLK_MMC1 48 |
||||
#define CLK_MMC1_SAMPLE 49 |
||||
#define CLK_MMC1_OUTPUT 50 |
||||
#define CLK_MMC2 51 |
||||
#define CLK_MMC2_SAMPLE 52 |
||||
#define CLK_MMC2_OUTPUT 53 |
||||
#define CLK_CE 54 |
||||
#define CLK_SPI0 55 |
||||
#define CLK_USB_PHY0 56 |
||||
#define CLK_USB_OHCI0 57 |
||||
|
||||
#define CLK_DRAM_VE 59 |
||||
#define CLK_DRAM_CSI 60 |
||||
#define CLK_DRAM_EHCI 61 |
||||
#define CLK_DRAM_OHCI 62 |
||||
#define CLK_DE 63 |
||||
#define CLK_TCON0 64 |
||||
#define CLK_CSI_MISC 65 |
||||
#define CLK_CSI0_MCLK 66 |
||||
#define CLK_CSI1_SCLK 67 |
||||
#define CLK_CSI1_MCLK 68 |
||||
#define CLK_VE 69 |
||||
#define CLK_AC_DIG 70 |
||||
#define CLK_AVS 71 |
||||
|
||||
#define CLK_MIPI_CSI 73 |
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ |
||||
@ -0,0 +1,78 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
||||
* |
||||
* Based on sun8i-v3s-ccu.h, which is |
||||
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_ |
||||
#define _DT_BINDINGS_RST_SUN8I_V3S_H_ |
||||
|
||||
#define RST_USB_PHY0 0 |
||||
|
||||
#define RST_MBUS 1 |
||||
|
||||
#define RST_BUS_CE 5 |
||||
#define RST_BUS_DMA 6 |
||||
#define RST_BUS_MMC0 7 |
||||
#define RST_BUS_MMC1 8 |
||||
#define RST_BUS_MMC2 9 |
||||
#define RST_BUS_DRAM 11 |
||||
#define RST_BUS_EMAC 12 |
||||
#define RST_BUS_HSTIMER 14 |
||||
#define RST_BUS_SPI0 15 |
||||
#define RST_BUS_OTG 17 |
||||
#define RST_BUS_EHCI0 18 |
||||
#define RST_BUS_OHCI0 22 |
||||
#define RST_BUS_VE 26 |
||||
#define RST_BUS_TCON0 27 |
||||
#define RST_BUS_CSI 30 |
||||
#define RST_BUS_DE 34 |
||||
#define RST_BUS_DBG 38 |
||||
#define RST_BUS_EPHY 39 |
||||
#define RST_BUS_CODEC 40 |
||||
#define RST_BUS_I2C0 46 |
||||
#define RST_BUS_I2C1 47 |
||||
#define RST_BUS_UART0 49 |
||||
#define RST_BUS_UART1 50 |
||||
#define RST_BUS_UART2 51 |
||||
|
||||
#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ |
||||
Loading…
Reference in new issue