Tom Rini
9 years ago
commit
6f4e050639
@ -0,0 +1,22 @@ |
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/*
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* Copyright 2015 Broadcom Corporation. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __BCM_UDC_OTG_H |
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#define __BCM_UDC_OTG_H |
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#include <common.h> |
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static inline void wfld_set(uintptr_t addr, uint32_t fld_val, uint32_t fld_mask) |
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{ |
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writel(((readl(addr) & ~(fld_mask)) | (fld_val)), (addr)); |
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} |
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static inline void wfld_clear(uintptr_t addr, uint32_t fld_mask) |
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{ |
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writel((readl(addr) & ~(fld_mask)), (addr)); |
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} |
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#endif |
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@ -0,0 +1,51 @@ |
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/*
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* Copyright 2015 Broadcom Corporation. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/sysmap.h> |
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#include <usb/s3c_udc.h> |
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#include "bcm_udc_otg.h" |
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void otg_phy_init(struct s3c_udc *dev) |
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{ |
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/* set Phy to driving mode */ |
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wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, |
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HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); |
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udelay(100); |
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/* clear Soft Disconnect */ |
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wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, |
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HSOTG_DCTL_SFTDISCON_MASK); |
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/* invoke Reset (active low) */ |
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wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, |
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HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); |
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/* Reset needs to be asserted for 2ms */ |
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udelay(2000); |
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/* release Reset */ |
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wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, |
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HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK, |
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HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); |
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} |
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void otg_phy_off(struct s3c_udc *dev) |
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{ |
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/* Soft Disconnect */ |
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wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, |
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HSOTG_DCTL_SFTDISCON_MASK, |
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HSOTG_DCTL_SFTDISCON_MASK); |
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/* set Phy to non-driving (reset) mode */ |
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wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, |
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HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK, |
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HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); |
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} |
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@ -0,0 +1,97 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* DWC3 controller driver |
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* |
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* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <linux/usb/dwc3.h> |
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void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) |
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{ |
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clrsetbits_le32(&dwc3_reg->g_ctl, |
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DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), |
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DWC3_GCTL_PRTCAPDIR(mode)); |
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} |
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void dwc3_phy_reset(struct dwc3 *dwc3_reg) |
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{ |
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/* Assert USB3 PHY reset */ |
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setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); |
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/* Assert USB2 PHY reset */ |
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setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); |
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mdelay(100); |
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/* Clear USB3 PHY reset */ |
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clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); |
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/* Clear USB2 PHY reset */ |
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clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); |
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} |
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void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) |
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{ |
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/* Before Resetting PHY, put Core in Reset */ |
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setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); |
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/* reset USB3 phy - if required */ |
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dwc3_phy_reset(dwc3_reg); |
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/* After PHYs are stable we can take Core out of reset state */ |
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clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); |
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} |
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int dwc3_core_init(struct dwc3 *dwc3_reg) |
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{ |
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u32 reg; |
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u32 revision; |
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unsigned int dwc3_hwparams1; |
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revision = readl(&dwc3_reg->g_snpsid); |
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/* This should read as U3 followed by revision number */ |
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if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { |
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puts("this is not a DesignWare USB3 DRD Core\n"); |
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return -1; |
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} |
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dwc3_core_soft_reset(dwc3_reg); |
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dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); |
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reg = readl(&dwc3_reg->g_ctl); |
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reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
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reg &= ~DWC3_GCTL_DISSCRAMBLE; |
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switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { |
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case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
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reg &= ~DWC3_GCTL_DSBLCLKGTNG; |
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break; |
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default: |
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debug("No power optimization available\n"); |
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} |
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/*
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* WORKAROUND: DWC3 revisions <1.90a have a bug |
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* where the device can fail to connect at SuperSpeed |
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* and falls back to high-speed mode which causes |
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* the device to enter a Connect/Disconnect loop |
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*/ |
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if ((revision & DWC3_REVISION_MASK) < 0x190a) |
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reg |= DWC3_GCTL_U2RSTECN; |
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writel(reg, &dwc3_reg->g_ctl); |
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return 0; |
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} |
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void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) |
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{ |
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setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | |
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GFLADJ_30MHZ(val)); |
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} |
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@ -0,0 +1,111 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* FSL USB HOST xHCI Controller |
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* |
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* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <usb.h> |
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#include <asm-generic/errno.h> |
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#include <linux/compat.h> |
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#include <linux/usb/xhci-fsl.h> |
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#include <linux/usb/dwc3.h> |
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#include "xhci.h" |
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/* Declare global data pointer */ |
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DECLARE_GLOBAL_DATA_PTR; |
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static struct fsl_xhci fsl_xhci; |
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unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR; |
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__weak int __board_usb_init(int index, enum usb_init_type init) |
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{ |
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return 0; |
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} |
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void usb_phy_reset(struct dwc3 *dwc3_reg) |
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{ |
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/* Assert USB3 PHY reset */ |
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setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); |
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/* Assert USB2 PHY reset */ |
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setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); |
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mdelay(200); |
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/* Clear USB3 PHY reset */ |
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clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); |
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/* Clear USB2 PHY reset */ |
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clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); |
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} |
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static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) |
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{ |
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int ret = 0; |
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ret = dwc3_core_init(fsl_xhci->dwc3_reg); |
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if (ret) { |
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debug("%s:failed to initialize core\n", __func__); |
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return ret; |
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} |
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/* We are hard-coding DWC3 core to Host Mode */ |
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dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); |
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/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */ |
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dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT); |
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return ret; |
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} |
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static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) |
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{ |
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/*
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* Currently fsl socs do not support PHY shutdown from |
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* sw. But this support may be added in future socs. |
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*/ |
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return 0; |
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} |
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) |
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{ |
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struct fsl_xhci *ctx = &fsl_xhci; |
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int ret = 0; |
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ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; |
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); |
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ret = board_usb_init(index, USB_INIT_HOST); |
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if (ret != 0) { |
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puts("Failed to initialize board for USB\n"); |
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return ret; |
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} |
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ret = fsl_xhci_core_init(ctx); |
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if (ret < 0) { |
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puts("Failed to initialize xhci\n"); |
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return ret; |
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} |
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*hccr = (struct xhci_hccr *)ctx->hcd; |
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*hcor = (struct xhci_hcor *)((uintptr_t) *hccr |
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+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); |
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debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n", |
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(uintptr_t)*hccr, (uintptr_t)*hcor, |
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(uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); |
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return ret; |
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} |
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void xhci_hcd_stop(int index) |
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{ |
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struct fsl_xhci *ctx = &fsl_xhci; |
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fsl_xhci_core_exit(ctx); |
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} |
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@ -0,0 +1,64 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* FSL USB HOST xHCI Controller |
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* |
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* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_XHCI_FSL_H_ |
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#define _ASM_ARCH_XHCI_FSL_H_ |
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/* Default to the FSL XHCI defines */ |
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#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 |
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#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC |
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#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) |
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#define USB3_PHY_RX_POWERON BIT(14) |
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#define USB3_PHY_TX_POWERON BIT(15) |
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#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) |
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#define USB3_PWRCTL_CLK_CMD_SHIFT 14 |
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#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 |
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/* USBOTGSS_WRAPPER definitions */ |
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#define USBOTGSS_WRAPRESET BIT(17) |
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#define USBOTGSS_DMADISABLE BIT(16) |
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#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) |
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#define USBOTGSS_STANDBYMODE_SMRT BIT(5) |
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#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) |
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#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) |
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#define USBOTGSS_IDLEMODE_SMRT BIT(3) |
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#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) |
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/* USBOTGSS_IRQENABLE_SET_0 bit */ |
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#define USBOTGSS_COREIRQ_EN BIT(1) |
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/* USBOTGSS_IRQENABLE_SET_1 bits */ |
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) |
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) |
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) |
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) |
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) |
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) |
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) |
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) |
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#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) |
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#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) |
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struct fsl_xhci { |
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struct xhci_hccr *hcd; |
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struct dwc3 *dwc3_reg; |
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}; |
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#if defined(CONFIG_LS102XA) |
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#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR |
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#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 |
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#elif defined(CONFIG_LS2085A) |
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#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR |
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#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR |
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#endif |
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#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ |
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CONFIG_SYS_FSL_XHCI_USB2_ADDR} |
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#endif /* _ASM_ARCH_XHCI_FSL_H_ */ |
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