The '#' used as comments in the files cause the preprocessor trouble, so change to /* */. The mkimage command which uses this preprocessor output was moved to arch/arm/imx-common/Makefile .gitignore was updated to ignore .cfgtmp files. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>master
Troy Kisky
11 years ago
committed by
Stefano Babic
parent
0023997709
commit
71a988aa63
@ -1,209 +1,228 @@ |
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# |
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# (C) Copyright 2009 |
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# Stefano Babic DENX Software Engineering sbabic@denx.de. |
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# |
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# (C) Copyright 2010 |
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# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com |
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# |
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# See file CREDITS for list of people who contributed to this |
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# project. |
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# |
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# This program is free software; you can redistribute it and/or |
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# modify it under the terms of the GNU General Public License as |
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# published by the Free Software Foundation; either version 2 of |
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# the License or (at your option) any later version. |
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# |
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# This program is distributed in the hope that it will be useful, |
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# but WITHOUT ANY WARRANTY; without even the implied warranty of |
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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# GNU General Public License for more details. |
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# |
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# You should have received a copy of the GNU General Public License |
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# along with this program; if not write to the Free Software |
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# Foundation Inc. 51 Franklin Street Fifth Floor Boston, |
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# MA 02110-1301 USA |
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# |
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# Refer docs/README.imxmage for more details about how-to configure |
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# and create imximage boot image |
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# |
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# The syntax is taken as close as possible with the kwbimage |
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|
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# Boot Device : one of |
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# spi, nand, onenand, sd |
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|
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/* |
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* (C) Copyright 2009 |
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* Stefano Babic DENX Software Engineering sbabic@denx.de. |
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* |
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* (C) Copyright 2010 |
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* Klaus Steinhammer TTECH Control Gmbh kst@tttech.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not write to the Free Software |
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* Foundation Inc. 51 Franklin Street Fifth Floor Boston, |
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* MA 02110-1301 USA |
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* |
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* Refer docs/README.imxmage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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|
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/* |
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* Boot Device : one of |
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* spi, nand, onenand, sd |
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*/ |
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BOOT_FROM spi |
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|
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# Device Configuration Data (DCD) |
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# |
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# Each entry must have the format: |
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# Addr-type Address Value |
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# |
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# where: |
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# Addr-type register length (1,2 or 4 bytes) |
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# Address absolute address of the register |
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# value value to be stored in the register |
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|
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####################### |
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### Disable WDOG ### |
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####################### |
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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|
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/* |
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* ####################### |
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* ### Disable WDOG ### |
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* ####################### |
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*/ |
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DATA 2 0x73f98000 0x30 |
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|
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####################### |
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### SET DDR Clk ### |
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####################### |
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|
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# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) |
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/* |
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* ####################### |
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* ### SET DDR Clk ### |
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* ####################### |
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*/ |
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/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */ |
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DATA 4 0x73FD4018 0x000024C0 |
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|
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# DOUBLE SPI CLK (13MHz->26 MHz Clock) |
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/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */ |
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DATA 4 0x73FD4038 0x2010241 |
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|
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#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa8600 0x00000107 |
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#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa8604 0x00000107 |
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#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa8608 0x00000187 |
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#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa860c 0x00000187 |
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#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST |
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/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */ |
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DATA 4 0x73fa8614 0x00000107 |
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#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) |
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/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */ |
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DATA 4 0x73fa86a8 0x00000187 |
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|
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####################### |
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### Settings IOMUXC ### |
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####################### |
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# DDR IOMUX configuration |
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# Control, Data, Address pads are in their default state: HIGH DS, FAST SR. |
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# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS |
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/* |
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* ####################### |
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* ### Settings IOMUXC ### |
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* ####################### |
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*/ |
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/* |
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* DDR IOMUX configuration |
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* Control, Data, Address pads are in their default state: HIGH DS, FAST SR. |
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* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS |
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*/ |
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DATA 4 0x73fa84b8 0x000000e7 |
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# PVTC MAX (at GPC, PGR reg) |
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#DATA 4 0x73FD8004 0x1fc00000 |
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/* PVTC MAX (at GPC, PGR reg) */ |
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/* DATA 4 0x73FD8004 0x1fc00000 */ |
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|
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#DQM0 DS high slew rate slow |
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/* DQM0 DS high slew rate slow */ |
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DATA 4 0x73fa84d4 0x000000e4 |
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#DQM1 DS high slew rate slow |
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/* DQM1 DS high slew rate slow */ |
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DATA 4 0x73fa84d8 0x000000e4 |
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#DQM2 DS high slew rate slow |
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/* DQM2 DS high slew rate slow */ |
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DATA 4 0x73fa84dc 0x000000e4 |
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#DQM3 DS high slew rate slow |
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/* DQM3 DS high slew rate slow */ |
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DATA 4 0x73fa84e0 0x000000e4 |
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|
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#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow |
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */ |
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DATA 4 0x73fa84bc 0x000000c4 |
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#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow |
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */ |
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DATA 4 0x73fa84c0 0x000000c4 |
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#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow |
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */ |
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DATA 4 0x73fa84c4 0x000000c4 |
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#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow |
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */ |
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DATA 4 0x73fa84c8 0x000000c4 |
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#DRAM_DATA B0 |
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/* DRAM_DATA B0 */ |
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DATA 4 0x73fa88a4 0x00000004 |
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#DRAM_DATA B1 |
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/* DRAM_DATA B1 */ |
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DATA 4 0x73fa88ac 0x00000004 |
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#DRAM_DATA B2 |
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/* DRAM_DATA B2 */ |
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DATA 4 0x73fa88b8 0x00000004 |
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#DRAM_DATA B3 |
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/* DRAM_DATA B3 */ |
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DATA 4 0x73fa882c 0x00000004 |
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|
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#DRAM_DATA B0 slew rate |
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/* DRAM_DATA B0 slew rate */ |
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DATA 4 0x73fa8878 0x00000000 |
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#DRAM_DATA B1 slew rate |
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/* DRAM_DATA B1 slew rate */ |
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DATA 4 0x73fa8880 0x00000000 |
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#DRAM_DATA B2 slew rate |
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/* DRAM_DATA B2 slew rate */ |
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DATA 4 0x73fa888c 0x00000000 |
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#DRAM_DATA B3 slew rate |
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/* DRAM_DATA B3 slew rate */ |
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DATA 4 0x73fa889c 0x00000000 |
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|
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####################### |
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### Configure SDRAM ### |
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####################### |
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/* |
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* ####################### |
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* ### Configure SDRAM ### |
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* ####################### |
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*/ |
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|
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# Configure CS0 |
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####################### |
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/* Configure CS0 */ |
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/* ####################### */ |
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|
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# ESDCTL0: Enable controller |
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/* ESDCTL0: Enable controller */ |
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DATA 4 0x83fd9000 0x83220000 |
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# Init DRAM on CS0 |
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# ESDSCR: Precharge command |
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/* Init DRAM on CS0 / |
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/* ESDSCR: Precharge command */ |
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DATA 4 0x83fd9014 0x04008008 |
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# ESDSCR: Refresh command |
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/* ESDSCR: Refresh command */ |
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DATA 4 0x83fd9014 0x00008010 |
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# ESDSCR: Refresh command |
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/* ESDSCR: Refresh command */ |
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DATA 4 0x83fd9014 0x00008010 |
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# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) |
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/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */ |
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DATA 4 0x83fd9014 0x00338018 |
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# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) |
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/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */ |
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DATA 4 0x83fd9014 0x0020801a |
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# ESDSCR |
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/* ESDSCR */ |
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DATA 4 0x83fd9014 0x00008000 |
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# ESDSCR: EMR with full Drive strength |
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#DATA 4 0x83fd9014 0x0000801a |
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/* ESDSCR: EMR with full Drive strength */ |
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/* DATA 4 0x83fd9014 0x0000801a */ |
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# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 |
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/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */ |
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DATA 4 0x83fd9000 0xC3220000 |
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|
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# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks |
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#DATA 4 0x83fd9004 0xC33574AA |
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#micron mDDR |
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# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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#DATA 4 0x83FD9004 0x101564a8 |
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#hynix mDDR |
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# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks |
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# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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/* |
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* ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks |
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* DATA 4 0x83fd9004 0xC33574AA |
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*/ |
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/* |
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* micron mDDR |
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* ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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* DATA 4 0x83FD9004 0x101564a8 |
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*/ |
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/* |
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* hynix mDDR |
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* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks |
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* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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*/ |
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DATA 4 0x83FD9004 0x704564a8 |
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# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 |
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/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */ |
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DATA 4 0x83fd9010 0x000a1700 |
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# Configure CS1 |
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####################### |
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/* Configure CS1 */ |
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/* ####################### */ |
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# ESDCTL1: Enable controller |
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/* ESDCTL1: Enable controller */ |
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DATA 4 0x83fd9008 0x83220000 |
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# Init DRAM on CS1 |
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# ESDSCR: Precharge command |
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/* Init DRAM on CS1 */ |
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/* ESDSCR: Precharge command */ |
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DATA 4 0x83fd9014 0x0400800c |
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# ESDSCR: Refresh command |
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/* ESDSCR: Refresh command */ |
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DATA 4 0x83fd9014 0x00008014 |
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# ESDSCR: Refresh command |
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/* ESDSCR: Refresh command */ |
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DATA 4 0x83fd9014 0x00008014 |
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# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) |
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/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */ |
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DATA 4 0x83fd9014 0x0033801c |
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# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) |
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/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */ |
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DATA 4 0x83fd9014 0x0020801e |
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# ESDSCR |
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/* ESDSCR */ |
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DATA 4 0x83fd9014 0x00008004 |
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|
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# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 |
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/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */ |
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DATA 4 0x83fd9008 0xC3220000 |
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|
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# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks |
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#DATA 4 0x83fd900c 0xC33574AA |
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|
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#micron mDDR |
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# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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#DATA 4 0x83FD900C 0x101564a8 |
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|
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#hynix mDDR |
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# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks |
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# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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/* |
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* ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks |
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* DATA 4 0x83fd900c 0xC33574AA |
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*/ |
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/* |
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* micron mDDR |
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* ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks |
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* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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* DATA 4 0x83FD900C 0x101564a8 |
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*/ |
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/* |
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* hynix mDDR |
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* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks |
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* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks |
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*/ |
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DATA 4 0x83FD900C 0x704564a8 |
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|
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# ESDSCR (mDRAM configuration finished) |
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/* ESDSCR (mDRAM configuration finished) */ |
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DATA 4 0x83FD9014 0x00000004 |
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|
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# ESDSCR - clear "configuration request" bit |
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/* ESDSCR - clear "configuration request" bit */ |
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DATA 4 0x83fd9014 0x00000000 |
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|
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@ -1,4 +1,4 @@ |
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BOOT_FROM sd |
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|
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# DDR2 init |
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/* DDR2 init */ |
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DATA 4 0xB8001010 0x00000304 |
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|
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Reference in new issue