These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
9 years ago
committed by
Tom Rini
parent
af7f884ba1
commit
7495e41ba6
@ -1,15 +0,0 @@ |
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if TARGET_SNOWBALL |
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config SYS_BOARD |
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default "snowball" |
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config SYS_VENDOR |
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default "st-ericsson" |
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config SYS_SOC |
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default "u8500" |
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config SYS_CONFIG_NAME |
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default "snowball" |
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endif |
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@ -1,6 +0,0 @@ |
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SNOWBALL BOARD |
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M: Mathieu Poirier <mathieu.poirier@linaro.org> |
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S: Maintained |
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F: board/st-ericsson/snowball/ |
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F: include/configs/snowball.h |
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F: configs/snowball_defconfig |
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@ -1,9 +0,0 @@ |
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#
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# Copyright (C) ST-Ericsson SA 2009
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ccflags-y += -D__RELEASE -D__STN_8500
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obj-y := snowball.o
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@ -1,745 +0,0 @@ |
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/*
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* Copyright (C) ST-Ericsson SA 2010 |
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* Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. |
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* The purpose is that GPIO config found in kernel should work by simply |
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* copy-paste it to U-boot. |
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* |
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* Ported to U-boot by: |
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* Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> |
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** |
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* License terms: GNU General Public License, version 2 |
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* Author: Rabin Vincent <rabin.vincent@stericsson.com> |
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*/ |
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#ifndef __DB8500_PINS_H |
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#define __DB8500_PINS_H |
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#include <asm/arch/db8500_pincfg.h> |
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#define GPIO0_GPIO PIN_CFG(0, GPIO) |
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#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A) |
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#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B) |
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#define GPIO0_IP_TDO PIN_CFG(0, ALT_C) |
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#define GPIO1_GPIO PIN_CFG(1, GPIO) |
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#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A) |
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#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B) |
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#define GPIO1_IP_TDI PIN_CFG(1, ALT_C) |
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#define GPIO2_GPIO PIN_CFG(2, GPIO) |
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#define GPIO2_U0_RXD PIN_CFG(2, ALT_A) |
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#define GPIO2_NONE PIN_CFG(2, ALT_B) |
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#define GPIO2_IP_TMS PIN_CFG(2, ALT_C) |
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#define GPIO3_GPIO PIN_CFG(3, GPIO) |
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#define GPIO3_U0_TXD PIN_CFG(3, ALT_A) |
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#define GPIO3_NONE PIN_CFG(3, ALT_B) |
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#define GPIO3_IP_TCK PIN_CFG(3, ALT_C) |
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#define GPIO4_GPIO PIN_CFG(4, GPIO) |
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#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) |
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#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) |
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#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) |
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#define GPIO5_GPIO PIN_CFG(5, GPIO) |
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#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) |
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#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) |
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#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) |
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#define GPIO6_GPIO PIN_CFG(6, GPIO) |
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#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) |
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#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) |
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#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) |
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#define GPIO7_GPIO PIN_CFG(7, GPIO) |
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#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) |
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#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) |
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#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) |
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#define GPIO8_GPIO PIN_CFG(8, GPIO) |
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#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) |
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#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) |
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#define GPIO9_GPIO PIN_CFG(9, GPIO) |
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#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) |
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#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) |
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#define GPIO10_GPIO PIN_CFG(10, GPIO) |
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#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) |
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#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) |
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#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) |
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#define GPIO11_GPIO PIN_CFG(11, GPIO) |
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#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) |
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#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) |
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#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) |
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#define GPIO12_GPIO PIN_CFG(12, GPIO) |
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#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A) |
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#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B) |
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#define GPIO13_GPIO PIN_CFG(13, GPIO) |
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#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A) |
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#define GPIO14_GPIO PIN_CFG(14, GPIO) |
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#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A) |
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#define GPIO15_GPIO PIN_CFG(15, GPIO) |
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#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A) |
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#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B) |
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#define GPIO16_GPIO PIN_CFG(16, GPIO) |
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#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) |
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#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) |
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#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) |
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#define GPIO17_GPIO PIN_CFG(17, GPIO) |
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#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) |
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#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) |
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#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) |
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#define GPIO18_GPIO PIN_CFG(18, GPIO) |
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#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) |
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#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) |
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#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) |
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#define GPIO19_GPIO PIN_CFG(19, GPIO) |
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#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) |
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#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) |
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#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) |
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#define GPIO20_GPIO PIN_CFG(20, GPIO) |
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#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) |
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#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) |
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#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) |
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#define GPIO21_GPIO PIN_CFG(21, GPIO) |
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#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) |
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#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) |
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#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) |
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#define GPIO22_GPIO PIN_CFG(22, GPIO) |
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#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) |
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#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) |
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#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) |
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#define GPIO23_GPIO PIN_CFG(23, GPIO) |
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#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) |
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#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) |
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#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) |
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#define GPIO24_GPIO PIN_CFG(24, GPIO) |
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#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) |
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#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) |
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#define GPIO24_MS_BS PIN_CFG(24, ALT_C) |
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#define GPIO25_GPIO PIN_CFG(25, GPIO) |
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#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) |
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#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) |
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#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) |
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#define GPIO26_GPIO PIN_CFG(26, GPIO) |
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#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) |
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#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) |
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#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) |
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#define GPIO27_GPIO PIN_CFG(27, GPIO) |
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#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) |
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#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) |
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#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) |
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#define GPIO28_GPIO PIN_CFG(28, GPIO) |
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#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) |
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#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) |
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#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) |
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#define GPIO29_GPIO PIN_CFG(29, GPIO) |
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#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A) |
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#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B) |
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#define GPIO29_U2_RXD PIN_CFG(29, ALT_C) |
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#define GPIO30_GPIO PIN_CFG(30, GPIO) |
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#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) |
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#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B) |
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#define GPIO30_U2_TXD PIN_CFG(30, ALT_C) |
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#define GPIO31_GPIO PIN_CFG(31, GPIO) |
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#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A) |
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#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B) |
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#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C) |
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#define GPIO32_GPIO PIN_CFG(32, GPIO) |
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#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A) |
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#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B) |
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#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C) |
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#define GPIO33_GPIO PIN_CFG(33, GPIO) |
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#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A) |
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#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B) |
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#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C) |
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#define GPIO34_GPIO PIN_CFG(34, GPIO) |
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#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A) |
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#define GPIO34_NONE PIN_CFG(34, ALT_B) |
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#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C) |
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#define GPIO35_GPIO PIN_CFG(35, GPIO) |
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#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A) |
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#define GPIO35_NONE PIN_CFG(35, ALT_B) |
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#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C) |
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#define GPIO36_GPIO PIN_CFG(36, GPIO) |
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#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A) |
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#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B) |
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#define GPIO36_U0_RIn PIN_CFG(36, ALT_C) |
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#define GPIO64_GPIO PIN_CFG(64, GPIO) |
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#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A) |
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#define GPIO64_KP_O1 PIN_CFG(64, ALT_B) |
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#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C) |
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#define GPIO65_GPIO PIN_CFG(65, GPIO) |
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#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A) |
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#define GPIO65_KP_O0 PIN_CFG(65, ALT_B) |
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#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C) |
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#define GPIO66_GPIO PIN_CFG(66, GPIO) |
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#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A) |
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#define GPIO66_KP_I1 PIN_CFG(66, ALT_B) |
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#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C) |
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#define GPIO67_GPIO PIN_CFG(67, GPIO) |
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#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A) |
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#define GPIO67_KP_I0 PIN_CFG(67, ALT_B) |
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#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C) |
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#define GPIO68_GPIO PIN_CFG(68, GPIO) |
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#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A) |
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#define GPIO68_KP_O7 PIN_CFG(68, ALT_B) |
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#define GPIO68_SM_CLE PIN_CFG(68, ALT_C) |
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#define GPIO69_GPIO PIN_CFG(69, GPIO) |
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#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A) |
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#define GPIO69_KP_I7 PIN_CFG(69, ALT_B) |
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#define GPIO69_SM_ALE PIN_CFG(69, ALT_C) |
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#define GPIO70_GPIO PIN_CFG(70, GPIO) |
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#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A) |
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#define GPIO70_KP_O5 PIN_CFG(70, ALT_B) |
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#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C) |
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#define GPIO71_GPIO PIN_CFG(71, GPIO) |
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#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A) |
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#define GPIO71_KP_O4 PIN_CFG(71, ALT_B) |
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#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C) |
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#define GPIO72_GPIO PIN_CFG(72, GPIO) |
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#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A) |
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#define GPIO72_KP_O3 PIN_CFG(72, ALT_B) |
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#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C) |
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#define GPIO73_GPIO PIN_CFG(73, GPIO) |
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#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A) |
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#define GPIO73_KP_O2 PIN_CFG(73, ALT_B) |
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#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C) |
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#define GPIO74_GPIO PIN_CFG(74, GPIO) |
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#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A) |
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#define GPIO74_KP_I5 PIN_CFG(74, ALT_B) |
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#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C) |
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#define GPIO75_GPIO PIN_CFG(75, GPIO) |
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#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A) |
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#define GPIO75_KP_I4 PIN_CFG(75, ALT_B) |
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#define GPIO75_U2_RXD PIN_CFG(75, ALT_C) |
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#define GPIO76_GPIO PIN_CFG(76, GPIO) |
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#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A) |
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#define GPIO76_KP_I3 PIN_CFG(76, ALT_B) |
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#define GPIO76_U2_TXD PIN_CFG(76, ALT_C) |
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#define GPIO77_GPIO PIN_CFG(77, GPIO) |
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#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A) |
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#define GPIO77_KP_I2 PIN_CFG(77, ALT_B) |
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#define GPIO77_NONE PIN_CFG(77, ALT_C) |
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#define GPIO78_GPIO PIN_CFG(78, GPIO) |
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#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A) |
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#define GPIO78_KP_O6 PIN_CFG(78, ALT_B) |
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#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C) |
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#define GPIO79_GPIO PIN_CFG(79, GPIO) |
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#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A) |
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#define GPIO79_KP_I6 PIN_CFG(79, ALT_B) |
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#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C) |
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#define GPIO80_GPIO PIN_CFG(80, GPIO) |
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#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A) |
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#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B) |
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#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C) |
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#define GPIO81_GPIO PIN_CFG(81, GPIO) |
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#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A) |
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#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B) |
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#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C) |
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#define GPIO82_GPIO PIN_CFG(82, GPIO) |
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#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A) |
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#define GPIO82_KP_O5 PIN_CFG(82, ALT_B) |
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#define GPIO83_GPIO PIN_CFG(83, GPIO) |
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#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A) |
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#define GPIO83_KP_O4 PIN_CFG(83, ALT_B) |
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#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP) |
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#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A) |
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#define GPIO84_KP_I5 PIN_CFG(84, ALT_B) |
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#define GPIO85_GPIO PIN_CFG(85, GPIO) |
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#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A) |
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#define GPIO85_KP_I4 PIN_CFG(85, ALT_B) |
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#define GPIO86_GPIO PIN_CFG(86, GPIO) |
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#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A) |
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#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B) |
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#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C) |
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#define GPIO87_GPIO PIN_CFG(87, GPIO) |
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#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A) |
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#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B) |
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#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C) |
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#define GPIO88_GPIO PIN_CFG(88, GPIO) |
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#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A) |
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#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B) |
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#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C) |
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#define GPIO89_GPIO PIN_CFG(89, GPIO) |
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#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A) |
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#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B) |
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#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C) |
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#define GPIO90_GPIO PIN_CFG(90, GPIO) |
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#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A) |
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#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B) |
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#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C) |
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#define GPIO91_GPIO PIN_CFG(91, GPIO) |
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#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A) |
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#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B) |
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#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C) |
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#define GPIO92_GPIO PIN_CFG(92, GPIO) |
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#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A) |
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#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B) |
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#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C) |
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#define GPIO93_GPIO PIN_CFG(93, GPIO) |
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#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A) |
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#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B) |
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#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C) |
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#define GPIO94_GPIO PIN_CFG(94, GPIO) |
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#define GPIO94_KP_O7 PIN_CFG(94, ALT_A) |
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#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B) |
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#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C) |
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#define GPIO95_GPIO PIN_CFG(95, GPIO) |
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#define GPIO95_KP_I7 PIN_CFG(95, ALT_A) |
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#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B) |
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#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C) |
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#define GPIO96_GPIO PIN_CFG(96, GPIO) |
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#define GPIO96_KP_O6 PIN_CFG(96, ALT_A) |
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#define GPIO96_SM_OEn PIN_CFG(96, ALT_B) |
||||
#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C) |
||||
|
||||
#define GPIO97_GPIO PIN_CFG(97, GPIO) |
||||
#define GPIO97_KP_I6 PIN_CFG(97, ALT_A) |
||||
#define GPIO97_SM_WEn PIN_CFG(97, ALT_B) |
||||
#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) |
||||
|
||||
#define GPIO128_GPIO PIN_CFG(128, GPIO) |
||||
#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) |
||||
#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) |
||||
|
||||
#define GPIO129_GPIO PIN_CFG(129, GPIO) |
||||
#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) |
||||
#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) |
||||
|
||||
#define GPIO130_GPIO PIN_CFG(130, GPIO) |
||||
#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) |
||||
#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) |
||||
#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) |
||||
|
||||
#define GPIO131_GPIO PIN_CFG(131, GPIO) |
||||
#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) |
||||
#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) |
||||
|
||||
#define GPIO132_GPIO PIN_CFG(132, GPIO) |
||||
#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) |
||||
#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) |
||||
|
||||
#define GPIO133_GPIO PIN_CFG(133, GPIO) |
||||
#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) |
||||
#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) |
||||
|
||||
#define GPIO134_GPIO PIN_CFG(134, GPIO) |
||||
#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) |
||||
#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) |
||||
|
||||
#define GPIO135_GPIO PIN_CFG(135, GPIO) |
||||
#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) |
||||
#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) |
||||
|
||||
#define GPIO136_GPIO PIN_CFG(136, GPIO) |
||||
#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) |
||||
#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) |
||||
|
||||
#define GPIO137_GPIO PIN_CFG(137, GPIO) |
||||
#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) |
||||
#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) |
||||
|
||||
#define GPIO138_GPIO PIN_CFG(138, GPIO) |
||||
#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) |
||||
#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) |
||||
|
||||
#define GPIO139_GPIO PIN_CFG(139, GPIO) |
||||
#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A) |
||||
#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B) |
||||
#define GPIO139_KP_O8 PIN_CFG(139, ALT_C) |
||||
|
||||
#define GPIO140_GPIO PIN_CFG(140, GPIO) |
||||
#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A) |
||||
#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B) |
||||
#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C) |
||||
|
||||
#define GPIO141_GPIO PIN_CFG(141, GPIO) |
||||
#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A) |
||||
#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B) |
||||
#define GPIO141_KP_O9 PIN_CFG(141, ALT_C) |
||||
|
||||
#define GPIO142_GPIO PIN_CFG(142, GPIO) |
||||
#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A) |
||||
#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B) |
||||
#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C) |
||||
|
||||
#define GPIO143_GPIO PIN_CFG(143, GPIO) |
||||
#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A) |
||||
|
||||
#define GPIO144_GPIO PIN_CFG(144, GPIO) |
||||
#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A) |
||||
|
||||
#define GPIO145_GPIO PIN_CFG(145, GPIO) |
||||
#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A) |
||||
|
||||
#define GPIO146_GPIO PIN_CFG(146, GPIO) |
||||
#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) |
||||
|
||||
#define GPIO147_GPIO PIN_CFG(147, GPIO) |
||||
#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) |
||||
|
||||
#define GPIO148_GPIO PIN_CFG(148, GPIO) |
||||
#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) |
||||
|
||||
#define GPIO149_GPIO PIN_CFG(149, GPIO) |
||||
#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) |
||||
#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B) |
||||
#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C) |
||||
|
||||
#define GPIO150_GPIO PIN_CFG(150, GPIO) |
||||
#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A) |
||||
#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B) |
||||
|
||||
#define GPIO151_GPIO PIN_CFG(151, GPIO) |
||||
#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A) |
||||
#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B) |
||||
#define GPIO151_KP_O8 PIN_CFG(151, ALT_C) |
||||
|
||||
#define GPIO152_GPIO PIN_CFG(152, GPIO) |
||||
#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A) |
||||
#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B) |
||||
#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) |
||||
|
||||
#define GPIO153_GPIO PIN_CFG(153, GPIO) |
||||
#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) |
||||
#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) |
||||
#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) |
||||
|
||||
#define GPIO154_GPIO PIN_CFG(154, GPIO) |
||||
#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) |
||||
#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) |
||||
#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) |
||||
|
||||
#define GPIO155_GPIO PIN_CFG(155, GPIO) |
||||
#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) |
||||
#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) |
||||
#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) |
||||
|
||||
#define GPIO156_GPIO PIN_CFG(156, GPIO) |
||||
#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) |
||||
#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) |
||||
#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) |
||||
|
||||
#define GPIO157_GPIO PIN_CFG(157, GPIO) |
||||
#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) |
||||
#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) |
||||
#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) |
||||
|
||||
#define GPIO158_GPIO PIN_CFG(158, GPIO) |
||||
#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) |
||||
#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) |
||||
#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) |
||||
|
||||
#define GPIO159_GPIO PIN_CFG(159, GPIO) |
||||
#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) |
||||
#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) |
||||
#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) |
||||
|
||||
#define GPIO160_GPIO PIN_CFG(160, GPIO) |
||||
#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) |
||||
#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) |
||||
#define GPIO160_NONE PIN_CFG(160, ALT_C) |
||||
|
||||
#define GPIO161_GPIO PIN_CFG(161, GPIO) |
||||
#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) |
||||
#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) |
||||
#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) |
||||
|
||||
#define GPIO162_GPIO PIN_CFG(162, GPIO) |
||||
#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) |
||||
#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) |
||||
#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) |
||||
|
||||
#define GPIO163_GPIO PIN_CFG(163, GPIO) |
||||
#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) |
||||
#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) |
||||
#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) |
||||
|
||||
#define GPIO164_GPIO PIN_CFG(164, GPIO) |
||||
#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) |
||||
#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) |
||||
#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) |
||||
|
||||
#define GPIO165_GPIO PIN_CFG(165, GPIO) |
||||
#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) |
||||
#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) |
||||
#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) |
||||
|
||||
#define GPIO166_GPIO PIN_CFG(166, GPIO) |
||||
#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) |
||||
#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) |
||||
#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) |
||||
|
||||
#define GPIO167_GPIO PIN_CFG(167, GPIO) |
||||
#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) |
||||
#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) |
||||
#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) |
||||
|
||||
#define GPIO168_GPIO PIN_CFG(168, GPIO) |
||||
#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) |
||||
#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) |
||||
#define GPIO168_NONE PIN_CFG(168, ALT_C) |
||||
|
||||
#define GPIO169_GPIO PIN_CFG(169, GPIO) |
||||
#define GPIO169_RF_PURn PIN_CFG(169, ALT_A) |
||||
#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B) |
||||
#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C) |
||||
|
||||
#define GPIO170_GPIO PIN_CFG(170, GPIO) |
||||
#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A) |
||||
#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B) |
||||
#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C) |
||||
|
||||
#define GPIO171_GPIO PIN_CFG(171, GPIO) |
||||
#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A) |
||||
#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B) |
||||
#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C) |
||||
|
||||
#define GPIO192_GPIO PIN_CFG(192, GPIO) |
||||
#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A) |
||||
|
||||
#define GPIO193_GPIO PIN_CFG(193, GPIO) |
||||
#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A) |
||||
|
||||
#define GPIO194_GPIO PIN_CFG(194, GPIO) |
||||
#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A) |
||||
|
||||
#define GPIO195_GPIO PIN_CFG(195, GPIO) |
||||
#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A) |
||||
|
||||
#define GPIO196_GPIO PIN_CFG(196, GPIO) |
||||
#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) |
||||
|
||||
#define GPIO197_GPIO PIN_CFG(197, GPIO) |
||||
#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) |
||||
|
||||
#define GPIO198_GPIO PIN_CFG(198, GPIO) |
||||
#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) |
||||
|
||||
#define GPIO199_GPIO PIN_CFG(199, GPIO) |
||||
#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) |
||||
|
||||
#define GPIO200_GPIO PIN_CFG(200, GPIO) |
||||
#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) |
||||
|
||||
#define GPIO201_GPIO PIN_CFG(201, GPIO) |
||||
#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) |
||||
|
||||
#define GPIO202_GPIO PIN_CFG(202, GPIO) |
||||
#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) |
||||
#define GPIO202_PWL PIN_CFG(202, ALT_B) |
||||
#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) |
||||
|
||||
#define GPIO203_GPIO PIN_CFG(203, GPIO) |
||||
#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) |
||||
|
||||
#define GPIO204_GPIO PIN_CFG(204, GPIO) |
||||
#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) |
||||
|
||||
#define GPIO205_GPIO PIN_CFG(205, GPIO) |
||||
#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) |
||||
|
||||
#define GPIO206_GPIO PIN_CFG(206, GPIO) |
||||
#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) |
||||
|
||||
#define GPIO207_GPIO PIN_CFG(207, GPIO) |
||||
#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) |
||||
|
||||
#define GPIO208_GPIO PIN_CFG(208, GPIO) |
||||
#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) |
||||
|
||||
#define GPIO209_GPIO PIN_CFG(209, GPIO) |
||||
#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A) |
||||
#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B) |
||||
|
||||
#define GPIO210_GPIO PIN_CFG(210, GPIO) |
||||
#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A) |
||||
|
||||
#define GPIO211_GPIO PIN_CFG(211, GPIO) |
||||
#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A) |
||||
|
||||
#define GPIO212_GPIO PIN_CFG(212, GPIO) |
||||
#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A) |
||||
#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B) |
||||
|
||||
#define GPIO213_GPIO PIN_CFG(213, GPIO) |
||||
#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A) |
||||
#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B) |
||||
|
||||
#define GPIO214_GPIO PIN_CFG(214, GPIO) |
||||
#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A) |
||||
#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B) |
||||
|
||||
#define GPIO215_GPIO PIN_CFG(215, GPIO) |
||||
#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) |
||||
#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) |
||||
#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) |
||||
|
||||
#define GPIO216_GPIO PIN_CFG(216, GPIO) |
||||
#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) |
||||
#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) |
||||
#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) |
||||
|
||||
#define GPIO217_GPIO PIN_CFG(217, GPIO) |
||||
#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) |
||||
#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) |
||||
#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) |
||||
|
||||
#define GPIO218_GPIO PIN_CFG(218, GPIO) |
||||
#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) |
||||
#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) |
||||
#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) |
||||
|
||||
#define GPIO219_GPIO PIN_CFG(219, GPIO) |
||||
#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) |
||||
#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B) |
||||
|
||||
#define GPIO220_GPIO PIN_CFG(220, GPIO) |
||||
#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A) |
||||
#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B) |
||||
#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C) |
||||
|
||||
#define GPIO221_GPIO PIN_CFG(221, GPIO) |
||||
#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A) |
||||
#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B) |
||||
|
||||
#define GPIO222_GPIO PIN_CFG(222, GPIO) |
||||
#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A) |
||||
#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B) |
||||
|
||||
#define GPIO223_GPIO PIN_CFG(223, GPIO) |
||||
#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A) |
||||
#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B) |
||||
#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C) |
||||
|
||||
#define GPIO224_GPIO PIN_CFG(224, GPIO) |
||||
#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A) |
||||
#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B) |
||||
#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C) |
||||
|
||||
#define GPIO225_GPIO PIN_CFG(225, GPIO) |
||||
#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A) |
||||
#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B) |
||||
#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C) |
||||
|
||||
#define GPIO226_GPIO PIN_CFG(226, GPIO) |
||||
#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A) |
||||
#define GPIO226_PWL PIN_CFG(226, ALT_B) |
||||
#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C) |
||||
|
||||
#define GPIO227_GPIO PIN_CFG(227, GPIO) |
||||
#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A) |
||||
|
||||
#define GPIO228_GPIO PIN_CFG(228, GPIO) |
||||
#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A) |
||||
|
||||
#define GPIO229_GPIO PIN_CFG(229, GPIO) |
||||
#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) |
||||
#define GPIO229_PWL PIN_CFG(229, ALT_B) |
||||
#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) |
||||
|
||||
#define GPIO230_GPIO PIN_CFG(230, GPIO) |
||||
#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) |
||||
#define GPIO230_PWL PIN_CFG(230, ALT_B) |
||||
#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) |
||||
|
||||
#define GPIO256_GPIO PIN_CFG(256, GPIO) |
||||
#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) |
||||
|
||||
#define GPIO257_GPIO PIN_CFG(257, GPIO) |
||||
#define GPIO257_USB_STP PIN_CFG(257, ALT_A) |
||||
|
||||
#define GPIO258_GPIO PIN_CFG(258, GPIO) |
||||
#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A) |
||||
#define GPIO258_NONE PIN_CFG(258, ALT_B) |
||||
#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C) |
||||
|
||||
#define GPIO259_GPIO PIN_CFG(259, GPIO) |
||||
#define GPIO259_USB_DIR PIN_CFG(259, ALT_A) |
||||
|
||||
#define GPIO260_GPIO PIN_CFG(260, GPIO) |
||||
#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A) |
||||
|
||||
#define GPIO261_GPIO PIN_CFG(261, GPIO) |
||||
#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A) |
||||
|
||||
#define GPIO262_GPIO PIN_CFG(262, GPIO) |
||||
#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A) |
||||
|
||||
#define GPIO263_GPIO PIN_CFG(263, GPIO) |
||||
#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A) |
||||
|
||||
#define GPIO264_GPIO PIN_CFG(264, GPIO) |
||||
#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A) |
||||
|
||||
#define GPIO265_GPIO PIN_CFG(265, GPIO) |
||||
#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A) |
||||
|
||||
#define GPIO266_GPIO PIN_CFG(266, GPIO) |
||||
#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A) |
||||
|
||||
#define GPIO267_GPIO PIN_CFG(267, GPIO) |
||||
#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A) |
||||
|
||||
#endif |
||||
@ -1,340 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2009 |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <i2c.h> |
||||
#include <mmc.h> |
||||
#include <asm/types.h> |
||||
#include <asm/io.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/arch/db8500_pincfg.h> |
||||
#include <asm/arch/prcmu.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
|
||||
#ifdef CONFIG_MMC |
||||
#include "../../../drivers/mmc/arm_pl180_mmci.h" |
||||
#endif |
||||
#include "db8500_pins.h" |
||||
|
||||
/*
|
||||
* Get a global data pointer |
||||
*/ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Memory controller register |
||||
*/ |
||||
#define DMC_BASE_ADDR 0x80156000 |
||||
#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) |
||||
|
||||
/*
|
||||
* GPIO pin config common for MOP500/HREF boards |
||||
*/ |
||||
unsigned long gpio_cfg_common[] = { |
||||
/* I2C */ |
||||
GPIO147_I2C0_SCL, |
||||
GPIO148_I2C0_SDA, |
||||
GPIO16_I2C1_SCL, |
||||
GPIO17_I2C1_SDA, |
||||
GPIO10_I2C2_SDA, |
||||
GPIO11_I2C2_SCL, |
||||
GPIO229_I2C3_SDA, |
||||
GPIO230_I2C3_SCL, |
||||
|
||||
/* SSP0, to AB8500 */ |
||||
GPIO143_SSP0_CLK, |
||||
GPIO144_SSP0_FRM, |
||||
GPIO145_SSP0_RXD | PIN_PULL_DOWN, |
||||
GPIO146_SSP0_TXD, |
||||
|
||||
/* MMC0 (MicroSD card) */ |
||||
GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH, |
||||
GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH, |
||||
GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH, |
||||
GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, |
||||
GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL, |
||||
GPIO23_MC0_CLK | PIN_OUTPUT_LOW, |
||||
GPIO24_MC0_CMD | PIN_INPUT_PULLUP, |
||||
GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP, |
||||
GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP, |
||||
GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP, |
||||
GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP, |
||||
|
||||
/* MMC4 (On-board eMMC) */ |
||||
GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP, |
||||
GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP, |
||||
GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP, |
||||
GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP, |
||||
GPIO201_MC4_CMD | PIN_INPUT_PULLUP, |
||||
GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL, |
||||
GPIO203_MC4_CLK | PIN_OUTPUT_LOW, |
||||
GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP, |
||||
GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP, |
||||
GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP, |
||||
GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP, |
||||
|
||||
/* UART2, console */ |
||||
GPIO29_U2_RXD | PIN_INPUT_PULLUP, |
||||
GPIO30_U2_TXD | PIN_OUTPUT_HIGH, |
||||
GPIO31_U2_CTSn | PIN_INPUT_PULLUP, |
||||
GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, |
||||
|
||||
/*
|
||||
* USB, pin 256-267 USB, Is probably already setup correctly from |
||||
* BootROM/boot stages, but we don't trust that and set it up anyway |
||||
*/ |
||||
GPIO256_USB_NXT, |
||||
GPIO257_USB_STP, |
||||
GPIO258_USB_XCLK, |
||||
GPIO259_USB_DIR, |
||||
GPIO260_USB_DAT7, |
||||
GPIO261_USB_DAT6, |
||||
GPIO262_USB_DAT5, |
||||
GPIO263_USB_DAT4, |
||||
GPIO264_USB_DAT3, |
||||
GPIO265_USB_DAT2, |
||||
GPIO266_USB_DAT1, |
||||
GPIO267_USB_DAT0, |
||||
}; |
||||
|
||||
unsigned long gpio_cfg_snowball[] = { |
||||
/* MMC0 (MicroSD card) */ |
||||
GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */ |
||||
GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */ |
||||
GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */ |
||||
|
||||
/* eMMC */ |
||||
GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */ |
||||
|
||||
/* LAN */ |
||||
GPIO131_SM_ADQ8, |
||||
GPIO132_SM_ADQ9, |
||||
GPIO133_SM_ADQ10, |
||||
GPIO134_SM_ADQ11, |
||||
GPIO135_SM_ADQ12, |
||||
GPIO136_SM_ADQ13, |
||||
GPIO137_SM_ADQ14, |
||||
GPIO138_SM_ADQ15, |
||||
|
||||
/* RSTn_LAN */ |
||||
GPIO141_GPIO | PIN_OUTPUT_HIGH, |
||||
}; |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/*
|
||||
* Setup board (bd) and board-info (bi). |
||||
* bi_arch_number: Unique id for this board. It will passed in r1 to |
||||
* Linux startup code and is the machine_id. |
||||
* bi_boot_params: Where this board expects params. |
||||
*/ |
||||
gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL; |
||||
gd->bd->bi_boot_params = 0x00000100; |
||||
|
||||
/* Configure GPIO pins needed by U-boot */ |
||||
db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common)); |
||||
|
||||
db8500_gpio_config_pins(gpio_cfg_snowball, |
||||
ARRAY_SIZE(gpio_cfg_snowball)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
||||
gd->ram_size = gd->bd->bi_dram[0].size = |
||||
get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int raise_ab8500_gpio16(void) |
||||
{ |
||||
int ret; |
||||
|
||||
/* selection */ |
||||
ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
ret |= 0x80; |
||||
ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
/* direction */ |
||||
ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
ret |= 0x80; |
||||
ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
/* out */ |
||||
ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
ret |= 0x80; |
||||
ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret); |
||||
|
||||
out: |
||||
return ret; |
||||
} |
||||
|
||||
static int raise_ab8500_gpio26(void) |
||||
{ |
||||
int ret; |
||||
|
||||
/* selection */ |
||||
ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
ret |= 0x2; |
||||
ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
/* out */ |
||||
ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG); |
||||
if (ret < 0) |
||||
goto out; |
||||
|
||||
ret |= 0x2; |
||||
ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret); |
||||
|
||||
out: |
||||
return ret; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
/* enable 3V3 for LAN controller */ |
||||
if (raise_ab8500_gpio26() >= 0) { |
||||
/* Turn on FSMC device */ |
||||
writel(0x1, 0x8000f000); |
||||
writel(0x1, 0x8000f008); |
||||
|
||||
/* setup FSMC for LAN controler */ |
||||
writel(0x305b, 0x80000000); |
||||
|
||||
/* run at the highest possible speed */ |
||||
writel(0x01010210, 0x80000004); |
||||
} else |
||||
printf("error: can't raise GPIO26\n"); |
||||
|
||||
/* enable 3v6 for GBF chip */ |
||||
if ((raise_ab8500_gpio16() < 0)) |
||||
printf("error: cant' raise GPIO16\n"); |
||||
|
||||
/* empty UART RX FIFO */ |
||||
while (tstc()) |
||||
(void) getc(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_MMC |
||||
/*
|
||||
* emmc_host_init - initialize the emmc controller. |
||||
* Configure GPIO settings, set initial clock and power for emmc slot. |
||||
* Initialize mmc struct and register with mmc framework. |
||||
*/ |
||||
static int emmc_host_init(void) |
||||
{ |
||||
struct pl180_mmc_host *host; |
||||
|
||||
host = malloc(sizeof(struct pl180_mmc_host)); |
||||
if (!host) |
||||
return -ENOMEM; |
||||
memset(host, 0, sizeof(*host)); |
||||
|
||||
host->base = (struct sdi_registers *)CFG_EMMC_BASE; |
||||
host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON; |
||||
host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | |
||||
SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN; |
||||
strcpy(host->name, "EMMC"); |
||||
host->caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; |
||||
host->voltages = VOLTAGE_WINDOW_MMC; |
||||
host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2); |
||||
host->clock_max = ARM_MCLK / 2; |
||||
host->clock_in = ARM_MCLK; |
||||
host->version2 = 1; |
||||
|
||||
return arm_pl180_mmci_init(host); |
||||
} |
||||
|
||||
/*
|
||||
* mmc_host_init - initialize the external mmc controller. |
||||
* Configure GPIO settings, set initial clock and power for mmc slot. |
||||
* Initialize mmc struct and register with mmc framework. |
||||
*/ |
||||
static int mmc_host_init(void) |
||||
{ |
||||
struct pl180_mmc_host *host; |
||||
u32 sdi_u32; |
||||
|
||||
host = malloc(sizeof(struct pl180_mmc_host)); |
||||
if (!host) |
||||
return -ENOMEM; |
||||
memset(host, 0, sizeof(*host)); |
||||
|
||||
host->base = (struct sdi_registers *)CFG_MMC_BASE; |
||||
sdi_u32 = 0xBF; |
||||
writel(sdi_u32, &host->base->power); |
||||
host->pwr_init = 0xBF; |
||||
host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | |
||||
SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN; |
||||
strcpy(host->name, "MMC"); |
||||
host->caps = MMC_MODE_8BIT; |
||||
host->b_max = 0; |
||||
host->voltages = VOLTAGE_WINDOW_SD; |
||||
host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2); |
||||
host->clock_max = ARM_MCLK / 2; |
||||
host->clock_in = ARM_MCLK; |
||||
host->version2 = 1; |
||||
|
||||
return arm_pl180_mmci_init(host); |
||||
} |
||||
|
||||
/*
|
||||
* board_mmc_init - initialize all the mmc/sd host controllers. |
||||
* Called by generic mmc framework. |
||||
*/ |
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int error; |
||||
|
||||
(void) bis; |
||||
|
||||
error = emmc_host_init(); |
||||
if (error) { |
||||
printf("emmc_host_init() %d\n", error); |
||||
return -1; |
||||
} |
||||
|
||||
u8500_mmc_power_init(); |
||||
|
||||
error = mmc_host_init(); |
||||
if (error) { |
||||
printf("mmc_host_init() %d\n", error); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_MMC */ |
||||
@ -1,15 +0,0 @@ |
||||
if TARGET_U8500_HREF |
||||
|
||||
config SYS_BOARD |
||||
default "u8500" |
||||
|
||||
config SYS_VENDOR |
||||
default "st-ericsson" |
||||
|
||||
config SYS_SOC |
||||
default "u8500" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "u8500_href" |
||||
|
||||
endif |
||||
@ -1,6 +0,0 @@ |
||||
U8500 BOARD |
||||
#M: - |
||||
S: Maintained |
||||
F: board/st-ericsson/u8500/ |
||||
F: include/configs/u8500_href.h |
||||
F: configs/u8500_href_defconfig |
||||
@ -1,9 +0,0 @@ |
||||
#
|
||||
# Copyright (C) ST-Ericsson SA 2009
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ccflags-y += -D__RELEASE -D__STN_8500
|
||||
|
||||
obj-y := u8500_href.o gpio.o
|
||||
@ -1,331 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2009 |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/gpio.h> |
||||
|
||||
static struct gpio_register *addr_gpio_register[] = { |
||||
(void *)U8500_GPIO_0_BASE, |
||||
(void *)U8500_GPIO_1_BASE, |
||||
(void *)U8500_GPIO_2_BASE, |
||||
(void *)U8500_GPIO_3_BASE, |
||||
(void *)U8500_GPIO_4_BASE, |
||||
(void *)U8500_GPIO_5_BASE, |
||||
(void *)U8500_GPIO_6_BASE, |
||||
(void *)U8500_GPIO_7_BASE, |
||||
(void *)U8500_GPIO_8_BASE, |
||||
}; |
||||
|
||||
struct gpio_altfun_data altfun_table[] = { |
||||
{ |
||||
.altfun = GPIO_ALT_I2C_0, |
||||
.start = 147, |
||||
.end = 148, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_I2C_1, |
||||
.start = 16, |
||||
.end = 17, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_B, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_I2C_2, |
||||
.start = 10, |
||||
.end = 11, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_B, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_I2C_3, |
||||
.start = 229, |
||||
.end = 230, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_C, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_UART_0_MODEM, |
||||
.start = 0, |
||||
.end = 3, |
||||
.cont = 1, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_UART_0_MODEM, |
||||
.start = 33, |
||||
.end = 36, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_C, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_UART_1, |
||||
.start = 4, |
||||
.end = 7, |
||||
.cont = 0, |
||||
.type = |
||||
GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_UART_2, |
||||
.start = 18, |
||||
.end = 19, |
||||
.cont = 1, |
||||
.type = GPIO_ALTF_B, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_UART_2, |
||||
.start = 29, |
||||
.end = 32, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_C, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_MSP_0, |
||||
.start = 12, |
||||
.end = 17, |
||||
.cont = 1, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_MSP_0, |
||||
.start = 21, |
||||
.end = 21, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_B, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_MSP_1, |
||||
.start = 33, |
||||
.end = 36, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_MSP_2, |
||||
.start = 192, |
||||
.end = 196, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_LCD_PANEL, |
||||
.start = 64, |
||||
.end = 93, |
||||
.cont = 1, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_LCD_PANEL, |
||||
.start = 150, |
||||
.end = 171, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_B, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_SD_CARD0, |
||||
.start = 18, |
||||
.end = 28, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_MM_CARD0, |
||||
.start = 18, |
||||
.end = 32, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_USB_OTG, |
||||
.start = 256, |
||||
.end = 267, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_EMMC, |
||||
.start = 197, |
||||
.end = 207, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
{ |
||||
.altfun = GPIO_ALT_POP_EMMC, |
||||
.start = 128, |
||||
.end = 138, |
||||
.cont = 0, |
||||
.type = GPIO_ALTF_A, |
||||
}, |
||||
}; |
||||
|
||||
/*
|
||||
* Static Function declarations |
||||
*/ |
||||
enum gpio_error gpio_setpinconfig(int pin_id, struct gpio_config *config) |
||||
{ |
||||
struct gpio_register *p_gpio_register = |
||||
addr_gpio_register[GPIO_BLOCK(pin_id)]; |
||||
u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); |
||||
enum gpio_error error = GPIO_OK; |
||||
u32 temp_reg; |
||||
|
||||
switch (config->mode) { |
||||
case GPIO_ALTF_A: |
||||
temp_reg = readl(&p_gpio_register->gpio_afsa); |
||||
temp_reg |= mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsa); |
||||
temp_reg = readl(&p_gpio_register->gpio_afsb); |
||||
temp_reg &= ~mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsb); |
||||
break; |
||||
case GPIO_ALTF_B: |
||||
temp_reg = readl(&p_gpio_register->gpio_afsa); |
||||
temp_reg &= ~mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsa); |
||||
temp_reg = readl(&p_gpio_register->gpio_afsb); |
||||
temp_reg |= mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsb); |
||||
break; |
||||
case GPIO_ALTF_C: |
||||
temp_reg = readl(&p_gpio_register->gpio_afsa); |
||||
temp_reg |= mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsa); |
||||
temp_reg = readl(&p_gpio_register->gpio_afsb); |
||||
temp_reg |= mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsb); |
||||
break; |
||||
case GPIO_MODE_SOFTWARE: |
||||
temp_reg = readl(&p_gpio_register->gpio_afsa); |
||||
temp_reg &= ~mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsa); |
||||
temp_reg = readl(&p_gpio_register->gpio_afsb); |
||||
temp_reg &= ~mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsb); |
||||
|
||||
switch (config->direction) { |
||||
case GPIO_DIR_INPUT: |
||||
writel(mask, &p_gpio_register->gpio_dirc); |
||||
break; |
||||
case GPIO_DIR_OUTPUT: |
||||
writel(mask, &p_gpio_register->gpio_dirs); |
||||
break; |
||||
case GPIO_DIR_LEAVE_UNCHANGED: |
||||
break; |
||||
default: |
||||
return GPIO_INVALID_PARAMETER; |
||||
} |
||||
|
||||
break; |
||||
case GPIO_MODE_LEAVE_UNCHANGED: |
||||
break; |
||||
default: |
||||
return GPIO_INVALID_PARAMETER; |
||||
} |
||||
return error; |
||||
} |
||||
|
||||
enum gpio_error gpio_resetgpiopin(int pin_id, char *dev_name) |
||||
{ |
||||
struct gpio_register *p_gpio_register = |
||||
addr_gpio_register[GPIO_BLOCK(pin_id)]; |
||||
u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); |
||||
enum gpio_error error = GPIO_OK; |
||||
u32 temp_reg; |
||||
|
||||
temp_reg = readl(&p_gpio_register->gpio_afsa); |
||||
temp_reg &= ~mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsa); |
||||
temp_reg = readl(&p_gpio_register->gpio_afsb); |
||||
temp_reg &= ~mask; |
||||
writel(temp_reg, &p_gpio_register->gpio_afsb); |
||||
writel(mask, &p_gpio_register->gpio_dirc); |
||||
|
||||
return error; |
||||
} |
||||
|
||||
struct gpio_config altfun_pinconfig; |
||||
enum gpio_error gpio_altfunction(enum gpio_alt_function alt_func, |
||||
int which_altfunc, char *dev_name) |
||||
{ |
||||
int i, j, start, end; |
||||
enum gpio_error error = -1; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(altfun_table); i++) { |
||||
if (altfun_table[i].altfun != alt_func) |
||||
continue; |
||||
|
||||
start = altfun_table[i].start; |
||||
end = altfun_table[i].end; |
||||
for (j = start; j <= end; j++) { |
||||
if (which_altfunc == GPIO_ALTF_FIND) |
||||
altfun_pinconfig.mode = altfun_table[i].type; |
||||
else |
||||
altfun_pinconfig.mode = which_altfunc; |
||||
altfun_pinconfig.direction = GPIO_DIR_OUTPUT; |
||||
altfun_pinconfig.dev_name = dev_name; |
||||
|
||||
if (which_altfunc != GPIO_ALTF_DISABLE) |
||||
error = gpio_setpinconfig(j, &altfun_pinconfig); |
||||
else |
||||
error = gpio_resetgpiopin(j, dev_name); |
||||
if (!error) |
||||
continue; |
||||
printf("GPIO %d configuration failure (nmdk_error:%d)", |
||||
j, error); |
||||
error = GPIO_INVALID_PARAMETER; |
||||
return error; |
||||
} |
||||
|
||||
if (!altfun_table[i].cont) |
||||
break; |
||||
} |
||||
return error; |
||||
} |
||||
|
||||
int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name) |
||||
{ |
||||
struct gpio_register *p_gpio_register = |
||||
addr_gpio_register[GPIO_BLOCK(pin_id)]; |
||||
u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); |
||||
|
||||
switch (value) { |
||||
case GPIO_DATA_HIGH: |
||||
writel(mask, &p_gpio_register->gpio_dats); |
||||
break; |
||||
case GPIO_DATA_LOW: |
||||
writel(mask, &p_gpio_register->gpio_datc); |
||||
break; |
||||
default: |
||||
printf("Invalid value passed in %s", __FUNCTION__); |
||||
return GPIO_INVALID_PARAMETER; |
||||
} |
||||
return GPIO_OK; |
||||
} |
||||
|
||||
int gpio_readpin(int pin_id, enum gpio_data *rv) |
||||
{ |
||||
struct gpio_register *p_gpio_register = |
||||
addr_gpio_register[GPIO_BLOCK(pin_id)]; |
||||
u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); |
||||
|
||||
if ((readl(&p_gpio_register->gpio_dat) & mask) != 0) |
||||
*rv = GPIO_DATA_HIGH; |
||||
else |
||||
*rv = GPIO_DATA_LOW; |
||||
return GPIO_OK; |
||||
} |
||||
|
||||
int gpio_altfuncenable(enum gpio_alt_function altfunc, char *dev_name) |
||||
{ |
||||
return (int)gpio_altfunction(altfunc, GPIO_ALTF_FIND, dev_name); |
||||
} |
||||
|
||||
int gpio_altfuncdisable(enum gpio_alt_function altfunc, char *dev_name) |
||||
{ |
||||
return (int)gpio_altfunction(altfunc, GPIO_ALTF_DISABLE, dev_name); |
||||
} |
||||
@ -1,477 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2009 |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <i2c.h> |
||||
#include <asm/types.h> |
||||
#include <asm/io.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/prcmu.h> |
||||
#ifdef CONFIG_MMC |
||||
#include "../../../drivers/mmc/arm_pl180_mmci.h" |
||||
#endif |
||||
|
||||
#define NOMADIK_PER4_BASE (0x80150000) |
||||
#define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000) |
||||
#define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000) |
||||
|
||||
/* Power, Reset, Clock Management Unit */ |
||||
/*
|
||||
* SVA: Smart Video Accelerator |
||||
* SIA: Smart Imaging Accelerator |
||||
* SGA: Smart Graphic accelerator |
||||
* B2R2: Graphic blitter |
||||
*/ |
||||
#define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000) |
||||
#define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004) |
||||
#define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008) |
||||
#define PRCM_SIAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x00C) |
||||
#define PRCM_SAAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x010) |
||||
#define PRCM_SGACLK_MGT_REG (PRCMU_BASE + 0x014) |
||||
#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) |
||||
#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) |
||||
#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) |
||||
#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) |
||||
#define PRCM_SLIMCLK_MGT_REG (PRCMU_BASE + 0x028) |
||||
#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) |
||||
#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) |
||||
#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) |
||||
#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) |
||||
#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) |
||||
#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) |
||||
#define PRCM_DMACLK_MGT_REG (PRCMU_BASE + 0x074) |
||||
#define PRCM_B2R2CLK_MGT_REG (PRCMU_BASE + 0x078) |
||||
|
||||
#define PRCM_PLLSOC0_FREQ_REG (PRCMU_BASE + 0x080) |
||||
#define PRCM_PLLSOC1_FREQ_REG (PRCMU_BASE + 0x084) |
||||
#define PRCM_PLLARM_FREQ_REG (PRCMU_BASE + 0x088) |
||||
#define PRCM_PLLDDR_FREQ_REG (PRCMU_BASE + 0x08C) |
||||
#define PRCM_ARM_CHGCLKREQ_REG (PRCMU_BASE + 0x114) |
||||
|
||||
#define PRCM_TCR (PRCMU_BASE + 0x1C8) |
||||
|
||||
/*
|
||||
* Memory controller register |
||||
*/ |
||||
#define DMC_BASE_ADDR 0x80156000 |
||||
#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) |
||||
|
||||
int board_id; /* set in board_late_init() */ |
||||
|
||||
/* PLLs for clock management registers */ |
||||
enum { |
||||
GATED = 0, |
||||
PLLSOC0, /* pllsw = 001, ffs() = 1 */ |
||||
PLLSOC1, /* pllsw = 010, ffs() = 2 */ |
||||
PLLDDR, /* pllsw = 100, ffs() = 3 */ |
||||
PLLARM, |
||||
}; |
||||
|
||||
static struct pll_freq_regs { |
||||
int idx; /* index fror pll_name and pll_khz arrays */ |
||||
uint32_t addr; |
||||
} pll_freq_regs[] = { |
||||
{PLLSOC0, PRCM_PLLSOC0_FREQ_REG}, |
||||
{PLLSOC1, PRCM_PLLSOC1_FREQ_REG}, |
||||
{PLLDDR, PRCM_PLLDDR_FREQ_REG}, |
||||
{PLLARM, PRCM_PLLARM_FREQ_REG}, |
||||
{0, 0}, |
||||
}; |
||||
|
||||
static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"}; |
||||
static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */ |
||||
|
||||
static struct clk_mgt_regs { |
||||
uint32_t addr; |
||||
uint32_t val; |
||||
const char *descr; |
||||
} clk_mgt_regs[] = { |
||||
/* register content taken from bootrom settings */ |
||||
{PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */ |
||||
{PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */ |
||||
{PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */ |
||||
{PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */ |
||||
{PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */ |
||||
{PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */ |
||||
{PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */ |
||||
{PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */ |
||||
{PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */ |
||||
{PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */ |
||||
{PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */ |
||||
{PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */ |
||||
{PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */ |
||||
{PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */ |
||||
{PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */ |
||||
{PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */ |
||||
{PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */ |
||||
{PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */ |
||||
{0, 0, NULL}, |
||||
}; |
||||
|
||||
static void init_regs(void); |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
#if defined(CONFIG_SHOW_BOOT_PROGRESS) |
||||
void show_boot_progress(int progress) |
||||
{ |
||||
printf("Boot reached stage %d\n", progress); |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
init_regs(); |
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
uint32_t unused_cols_rows; |
||||
unsigned int nrows; |
||||
unsigned int ncols; |
||||
|
||||
gd->bd->bi_arch_number = 0x1A4; |
||||
gd->bd->bi_boot_params = 0x00000100; |
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
||||
|
||||
/*
|
||||
* Assumption: 2 CS active, both CS have same layout. |
||||
* 15 rows max, 11 cols max (controller spec). |
||||
* memory chip has 8 banks, I/O width 32 bit. |
||||
* The correct way would be to read MR#8: I/O width and density, |
||||
* but this requires locking against the PRCMU firmware. |
||||
* Simplified approach: |
||||
* Read number of unused rows and columns from mem controller. |
||||
* size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes |
||||
*/ |
||||
unused_cols_rows = readl(DMC_CTL_97); |
||||
nrows = 15 - (unused_cols_rows & 0x07); |
||||
ncols = 11 - ((unused_cols_rows & 0x0700) >> 8); |
||||
gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4; |
||||
|
||||
icache_enable(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = PHYS_SDRAM_SIZE_1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
unsigned int addr_vall_arr[] = { |
||||
0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */ |
||||
0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */ |
||||
0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */ |
||||
0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */ |
||||
0x80157020, 0x00000150, /* I2C 48MHz clock */ |
||||
0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */ |
||||
0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */ |
||||
0xA03DF000, 0x0000000D, /* Clock for MTU Timers */ |
||||
0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */ |
||||
0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */ |
||||
0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */ |
||||
0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */ |
||||
0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */ |
||||
0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */ |
||||
0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */ |
||||
0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */ |
||||
0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */ |
||||
0x801571E4, 0x0000000C, /* PRCMU settings for B2R2,
|
||||
PRCM_APE_RESETN_SET_REG */ |
||||
0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */ |
||||
0xA03FF000, 0x00000003, /* USB */ |
||||
0xA03FF008, 0x00000001, /* USB */ |
||||
0xA03FE00C, 0x00000000, /* USB */ |
||||
0xA03FE020, 0x00000FFF, /* USB */ |
||||
0xA03FE024, 0x00000000 /* USB */ |
||||
}; |
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT |
||||
/*
|
||||
* called after all initialisation were done, but before the generic |
||||
* mmc_initialize(). |
||||
*/ |
||||
int board_late_init(void) |
||||
{ |
||||
uchar byte; |
||||
|
||||
/*
|
||||
* Determine and set board_id environment variable |
||||
* 0: mop500, 1: href500 |
||||
* Above boards have different GPIO expander chips which we can |
||||
* distinguish by the chip id. |
||||
* |
||||
* The board_id environment variable is needed for the Linux bootargs. |
||||
*/ |
||||
(void) i2c_set_bus_num(0); |
||||
(void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1); |
||||
if (byte == 0x01) { |
||||
board_id = 0; |
||||
setenv("board_id", "0"); |
||||
} else { |
||||
board_id = 1; |
||||
setenv("board_id", "1"); |
||||
} |
||||
#ifdef CONFIG_MMC |
||||
u8500_mmc_power_init(); |
||||
|
||||
/*
|
||||
* config extended GPIO pins for level shifter and |
||||
* SDMMC_ENABLE |
||||
*/ |
||||
if (board_id == 0) { |
||||
/* MOP500 */ |
||||
byte = 0x0c; |
||||
(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1); |
||||
(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1); |
||||
} else { |
||||
/* HREF */ |
||||
/* set the direction of GPIO KPY9 and KPY10 */ |
||||
byte = 0x06; |
||||
(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1); |
||||
/* must be a multibyte access */ |
||||
(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1, |
||||
(uchar []) {0x06, 0x06}, 2); |
||||
} |
||||
#endif /* CONFIG_MMC */ |
||||
/*
|
||||
* Create a memargs variable which points uses either the memargs256 or |
||||
* memargs512 environment variable, depending on the memory size. |
||||
* memargs is used to build the bootargs, memargs256 and memargs512 are |
||||
* stored in the environment. |
||||
*/ |
||||
if (gd->bd->bi_dram[0].size == 0x10000000) { |
||||
setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}"); |
||||
setenv("mem", "256M"); |
||||
} else { |
||||
setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}"); |
||||
setenv("mem", "512M"); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_BOARD_LATE_INIT */ |
||||
|
||||
static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits) |
||||
{ |
||||
writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats); |
||||
writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis); |
||||
} |
||||
|
||||
static void init_regs(void) |
||||
{ |
||||
/* FIXME Remove magic register array settings for ED also */ |
||||
struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE; |
||||
|
||||
/* Enable timers */ |
||||
writel(1 << 17, &prcmu->tcr); |
||||
|
||||
u8500_prcmu_enable(&prcmu->per1clk_mgt); |
||||
u8500_prcmu_enable(&prcmu->per2clk_mgt); |
||||
u8500_prcmu_enable(&prcmu->per3clk_mgt); |
||||
u8500_prcmu_enable(&prcmu->per5clk_mgt); |
||||
u8500_prcmu_enable(&prcmu->per6clk_mgt); |
||||
u8500_prcmu_enable(&prcmu->per7clk_mgt); |
||||
|
||||
u8500_prcmu_enable(&prcmu->uartclk_mgt); |
||||
u8500_prcmu_enable(&prcmu->i2cclk_mgt); |
||||
|
||||
u8500_prcmu_enable(&prcmu->sdmmcclk_mgt); |
||||
|
||||
u8500_clock_enable(1, 9, -1); /* GPIO0 */ |
||||
|
||||
u8500_clock_enable(2, 11, -1); /* GPIO1 */ |
||||
|
||||
u8500_clock_enable(3, 8, -1); /* GPIO2 */ |
||||
u8500_clock_enable(5, 1, -1); /* GPIO3 */ |
||||
|
||||
u8500_clock_enable(3, 6, 6); /* UART2 */ |
||||
|
||||
gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0"); |
||||
u8500_clock_enable(3, 3, 3); /* I2C0 */ |
||||
|
||||
early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000); |
||||
gpio_altfuncenable(GPIO_ALT_UART_2, "UART2"); |
||||
|
||||
early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0); |
||||
gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC"); |
||||
|
||||
early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0); |
||||
gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD"); |
||||
|
||||
u8500_clock_enable(1, 5, 5); /* SDI0 */ |
||||
u8500_clock_enable(2, 4, 2); /* SDI4 */ |
||||
|
||||
u8500_clock_enable(6, 7, -1); /* MTU0 */ |
||||
u8500_clock_enable(3, 4, 4); /* SDI2 */ |
||||
|
||||
early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff); |
||||
gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC"); |
||||
|
||||
/*
|
||||
* Enabling clocks for all devices which are AMBA devices in the |
||||
* kernel. Otherwise they will not get probe()'d because the |
||||
* peripheral ID register will not be powered. |
||||
*/ |
||||
|
||||
/* XXX: some of these differ between ED/V1 */ |
||||
|
||||
u8500_clock_enable(1, 1, 1); /* UART1 */ |
||||
u8500_clock_enable(1, 0, 0); /* UART0 */ |
||||
|
||||
u8500_clock_enable(3, 2, 2); /* SSP1 */ |
||||
u8500_clock_enable(3, 1, 1); /* SSP0 */ |
||||
|
||||
u8500_clock_enable(2, 8, -1); /* SPI0 */ |
||||
u8500_clock_enable(2, 5, 3); /* MSP2 */ |
||||
} |
||||
|
||||
#ifdef CONFIG_MMC |
||||
static int u8500_mmci_board_init(void) |
||||
{ |
||||
enum gpio_error error; |
||||
struct gpio_register *gpio_base_address; |
||||
|
||||
gpio_base_address = (void *)(U8500_GPIO_0_BASE); |
||||
gpio_base_address->gpio_dats |= 0xFFC0000; |
||||
gpio_base_address->gpio_pdis &= ~0xFFC0000; |
||||
|
||||
/* save the GPIO0 AFSELA register */ |
||||
error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC"); |
||||
if (error != GPIO_OK) { |
||||
printf("u8500_mmci_board_init() gpio_altfuncenable failed\n"); |
||||
return -ENODEV; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bd) |
||||
{ |
||||
struct pl180_mmc_host *host; |
||||
|
||||
if (u8500_mmci_board_init()) |
||||
return -ENODEV; |
||||
|
||||
host = malloc(sizeof(struct pl180_mmc_host)); |
||||
if (!host) |
||||
return -ENOMEM; |
||||
memset(host, 0, sizeof(*host)); |
||||
|
||||
strcpy(host->name, "MMC"); |
||||
host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; |
||||
host->pwr_init = INIT_PWR; |
||||
host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; |
||||
host->voltages = VOLTAGE_WINDOW_MMC; |
||||
host->caps = 0; |
||||
host->clock_in = ARM_MCLK; |
||||
host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); |
||||
host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; |
||||
|
||||
return arm_pl180_mmci_init(host); |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* get_pll_freq_khz - return PLL frequency in kHz |
||||
*/ |
||||
static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg) |
||||
{ |
||||
uint32_t idf, ldf, odf, seldiv, phi; |
||||
|
||||
/*
|
||||
* PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0 |
||||
* PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1 |
||||
* where: |
||||
* IDF=R(2:0) (when R=000, IDF=1d) |
||||
* LDF = 2*D(7:0) (D must be greater than or equal to 6) |
||||
* ODF = N(5:0) (when N=000000, 0DF=1d) |
||||
*/ |
||||
|
||||
idf = (freq_reg & 0x70000) >> 16; |
||||
ldf = (freq_reg & 0xff) * 2; |
||||
odf = (freq_reg & 0x3f00) >> 8; |
||||
seldiv = (freq_reg & 0x01000000) >> 24; |
||||
phi = (inclk_khz * ldf) / (2 * odf * idf); |
||||
if (seldiv) |
||||
phi = phi/2; |
||||
|
||||
return phi; |
||||
} |
||||
|
||||
int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
uint32_t inclk_khz; |
||||
uint32_t reg, phi; |
||||
uint32_t clk_khz; |
||||
unsigned int clk_sel; |
||||
struct clk_mgt_regs *clks = clk_mgt_regs; |
||||
struct pll_freq_regs *plls = pll_freq_regs; |
||||
|
||||
/*
|
||||
* Go through list of PLLs. |
||||
* Initialise pll out frequency array (pll_khz) and print frequency. |
||||
*/ |
||||
inclk_khz = 38400; /* 38.4 MHz */ |
||||
while (plls->addr) { |
||||
reg = readl(plls->addr); |
||||
phi = get_pll_freq_khz(inclk_khz, reg); |
||||
pll_khz[plls->idx] = phi; |
||||
printf("%s PLL out frequency: %d.%d Mhz\n", |
||||
pll_name[plls->idx], phi/1000, phi % 1000); |
||||
plls++; |
||||
} |
||||
|
||||
/* check ARM clock source */ |
||||
reg = readl(PRCM_ARM_CHGCLKREQ_REG); |
||||
printf("A9 running on %s\n", |
||||
(reg & 1) ? "external clock" : "ARM PLL"); |
||||
|
||||
/* go through list of clk_mgt_reg */ |
||||
printf("\n%19s %9s %7s %9s enabled\n", |
||||
"name(addr)", "value", "PLL", "CLK[MHz]"); |
||||
while (clks->addr) { |
||||
reg = readl(clks->addr); |
||||
|
||||
/* convert bit position into array index */ |
||||
clk_sel = ffs((reg >> 5) & 0x7); /* PLLSW[2:0] */ |
||||
|
||||
if (reg & 0x200) |
||||
clk_khz = 38400; /* CLK38 is set */ |
||||
else if ((reg & 0x1f) == 0) |
||||
/* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */ |
||||
clk_khz = 0; |
||||
else |
||||
clk_khz = pll_khz[clk_sel] / (reg & 0x1f); |
||||
|
||||
printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n", |
||||
clks->descr, clks->addr, reg, pll_name[clk_sel], |
||||
clk_khz / 1000, clk_khz % 1000, |
||||
(reg & 0x100) ? "ena" : "dis"); |
||||
clks++; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
clkinfo, 1, 1, do_clkinfo, |
||||
"print clock info", |
||||
"" |
||||
); |
||||
@ -1,13 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_SNOWBALL=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
# CONFIG_CMD_EDITENV is not set |
||||
# CONFIG_CMD_ENV_EXISTS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
# CONFIG_CMD_ITEST is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
# CONFIG_CMD_NET is not set |
||||
# CONFIG_CMD_NFS is not set |
||||
CONFIG_SYS_PROMPT="U8500 $ " |
||||
@ -1,13 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_U8500_HREF=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
# CONFIG_CMD_EDITENV is not set |
||||
# CONFIG_CMD_ENV_EXISTS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
# CONFIG_CMD_ITEST is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
# CONFIG_CMD_NET is not set |
||||
# CONFIG_CMD_NFS is not set |
||||
CONFIG_SYS_PROMPT="U8500 $ " |
||||
@ -1,232 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2009 |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* #define DEBUG 1 |
||||
*/ |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_SNOWBALL |
||||
#define CONFIG_SYS_ICACHE_OFF |
||||
#define CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_ARCH_CPU_INIT |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_U8500 |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Size of environment and malloc() pool |
||||
*/ |
||||
/*
|
||||
* If you use U-Boot as crash kernel, make sure that it does not overwrite |
||||
* information saved by kexec during panic. Kexec expects the start |
||||
* address of the executable 32K above "crashkernel" address. |
||||
*/ |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_ENV_SIZE (8*1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) |
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_ENV_OFFSET 0x0118000 |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */ |
||||
|
||||
/*
|
||||
* PL011 Configuration |
||||
*/ |
||||
#define CONFIG_PL011_SERIAL |
||||
#define CONFIG_PL011_SERIAL_RLCR |
||||
#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT |
||||
|
||||
/*
|
||||
* U8500 UART registers base for 3 serial devices |
||||
*/ |
||||
#define CFG_UART0_BASE 0x80120000 |
||||
#define CFG_UART1_BASE 0x80121000 |
||||
#define CFG_UART2_BASE 0x80007000 |
||||
#define CFG_SERIAL0 CFG_UART0_BASE |
||||
#define CFG_SERIAL1 CFG_UART1_BASE |
||||
#define CFG_SERIAL2 CFG_UART2_BASE |
||||
#define CONFIG_PL011_CLOCK 38400000 |
||||
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \ |
||||
(void *)CFG_SERIAL2 } |
||||
#define CONFIG_CONS_INDEX 2 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* Devices and file systems |
||||
*/ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/*
|
||||
* Commands |
||||
*/ |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_EXT2 |
||||
|
||||
#ifndef CONFIG_BOOTDELAY |
||||
#define CONFIG_BOOTDELAY 1 |
||||
#endif |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev 1; " \
|
||||
"if run loadbootscript; " \
|
||||
"then run bootscript; " \
|
||||
"else " \
|
||||
"if run mmcload; " \
|
||||
"then run mmcboot; " \
|
||||
"else " \
|
||||
"mmc dev 0; " \
|
||||
"if run emmcloadbootscript; " \
|
||||
"then run bootscript; " \
|
||||
"else " \
|
||||
"if run emmcload; " \
|
||||
"then run emmcboot; " \
|
||||
"else " \
|
||||
"echo No media to boot from; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi; " |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"verify=n\0" \
|
||||
"loadaddr=0x00100000\0" \
|
||||
"console=ttyAMA2,115200n8\0" \
|
||||
"loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \
|
||||
"emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript " \
|
||||
"from mmc ...; source ${loadaddr}\0" \
|
||||
"memargs256=mem=96M@0 mem_modem=32M@96M mem=32M@128M " \
|
||||
"hwmem=22M@160M pmem_hwb=42M@182M mem_mali=32@224M\0" \
|
||||
"memargs512=mem=96M@0 mem_modem=32M@96M hwmem=32M@128M " \
|
||||
"mem=64M@160M mem_mali=32M@224M " \
|
||||
"pmem_hwb=128M@256M mem=128M@384M\0" \
|
||||
"memargs1024=mem=128M@0 mali.mali_mem=32M@128M " \
|
||||
"hwmem=168M@M160M mem=48M@328M " \
|
||||
"mem_issw=1M@383M mem=640M@384M\0" \
|
||||
"memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \
|
||||
"emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \
|
||||
"mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \
|
||||
"commonargs=setenv bootargs console=${console} " \
|
||||
"vmalloc=300M\0" \
|
||||
"emmcargs=setenv bootargs ${bootargs} " \
|
||||
"root=/dev/mmcblk0p3 " \
|
||||
"rootwait\0" \
|
||||
"addcons=setenv bootargs ${bootargs} " \
|
||||
"console=${console}\0" \
|
||||
"emmcboot=echo Booting from eMMC ...; " \
|
||||
"run commonargs emmcargs memargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"mmcargs=setenv bootargs ${bootargs} " \
|
||||
"root=/dev/mmcblk1p2 " \
|
||||
"rootwait earlyprintk\0" \
|
||||
"mmcboot=echo Booting from external MMC ...; " \
|
||||
"run commonargs mmcargs memargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"fdt_high=0x2BC00000\0" \
|
||||
"stdout=serial,usbtty\0" \
|
||||
"stdin=serial,usbtty\0" \
|
||||
"stderr=serial,usbtty\0" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
||||
+ sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 2 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ |
||||
|
||||
/*
|
||||
* additions for new relocation code |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000 |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/* landing address before relocation */ |
||||
#ifndef CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_TEXT_BASE 0x0 |
||||
#endif |
||||
|
||||
/*
|
||||
* MMC related configs |
||||
*/ |
||||
#define CONFIG_ARM_PL180_MMCI |
||||
#define MMC_BLOCK_SIZE 512 |
||||
#define CFG_EMMC_BASE 0x80114000 |
||||
#define CFG_MMC_BASE 0x80126000 |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/*
|
||||
* base register values for U8500 |
||||
*/ |
||||
#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */ |
||||
|
||||
|
||||
/*
|
||||
* U8500 GPIO register base for 9 banks |
||||
*/ |
||||
#define CONFIG_DB8500_GPIO |
||||
#define CFG_GPIO_0_BASE 0x8012E000 |
||||
#define CFG_GPIO_1_BASE 0x8012E080 |
||||
#define CFG_GPIO_2_BASE 0x8000E000 |
||||
#define CFG_GPIO_3_BASE 0x8000E080 |
||||
#define CFG_GPIO_4_BASE 0x8000E100 |
||||
#define CFG_GPIO_5_BASE 0x8000E180 |
||||
#define CFG_GPIO_6_BASE 0x8011E000 |
||||
#define CFG_GPIO_7_BASE 0x8011E080 |
||||
#define CFG_GPIO_8_BASE 0xA03FE000 |
||||
|
||||
#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,198 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2009 |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_U8500 |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#ifdef CONFIG_BOOT_SRAM |
||||
#define CONFIG_ENV_SIZE (32*1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024) |
||||
#else |
||||
#define CONFIG_ENV_SIZE (128*1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) |
||||
#endif |
||||
|
||||
/*
|
||||
* PL011 Configuration |
||||
*/ |
||||
#define CONFIG_PL011_SERIAL |
||||
#define CONFIG_PL011_SERIAL_RLCR |
||||
#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT |
||||
|
||||
/*
|
||||
* U8500 UART registers base for 3 serial devices |
||||
*/ |
||||
#define CFG_UART0_BASE 0x80120000 |
||||
#define CFG_UART1_BASE 0x80121000 |
||||
#define CFG_UART2_BASE 0x80007000 |
||||
#define CFG_SERIAL0 CFG_UART0_BASE |
||||
#define CFG_SERIAL1 CFG_UART1_BASE |
||||
#define CFG_SERIAL2 CFG_UART2_BASE |
||||
#define CONFIG_PL011_CLOCK 38400000 |
||||
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \ |
||||
(void *)CFG_SERIAL2 } |
||||
#define CONFIG_CONS_INDEX 2 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* Devices and file systems |
||||
*/ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/*
|
||||
* Commands |
||||
*/ |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_I2C |
||||
|
||||
#ifndef CONFIG_BOOTDELAY |
||||
#define CONFIG_BOOTDELAY 1 |
||||
#endif |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND "run emmcboot" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"verify=n\0" \
|
||||
"loadaddr=0x00100000\0" \
|
||||
"console=ttyAMA2,115200n8\0" \
|
||||
"memargs256=mem=96M@0 mem_modem=32M@96M mem=30M@128M " \
|
||||
"pmem=22M@158M pmem_hwb=44M@180M mem_mali=32@224M\0" \
|
||||
"memargs512=mem=96M@0 mem_modem=32M@96M mem=44M@128M " \
|
||||
"pmem=22M@172M mem=30M@194M mem_mali=32M@224M " \
|
||||
"pmem_hwb=54M@256M mem=202M@310M\0" \
|
||||
"commonargs=setenv bootargs cachepolicy=writealloc noinitrd " \
|
||||
"init=init " \
|
||||
"board_id=${board_id} " \
|
||||
"logo.${logo} " \
|
||||
"startup_graphics=${startup_graphics}\0" \
|
||||
"emmcargs=setenv bootargs ${bootargs} " \
|
||||
"root=/dev/mmcblk0p2 " \
|
||||
"rootdelay=1\0" \
|
||||
"addcons=setenv bootargs ${bootargs} " \
|
||||
"console=${console}\0" \
|
||||
"emmcboot=echo Booting from eMMC ...; " \
|
||||
"run commonargs emmcargs addcons memargs;" \
|
||||
"mmc read 0 ${loadaddr} 0xA0000 0x4000;" \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;" \
|
||||
"source ${loadaddr}\0" \
|
||||
"loaduimage=mmc init 1;fatload mmc 1 ${loadaddr} uImage\0" \
|
||||
"usbtty=cdc_acm\0" \
|
||||
"stdout=serial,usbtty\0" \
|
||||
"stdin=serial,usbtty\0" \
|
||||
"stderr=serial,usbtty\0" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
||||
+ sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 2 |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define CONFIG_U8500_I2C |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0 /* slave addr of controller */ |
||||
#define CONFIG_SYS_U8500_I2C0_BASE 0x80004000 |
||||
#define CONFIG_SYS_U8500_I2C1_BASE 0x80122000 |
||||
#define CONFIG_SYS_U8500_I2C2_BASE 0x80128000 |
||||
#define CONFIG_SYS_U8500_I2C3_BASE 0x80110000 |
||||
#define CONFIG_SYS_U8500_I2C_BUS_MAX 4 |
||||
|
||||
#define CONFIG_SYS_I2C_GPIOE_ADDR 0x42 /* GPIO expander chip addr */ |
||||
#define CONFIG_TC35892_GPIO |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_SIZE_1 0x20000000 /* 512 MB */ |
||||
|
||||
/*
|
||||
* additions for new relocation code |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/* landing address before relocation */ |
||||
#ifndef CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_TEXT_BASE 0x0 |
||||
#endif |
||||
|
||||
/*
|
||||
* MMC related configs |
||||
* NB Only externa SD slot is currently supported |
||||
*/ |
||||
#define MMC_BLOCK_SIZE 512 |
||||
#define CONFIG_ARM_PL180_MMCI |
||||
#define CONFIG_ARM_PL180_MMCI_BASE 0x80126000 /* MMC base for 8500 */ |
||||
#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 |
||||
#define CONFIG_MMC_DEV_NUM 1 |
||||
|
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET 0x13F80000 |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */ |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/*
|
||||
* base register values for U8500 |
||||
*/ |
||||
#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock |
||||
management unit */ |
||||
#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue