diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 6182d5f..31b73ed 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -108,8 +108,6 @@ struct socfpga_reset_manager {
 #define RSTMGR_GPIO1		RSTMGR_DEFINE(2, 25)
 #define RSTMGR_SDR		RSTMGR_DEFINE(3, 6)
 
-void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state);
-
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
 
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 5cc8336..f176c38 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -93,41 +93,6 @@ void socfpga_bridges_reset(int enable)
 	}
 }
 
-/* of_reset_id: emac reset id
- * state: 0 - disable reset, !0 - enable reset
- */
-void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)
-{
-	u32 reset_emac;
-	u32 reset_emacocp;
-
-	/* hardcode this now */
-	switch (of_reset_id) {
-	case EMAC0_RESET:
-		reset_emac = SOCFPGA_RESET(EMAC0);
-		reset_emacocp = SOCFPGA_RESET(EMAC0_OCP);
-		break;
-	case EMAC1_RESET:
-		reset_emac = SOCFPGA_RESET(EMAC1);
-		reset_emacocp = SOCFPGA_RESET(EMAC1_OCP);
-		break;
-	case EMAC2_RESET:
-		reset_emac = SOCFPGA_RESET(EMAC2);
-		reset_emacocp = SOCFPGA_RESET(EMAC2_OCP);
-		break;
-	default:
-		printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
-		hang();
-		break;
-	}
-
-	/* Reset ECC OCP first */
-	socfpga_per_reset(reset_emacocp, state);
-
-	/* Release the EMAC controller from reset */
-	socfpga_per_reset(reset_emac, state);
-}
-
 /*
  * Release peripherals from reset based on handoff
  */