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@ -46,12 +46,12 @@ |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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@ -72,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR; |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
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return 0; |
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return 0; |
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} |
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iomux_v3_cfg_t const uart1_pads[] = { |
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@ -83,8 +83,8 @@ iomux_v3_cfg_t const uart1_pads[] = { |
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}; |
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iomux_v3_cfg_t const uart2_pads[] = { |
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MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
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@ -132,23 +132,23 @@ struct i2c_pads_info i2c_pad_info2 = { |
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}; |
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iomux_v3_cfg_t const usdhc3_pads[] = { |
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MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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}; |
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iomux_v3_cfg_t const usdhc4_pads[] = { |
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MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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}; |
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iomux_v3_cfg_t const enet_pads1[] = { |
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@ -227,7 +227,7 @@ iomux_v3_cfg_t const usb_pads[] = { |
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static void setup_iomux_uart(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
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} |
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#ifdef CONFIG_USB_EHCI_MX6 |
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@ -246,55 +246,55 @@ int board_ehci_hcd_init(int port) |
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#ifdef CONFIG_FSL_ESDHC |
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struct fsl_esdhc_cfg usdhc_cfg[2] = { |
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{USDHC3_BASE_ADDR}, |
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{USDHC4_BASE_ADDR}, |
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{USDHC3_BASE_ADDR}, |
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{USDHC4_BASE_ADDR}, |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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int ret; |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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int ret; |
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if (cfg->esdhc_base == USDHC3_BASE_ADDR) { |
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if (cfg->esdhc_base == USDHC3_BASE_ADDR) { |
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gpio_direction_input(IMX_GPIO_NR(7, 0)); |
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ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); |
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} else { |
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} else { |
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gpio_direction_input(IMX_GPIO_NR(2, 6)); |
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ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); |
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} |
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} |
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return ret; |
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return ret; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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s32 status = 0; |
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u32 index = 0; |
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s32 status = 0; |
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u32 index = 0; |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
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for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { |
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switch (index) { |
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case 0: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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break; |
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case 1: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
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for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { |
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switch (index) { |
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case 0: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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break; |
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case 1: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
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break; |
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default: |
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printf("Warning: you configured more USDHC controllers" |
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printf("Warning: you configured more USDHC controllers" |
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"(%d) then supported by the board (%d)\n", |
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index + 1, CONFIG_SYS_FSL_USDHC_NUM); |
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return status; |
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} |
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return status; |
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} |
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status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); |
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} |
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status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); |
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} |
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return status; |
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return status; |
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} |
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#endif |
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@ -732,8 +732,8 @@ int overwrite_console(void) |
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int board_init(void) |
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{ |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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#ifdef CONFIG_MXC_SPI |
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setup_spi(); |
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@ -746,14 +746,14 @@ int board_init(void) |
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setup_sata(); |
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#endif |
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return 0; |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: MX6Q-Sabre Lite\n"); |
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puts("Board: MX6Q-Sabre Lite\n"); |
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return 0; |
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return 0; |
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} |
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struct button_key { |
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