Stefan Roese
20 years ago
parent
026cb5d864
commit
7644f16f6b
@ -0,0 +1,46 @@ |
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o ../common/misc.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,28 @@ |
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# esd CPCI2DP board
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#
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TEXT_BASE = 0xFFFC0000
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@ -0,0 +1,215 @@ |
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/*
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* (C) Copyright 2005 |
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#include <command.h> |
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#include <malloc.h> |
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int board_early_init_f (void) |
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{ |
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unsigned long cntrl0Reg; |
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/*
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* Setup GPIO pins (CS4 as GPIO) |
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*/ |
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cntrl0Reg = mfdcr(cntrl0); |
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mtdcr(cntrl0, cntrl0Reg | 0x00800000); |
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out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* set output pins to high */ |
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out32(GPIO0_ODR, CFG_INTA_FAKE); /* INTA# is open drain */ |
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out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* setup for output */ |
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive |
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* IRQ 16 405GP internally generated; active low; level sensitive |
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* IRQ 17-24 RESERVED |
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* IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive |
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* IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive |
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* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive |
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* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive |
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* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive |
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* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive |
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* IRQ 31 (EXT IRQ 6) unused |
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*/ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr(uicer, 0x00000000); /* disable all ints */ |
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ |
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ |
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mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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return 0; |
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} |
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int misc_init_f (void) |
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{ |
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return 0; /* dummy implementation */ |
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} |
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int misc_init_r (void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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unsigned long cntrl0Reg; |
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/* adjust flash start and offset */ |
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
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gd->bd->bi_flashoffset = 0; |
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/*
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* Select cts (and not dsr) on uart1 |
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*/ |
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cntrl0Reg = mfdcr(cntrl0); |
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mtdcr(cntrl0, cntrl0Reg | 0x00001000); |
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return (0); |
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} |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard (void) |
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{ |
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unsigned char str[64]; |
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int i = getenv_r ("serial#", str, sizeof(str)); |
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puts ("Board: "); |
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if (i == -1) { |
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puts ("### No HW ID - assuming CPCI2DP"); |
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} else { |
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puts(str); |
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} |
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printf(" (Ver 1.0)"); |
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putc ('\n'); |
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return 0; |
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} |
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/* ------------------------------------------------------------------------- */ |
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long int initdram (int board_type) |
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{ |
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unsigned long val; |
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mtdcr(memcfga, mem_mb0cf); |
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val = mfdcr(memcfgd); |
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return (4*1024*1024 << ((val & 0x000e0000) >> 17)); |
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} |
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/* ------------------------------------------------------------------------- */ |
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int testdram (void) |
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{ |
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/* TODO: XXX XXX XXX */ |
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printf ("test: 64 MB - ok\n"); |
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return (0); |
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} |
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/* ------------------------------------------------------------------------- */ |
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#if defined(CFG_EEPROM_WREN) |
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state |
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* 0: disable write |
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* 1: enable write |
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* Returns: -1: wrong device address |
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* 0: dis-/en- able done |
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* 0/1: current state if <state> was -1. |
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*/ |
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int eeprom_write_enable (unsigned dev_addr, int state) { |
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if (CFG_I2C_EEPROM_ADDR != dev_addr) { |
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return -1; |
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} |
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else { |
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switch (state) { |
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case 1: |
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/* Enable write access, clear bit GPIO_SINT2. */ |
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); |
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state = 0; |
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break; |
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case 0: |
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/* Disable write access, set bit GPIO_SINT2. */ |
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); |
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state = 0; |
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break; |
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default: |
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/* Read current status back. */ |
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state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); |
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break; |
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} |
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} |
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return state; |
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} |
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#endif |
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#if defined(CFG_EEPROM_WREN) |
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int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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int query = argc == 1; |
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int state = 0; |
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if (query) { |
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/* Query write access state. */ |
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); |
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if (state < 0) { |
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puts ("Query of write access state failed.\n"); |
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} |
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else { |
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printf ("Write access for device 0x%0x is %sabled.\n", |
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CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); |
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state = 0; |
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} |
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} |
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else { |
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if ('0' == argv[1][0]) { |
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/* Disable write access. */ |
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); |
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} |
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else { |
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/* Enable write access. */ |
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); |
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} |
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if (state < 0) { |
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puts ("Setup of write access state failed.\n"); |
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} |
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} |
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return state; |
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} |
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U_BOOT_CMD( |
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eepwren, 2, 0, do_eep_wren, |
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"eepwren - Enable / disable / query EEPROM write access\n", |
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NULL |
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); |
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#endif /* #if defined(CFG_EEPROM_WREN) */ |
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@ -0,0 +1,84 @@ |
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/*
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <ppc4xx.h> |
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#include <asm/processor.h> |
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/*
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* include common flash code (for esd boards) |
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*/ |
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#include "../common/flash.c" |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static void flash_get_offsets (ulong base, flash_info_t *info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size_b0; |
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int i; |
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uint pbcr; |
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unsigned long base_b0; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0<<20); |
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} |
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/* Setup offsets */ |
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flash_get_offsets (-size_b0, &flash_info[0]); |
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/* Re-do sizing to get full correct info */ |
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mtdcr(ebccfga, pb0cr); |
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pbcr = mfdcr(ebccfgd); |
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mtdcr(ebccfga, pb0cr); |
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base_b0 = -size_b0; |
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); |
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mtdcr(ebccfgd, pbcr); |
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/* printf("pb1cr = %x\n", pbcr); */ |
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/* Monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, |
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-monitor_flash_len, |
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0xffffffff, |
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&flash_info[0]); |
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flash_info[0].size = size_b0; |
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return (size_b0); |
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} |
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@ -0,0 +1,149 @@ |
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/* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(powerpc) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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.resetvec 0xFFFFFFFC : |
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{ |
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*(.resetvec) |
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} = 0xffff |
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|
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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|
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cpu/ppc4xx/start.o (.text) |
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cpu/ppc4xx/traps.o (.text) |
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cpu/ppc4xx/interrupts.o (.text) |
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cpu/ppc4xx/serial.o (.text) |
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cpu/ppc4xx/cpu_init.o (.text) |
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cpu/ppc4xx/speed.o (.text) |
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common/dlmalloc.o (.text) |
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lib_generic/crc32.o (.text) |
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lib_ppc/extable.o (.text) |
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lib_generic/zlib.o (.text) |
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|
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/* . = env_offset;*/ |
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/* common/environment.o(.text)*/ |
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|
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*(.text) |
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*(.fixup) |
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*(.got1) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(.rodata) |
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*(.rodata1) |
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*(.rodata.str1.4) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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|
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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*(.got) |
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_GOT2_TABLE_ = .; |
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*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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|
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.data : |
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{ |
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*(.data) |
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*(.data1) |
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*(.sdata) |
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*(.sdata2) |
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*(.dynamic) |
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CONSTRUCTORS |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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|
||||
. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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|
||||
|
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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|
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__bss_start = .; |
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.bss : |
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{ |
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*(.sbss) *(.scommon) |
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*(.dynbss) |
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*(.bss) |
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*(COMMON) |
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} |
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_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -0,0 +1,271 @@ |
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/*
|
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* (C) Copyright 2005 |
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#undef CONFIG_BOOTCOMMAND |
||||
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */ |
||||
|
||||
#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \ |
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_EEPROM ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#undef CFG_HUSH_PARSER /* use "hush" command parser */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ |
||||
|
||||
#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ |
||||
#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ |
||||
#define CFG_BASE_BAUD 691200 |
||||
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 } |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
/* resource configuration */ |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
||||
|
||||
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ |
||||
|
||||
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */ |
||||
#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ |
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ |
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs + PB0/1 */ |
||||
#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ |
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFFC0000 |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
||||
#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
||||
#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
||||
|
||||
#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ |
||||
#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ |
||||
#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ |
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
||||
#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC16) for environment |
||||
*/ |
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
|
||||
#define CFG_EEPROM_WREN 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ |
||||
/* have only 8kB, 16kB is save here */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */ |
||||
#define CFG_EBC_PB0AP 0x92015480 |
||||
#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 2 (PB0) initialization */ |
||||
#define CFG_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ |
||||
#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 3 (PB1) initialization */ |
||||
#define CFG_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ |
||||
#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
||||
|
||||
#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* GPIO definitions |
||||
*/ |
||||
#define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */ |
||||
#define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue