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@ -528,12 +528,18 @@ int serial_init(void) |
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udiv = 1; |
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tmp = gd->baudrate * 16; |
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bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; |
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gd->freqUART = CFG_EXT_SERIAL_CLOCK; |
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#else |
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/* For 440, the cpu clock is on divider chain A, UART on divider
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* chain B ... so cpu clock is irrelevant. Get the "optimized" |
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* values that are subject to the 1/2 opb clock constraint |
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*/ |
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serial_divs (gd->baudrate, &udiv, &bdiv); |
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/* Correct UART frequency in bd-info struct now that
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* the UART divisor is available |
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*/ |
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gd->freqUART = gd->freqUART / udiv; |
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#endif |
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reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ |
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@ -644,6 +650,15 @@ int serial_init (void) |
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bdiv = (clk + tmp / 2) / tmp; |
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#endif /* CONFIG_405EX */ |
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/* Correct UART frequency in bd-info struct now that
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* the UART divisor is available |
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*/ |
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#ifdef CFG_EXT_SERIAL_CLOCK |
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gd->freqUART = CFG_EXT_SERIAL_CLOCK; |
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#else |
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gd->freqUART = gd->freqUART / udiv; |
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#endif |
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out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ |
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out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ |
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out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ |
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