Add a sysreset driver for the MPC83xx platform. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>lime2-spi
Mario Six
6 years ago
committed by
Simon Glass
parent
23471aed5c
commit
76fdad1f21
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 |
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <sysreset.h> |
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#include <wait_bit.h> |
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#include "sysreset_mpc83xx.h" |
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/* Magic 4-byte word to enable reset ('RSTE' in ASCII) */ |
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static const u32 RPR_MAGIC = 0x52535445; |
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/* Wait at most 2000ms for reset control enable bit */ |
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static const uint RESET_WAIT_TIMEOUT = 2000; |
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/**
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* __do_reset() - Execute the system reset |
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* |
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* Return: The functions resets the system, and never returns. |
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*/ |
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static int __do_reset(void) |
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{ |
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ulong msr; |
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int res; |
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
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puts("Resetting the board.\n"); |
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/* Interrupts and MMU off */ |
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msr = mfmsr(); |
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msr &= ~(MSR_EE | MSR_IR | MSR_DR); |
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mtmsr(msr); |
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/* Enable Reset Control Reg */ |
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out_be32(&immap->reset.rpr, RPR_MAGIC); |
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sync(); |
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isync(); |
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/* Confirm Reset Control Reg is enabled */ |
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res = wait_for_bit_be32(&immap->reset.rcer, RCER_CRE, true, |
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RESET_WAIT_TIMEOUT, false); |
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if (res) { |
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debug("%s: Timed out waiting for reset control to be set\n", |
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__func__); |
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return res; |
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} |
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udelay(200); |
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/* Perform reset, only one bit */ |
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out_be32(&immap->reset.rcr, RCR_SWHR); |
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/* Never executes */ |
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return 0; |
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} |
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static int mpc83xx_sysreset_request(struct udevice *dev, enum sysreset_t type) |
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{ |
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switch (type) { |
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case SYSRESET_WARM: |
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case SYSRESET_COLD: |
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return __do_reset(); |
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default: |
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return -EPROTONOSUPPORT; |
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} |
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return -EINPROGRESS; |
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} |
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/**
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* print_83xx_arb_event() - Print arbiter events to buffer |
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* @force: Print arbiter events, even if none are indicated by the system |
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* @buf: The buffer to receive the printed arbiter event information |
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* @size: The size of the buffer to receive the printed arbiter event |
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* information in bytes |
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* |
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* Return: Number of bytes printed to buffer, -ve on error |
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*/ |
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static int print_83xx_arb_event(bool force, char *buf, int size) |
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{ |
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int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT) |
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>> AEATR_EVENT_SHIFT; |
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int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID) |
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>> AEATR_MSTR_ID_SHIFT; |
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int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST) |
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>> AEATR_TBST_SHIFT; |
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int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE) |
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>> AEATR_TSIZE_SHIFT; |
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int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE) |
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>> AEATR_TTYPE_SHIFT; |
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int tsize_val = (tbst << 3) | tsize; |
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int tsize_bytes = tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize; |
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int res = 0; |
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/*
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* If we don't force output, and there is no event (event address == |
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* 0), then don't print anything |
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*/ |
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if (!force && !gd->arch.arbiter_event_address) |
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return 0; |
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if (CONFIG_IS_ENABLED(CONFIG_DISPLAY_AER_FULL)) { |
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res = snprintf(buf, size, |
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"Arbiter Event Status:\n" |
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" %s: 0x%08lX\n" |
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" %s: 0x%1x = %s\n" |
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" %s: 0x%02x = %s\n" |
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" %s: 0x%1x = %d bytes\n" |
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" %s: 0x%02x = %s\n", |
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"Event Address", gd->arch.arbiter_event_address, |
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"Event Type", etype, event[etype], |
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"Master ID", mstr_id, master[mstr_id], |
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"Transfer Size", tsize_val, tsize_bytes, |
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"Transfer Type", ttype, transfer[ttype]); |
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} else if (CONFIG_IS_ENABLED(CONFIG_DISPLAY_AER_BRIEF)) { |
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res = snprintf(buf, size, |
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"Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n", |
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gd->arch.arbiter_event_attributes, |
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gd->arch.arbiter_event_address); |
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} |
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return res; |
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} |
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static int mpc83xx_sysreset_get_status(struct udevice *dev, char *buf, int size) |
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{ |
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/* Ad-hoc data structure to map RSR bit values to their descriptions */ |
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static const struct { |
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/* Bit mask for the bit in question */ |
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ulong mask; |
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/* Description of the bitmask in question */ |
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char *desc; |
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} bits[] = { |
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{ |
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RSR_SWSR, "Software Soft"}, { |
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RSR_SWHR, "Software Hard"}, { |
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RSR_JSRS, "JTAG Soft"}, { |
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RSR_CSHR, "Check Stop"}, { |
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RSR_SWRS, "Software Watchdog"}, { |
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RSR_BMRS, "Bus Monitor"}, { |
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RSR_SRS, "External/Internal Soft"}, { |
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RSR_HRS, "External/Internal Hard"} |
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}; |
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int res; |
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ulong rsr = gd->arch.reset_status; |
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int i; |
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char *sep; |
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res = snprintf(buf, size, "Reset Status:"); |
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if (res < 0) { |
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debug("%s: Could not write reset status message (err = %d)\n", |
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dev->name, res); |
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return -EIO; |
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} |
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buf += res; |
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size -= res; |
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sep = " "; |
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for (i = 0; i < ARRAY_SIZE(bits); i++) |
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/* Print description of set bits */ |
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if (rsr & bits[i].mask) { |
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res = snprintf(buf, size, "%s%s%s", sep, bits[i].desc, |
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(i == ARRAY_SIZE(bits) - 1) ? "\n" : ""); |
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if (res < 0) { |
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debug("%s: Could not write reset status message (err = %d)\n", |
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dev->name, res); |
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return -EIO; |
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} |
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buf += res; |
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size -= res; |
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sep = ", "; |
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} |
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/*
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* TODO(mario.six@gdsys.cc): Move this into a dedicated |
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* arbiter driver |
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*/ |
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if (CONFIG_IS_ENABLED(CONFIG_DISPLAY_AER_FULL) || |
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CONFIG_IS_ENABLED(CONFIG_DISPLAY_AER_BRIEF)) { |
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/*
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* If there was a bus monitor reset event, we force the arbiter |
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* event to be printed |
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*/ |
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res = print_83xx_arb_event(rsr & RSR_BMRS, buf, size); |
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if (res < 0) { |
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debug("%s: Could not write arbiter event message (err = %d)\n", |
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dev->name, res); |
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return -EIO; |
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} |
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buf += res; |
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size -= res; |
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} |
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snprintf(buf, size, "\n"); |
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return 0; |
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} |
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static struct sysreset_ops mpc83xx_sysreset = { |
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.request = mpc83xx_sysreset_request, |
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.get_status = mpc83xx_sysreset_get_status, |
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}; |
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U_BOOT_DRIVER(sysreset_mpc83xx) = { |
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.name = "mpc83xx_sysreset", |
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.id = UCLASS_SYSRESET, |
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.ops = &mpc83xx_sysreset, |
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}; |
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@ -0,0 +1,103 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* (C) Copyright 2018 |
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc |
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*/ |
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#ifndef _SYSRESET_MPC83XX_H_ |
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#define _SYSRESET_MPC83XX_H_ |
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/*
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* String array for all possible event types; indexed by the EVENT field of the |
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* AEATR register. |
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*/ |
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static const char * const event[] = { |
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"Address Time Out", |
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"Data Time Out", |
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"Address Only Transfer Type", |
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"External Control Word Transfer Type", |
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"Reserved Transfer Type", |
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"Transfer Error", |
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"reserved", |
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"reserved" |
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}; |
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/*
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* String array for all possible master IDs, which reflects the source of the |
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* transaction that caused the error; indexed by the MSTR_ID field of the AEATR |
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* register. |
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*/ |
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static const char * const master[] = { |
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"e300 Core Data Transaction", |
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"reserved", |
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"e300 Core Instruction Fetch", |
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"reserved", |
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"TSEC1", |
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"TSEC2", |
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"USB MPH", |
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"USB DR", |
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"Encryption Core", |
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"I2C Boot Sequencer", |
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"JTAG", |
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"reserved", |
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"eSDHC", |
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"PCI1", |
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"PCI2", |
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"DMA", |
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"QUICC Engine 00", |
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"QUICC Engine 01", |
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"QUICC Engine 10", |
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"QUICC Engine 11", |
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"reserved", |
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"reserved", |
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"reserved", |
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"reserved", |
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"SATA1", |
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"SATA2", |
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"SATA3", |
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"SATA4", |
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"reserved", |
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"PCI Express 1", |
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"PCI Express 2", |
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"TDM-DMAC" |
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}; |
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/*
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* String array for all possible transfer types; indexed by the TTYPE field of |
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* the AEATR register. |
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*/ |
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static const char * const transfer[] = { |
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"Address-only, Clean Block", |
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"Address-only, lwarx reservation set", |
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"Single-beat or Burst write", |
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"reserved", |
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"Address-only, Flush Block", |
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"reserved", |
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"Burst write", |
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"reserved", |
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"Address-only, sync", |
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"Address-only, tlbsync", |
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"Single-beat or Burst read", |
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"Single-beat or Burst read", |
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"Address-only, Kill Block", |
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"Address-only, icbi", |
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"Burst read", |
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"reserved", |
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"Address-only, eieio", |
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"reserved", |
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"Single-beat write", |
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"reserved", |
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"ecowx - Illegal single-beat write", |
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"reserved", |
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"reserved", |
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"reserved", |
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"Address-only, TLB Invalidate", |
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"reserved", |
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"Single-beat or Burst read", |
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"reserved", |
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"eciwx - Illegal single-beat read", |
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"reserved", |
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"Burst read", |
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"reserved" |
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}; |
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#endif /* _SYSRESET_MPC83XX_H_ */ |
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