[PATCH] Update Yellowstone (440GR) to display board rev and PCI bus speed

Now the board revision and the current PCI bus speed are printed after
the board message.

Also the EBC initialising is now done via defines in the board config
file.

Signed-off-by: Stefan Roese <sr@denx.de>

board/amcc/yellowstone/yellowstone.c

@@ -39,24 +39,6 @@ int board_early_init_f(void)
 	reg = mfdcr(ebccfgd);
 	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
 
-	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
-	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */
-
-	mtebc(pb1ap, 0x00000000);
-	mtebc(pb1cr, 0x00000000);
-
-	mtebc(pb2ap, 0x04814500);
-	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */
-
-	mtebc(pb3ap, 0x00000000);
-	mtebc(pb3cr, 0x00000000);
-
-	mtebc(pb4ap, 0x00000000);
-	mtebc(pb4cr, 0x00000000);
-
-	mtebc(pb5ap, 0x00000000);
-	mtebc(pb5cr, 0x00000000);
-
 	/*--------------------------------------------------------------------
 	 * Setup the GPIO pins
 	 *-------------------------------------------------------------------*/
@@ -190,8 +172,15 @@ int misc_init_r (void)
 int checkboard(void)
 {
 	char *s = getenv("serial#");
+	u8 rev;
+	u8 val;
 
 	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
+
+	rev = *(u8 *)(CFG_CPLD + 0);
+	val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+
 	if (s != NULL) {
 		puts(", serial# ");
 		puts(s);

include/configs/yellowstone.h

@@ -302,6 +302,20 @@
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH		CFG_FLASH_BASE
+#define CFG_CPLD		0x80000000
+
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x03017300
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0xda000)
+
+/* Memory Bank 2 (CPLD) initialization						*/
+#define CFG_EBC_PB2AP		0x04814500
+#define CFG_EBC_PB2CR		(CFG_CPLD | 0x18000)
+
+/*-----------------------------------------------------------------------
  * Cache Configuration
  */
 #define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/