Tom Rini
11 years ago
commit
77fdd6d1eb
@ -0,0 +1,142 @@ |
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/fsl_portals.h> |
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#include <asm/fsl_liodn.h> |
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#ifdef CONFIG_SYS_DPAA_QBMAN |
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struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { |
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/* dqrr liodn, frame data liodn, liodn off, sdest */ |
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SET_QP_INFO(1, 27, 1, 0), |
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SET_QP_INFO(2, 28, 1, 0), |
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SET_QP_INFO(3, 29, 1, 1), |
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SET_QP_INFO(4, 30, 1, 1), |
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SET_QP_INFO(5, 31, 1, 2), |
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SET_QP_INFO(6, 32, 1, 2), |
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SET_QP_INFO(7, 33, 1, 3), |
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SET_QP_INFO(8, 34, 1, 3), |
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SET_QP_INFO(9, 35, 1, 0), |
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SET_QP_INFO(10, 36, 1, 0), |
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SET_QP_INFO(11, 37, 1, 1), |
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SET_QP_INFO(12, 38, 1, 1), |
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SET_QP_INFO(13, 39, 1, 2), |
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SET_QP_INFO(14, 40, 1, 2), |
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SET_QP_INFO(15, 41, 1, 3), |
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SET_QP_INFO(16, 42, 1, 3), |
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SET_QP_INFO(17, 43, 1, 0), |
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SET_QP_INFO(18, 44, 1, 0), |
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}; |
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#endif |
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#ifdef CONFIG_SYS_SRIO |
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struct srio_liodn_id_table srio_liodn_tbl[] = { |
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SET_SRIO_LIODN_BASE(1, 307), |
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SET_SRIO_LIODN_BASE(2, 387), |
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}; |
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int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); |
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#endif |
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struct liodn_id_table liodn_tbl[] = { |
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#ifdef CONFIG_SYS_DPAA_QBMAN |
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SET_QMAN_LIODN(62), |
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SET_BMAN_LIODN(63), |
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#endif |
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SET_SDHC_LIODN(1, 552), |
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SET_PME_LIODN(117), |
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SET_USB_LIODN(1, "fsl-usb2-mph", 553), |
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SET_USB_LIODN(2, "fsl-usb2-dr", 554), |
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SET_SATA_LIODN(1, 555), |
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SET_SATA_LIODN(2, 556), |
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), |
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), |
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), |
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), |
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SET_DMA_LIODN(1, 147), |
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SET_DMA_LIODN(2, 227), |
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SET_DMA_LIODN(3, 226), |
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SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), |
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SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), |
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SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), |
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SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), |
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#ifdef CONFIG_SYS_PMAN |
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SET_PMAN_LIODN(1, 513), |
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SET_PMAN_LIODN(2, 514), |
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SET_PMAN_LIODN(3, 515), |
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#endif |
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/* SET_NEXUS_LIODN(557), -- not yet implemented */ |
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}; |
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int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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struct liodn_id_table fman1_liodn_tbl[] = { |
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SET_FMAN_RX_1G_LIODN(1, 0, 88), |
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SET_FMAN_RX_1G_LIODN(1, 1, 89), |
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SET_FMAN_RX_1G_LIODN(1, 2, 90), |
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SET_FMAN_RX_1G_LIODN(1, 3, 91), |
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SET_FMAN_RX_1G_LIODN(1, 4, 92), |
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SET_FMAN_RX_1G_LIODN(1, 5, 93), |
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SET_FMAN_RX_10G_LIODN(1, 0, 94), |
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SET_FMAN_RX_10G_LIODN(1, 1, 95), |
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}; |
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int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); |
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#endif |
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struct liodn_id_table sec_liodn_tbl[] = { |
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SET_SEC_JR_LIODN_ENTRY(0, 454, 458), |
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SET_SEC_JR_LIODN_ENTRY(1, 455, 459), |
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SET_SEC_JR_LIODN_ENTRY(2, 456, 460), |
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SET_SEC_JR_LIODN_ENTRY(3, 457, 461), |
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SET_SEC_RTIC_LIODN_ENTRY(a, 453), |
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SET_SEC_RTIC_LIODN_ENTRY(b, 549), |
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SET_SEC_RTIC_LIODN_ENTRY(c, 550), |
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SET_SEC_RTIC_LIODN_ENTRY(d, 551), |
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SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), |
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SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), |
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SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), |
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SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), |
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SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), |
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SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), |
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SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), |
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SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), |
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}; |
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int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); |
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#ifdef CONFIG_SYS_DPAA_RMAN |
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struct liodn_id_table rman_liodn_tbl[] = { |
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/* Set RMan block 0-3 liodn offset */ |
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SET_RMAN_LIODN(0, 6), |
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SET_RMAN_LIODN(1, 7), |
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SET_RMAN_LIODN(2, 8), |
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SET_RMAN_LIODN(3, 9), |
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}; |
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int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); |
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#endif |
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struct liodn_id_table liodn_bases[] = { |
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#ifdef CONFIG_SYS_DPAA_DCE |
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[FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694), |
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#endif |
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[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), |
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#endif |
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#ifdef CONFIG_SYS_DPAA_PME |
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[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), |
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#endif |
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#ifdef CONFIG_SYS_DPAA_RMAN |
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[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), |
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#endif |
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}; |
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@ -0,0 +1,208 @@ |
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* Shengzhou Liu <Shengzhou.Liu@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/fsl_serdes.h> |
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#include <asm/processor.h> |
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#include "fsl_corenet2_serdes.h" |
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struct serdes_config { |
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u32 protocol; |
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u8 lanes[SRDS_MAX_LANES]; |
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}; |
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static const struct serdes_config serdes1_cfg_tbl[] = { |
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/* SerDes 1 */ |
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{0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, |
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{0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, PCIE4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, PCIE4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xDE, {PCIE3, PCIE3, PCIE3, PCIE3, |
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PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, |
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{0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, |
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PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, |
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{0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, |
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{0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, PCIE1, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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PCIE4, PCIE4, PCIE4, PCIE4} }, |
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#if defined(CONFIG_PPC_T2080) |
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{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, |
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XAUI_FM1_MAC9, XAUI_FM1_MAC9, |
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PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, |
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, |
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PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, |
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, |
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PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10, |
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XFI_FM1_MAC1, XFI_FM1_MAC2, |
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PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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PCIE4, PCIE4, PCIE4, PCIE4} }, |
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{0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, |
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SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, |
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PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, |
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PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, |
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PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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PCIE4, PCIE4, PCIE4, PCIE4} }, |
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{0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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PCIE4, PCIE4, PCIE4, PCIE4} }, |
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{0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, |
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
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PCIE4, PCIE4, PCIE4, PCIE4} }, |
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{0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10, |
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XFI_FM1_MAC1, XFI_FM1_MAC2, |
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PCIE4, PCIE4, PCIE4, PCIE4} }, |
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{0xAB, {PCIE3, PCIE3, PCIE3, PCIE3, |
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PCIE4, PCIE4, PCIE4, PCIE4} }, |
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{0xDA, {PCIE3, PCIE3, PCIE3, PCIE3, |
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PCIE3, PCIE3, PCIE3, PCIE3} }, |
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{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10, |
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XFI_FM1_MAC1, XFI_FM1_MAC2, |
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PCIE4, PCIE4, PCIE4, PCIE4} }, |
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#elif defined(CONFIG_PPC_T2081) |
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{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, |
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PCIE4, PCIE4, PCIE4, PCIE4} }, |
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{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, |
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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#endif |
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{} |
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}; |
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|
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#ifndef CONFIG_PPC_T2081 |
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static const struct serdes_config serdes2_cfg_tbl[] = { |
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/* SerDes 2 */ |
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{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, |
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{0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, |
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{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, |
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{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, |
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{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, |
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{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, |
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{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, |
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{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, |
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{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, |
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{} |
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}; |
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#endif |
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static const struct serdes_config *serdes_cfg_tbl[] = { |
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serdes1_cfg_tbl, |
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#ifndef CONFIG_PPC_T2081 |
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serdes2_cfg_tbl, |
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#endif |
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}; |
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) |
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{ |
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const struct serdes_config *ptr; |
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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ptr = serdes_cfg_tbl[serdes]; |
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while (ptr->protocol) { |
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if (ptr->protocol == cfg) |
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return ptr->lanes[lane]; |
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ptr++; |
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} |
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return 0; |
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} |
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int is_serdes_prtcl_valid(int serdes, u32 prtcl) |
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{ |
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int i; |
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const struct serdes_config *ptr; |
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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ptr = serdes_cfg_tbl[serdes]; |
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while (ptr->protocol) { |
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if (ptr->protocol == prtcl) |
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break; |
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ptr++; |
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} |
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if (!ptr->protocol) |
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return 0; |
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for (i = 0; i < SRDS_MAX_LANES; i++) { |
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if (ptr->lanes[i] != NONE) |
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return 1; |
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} |
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return 0; |
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} |
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@ -1,29 +0,0 @@ |
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#
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# Copyright 2008-2011 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
|
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# Version 2 as published by the Free Software Foundation.
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#
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||||
|
||||
obj-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
|
||||
lc_common_dimm_params.o
|
||||
|
||||
obj-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
|
||||
lc_common_dimm_params.o
|
||||
|
||||
obj-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
|
||||
lc_common_dimm_params.o
|
||||
ifdef CONFIG_DDR_SPD |
||||
SPD := y
|
||||
endif |
||||
ifdef CONFIG_SPD_EEPROM |
||||
SPD := y
|
||||
endif |
||||
ifdef SPD |
||||
obj-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
|
||||
obj-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
|
||||
obj-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o
|
||||
endif |
||||
|
||||
obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
|
||||
@ -0,0 +1,12 @@ |
||||
#
|
||||
# Copyright 2013 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_T2080QDS) += t2080qds.o
|
||||
obj-$(CONFIG_T2080QDS) += eth_t2080qds.o
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
obj-y += ddr.o
|
||||
obj-y += law.o
|
||||
obj-y += tlb.o
|
||||
@ -0,0 +1,127 @@ |
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License |
||||
* Version 2 or later as published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <hwconfig.h> |
||||
#include <asm/mmu.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <fsl_ddr_dimm_params.h> |
||||
#include <asm/fsl_law.h> |
||||
#include "ddr.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
||||
ulong ddr_freq; |
||||
|
||||
if (ctrl_num > 2) { |
||||
printf("Not supported controller number %d\n", ctrl_num); |
||||
return; |
||||
} |
||||
if (!pdimm->n_ranks) |
||||
return; |
||||
|
||||
/*
|
||||
* we use identical timing for all slots. If needed, change the code |
||||
* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; |
||||
*/ |
||||
if (popts->registered_dimm_en) |
||||
pbsp = rdimms[0]; |
||||
else |
||||
pbsp = udimms[0]; |
||||
|
||||
|
||||
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
|
||||
* freqency and n_banks specified in board_specific_parameters table. |
||||
*/ |
||||
ddr_freq = get_ddr_freq(0) / 1000000; |
||||
while (pbsp->datarate_mhz_high) { |
||||
if (pbsp->n_ranks == pdimm->n_ranks && |
||||
(pdimm->rank_density >> 30) >= pbsp->rank_gb) { |
||||
if (ddr_freq <= pbsp->datarate_mhz_high) { |
||||
popts->cpo_override = pbsp->cpo; |
||||
popts->write_data_delay = |
||||
pbsp->write_data_delay; |
||||
popts->clk_adjust = pbsp->clk_adjust; |
||||
popts->wrlvl_start = pbsp->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
popts->twot_en = pbsp->force_2t; |
||||
goto found; |
||||
} |
||||
pbsp_highest = pbsp; |
||||
} |
||||
pbsp++; |
||||
} |
||||
|
||||
if (pbsp_highest) { |
||||
printf("Error: board specific timing not found"); |
||||
printf("for data rate %lu MT/s\n", ddr_freq); |
||||
printf("Trying to use the highest speed (%u) parameters\n", |
||||
pbsp_highest->datarate_mhz_high); |
||||
popts->cpo_override = pbsp_highest->cpo; |
||||
popts->write_data_delay = pbsp_highest->write_data_delay; |
||||
popts->clk_adjust = pbsp_highest->clk_adjust; |
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
popts->twot_en = pbsp_highest->force_2t; |
||||
} else { |
||||
panic("DIMM is not supported by this board"); |
||||
} |
||||
found: |
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" |
||||
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " |
||||
"wrlvl_ctrl_3 0x%x\n", |
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, |
||||
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, |
||||
pbsp->wrlvl_ctl_3); |
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable: |
||||
* - number of DIMMs installed |
||||
*/ |
||||
popts->half_strength_driver_enable = 0; |
||||
/*
|
||||
* Write leveling override |
||||
*/ |
||||
popts->wrlvl_override = 1; |
||||
popts->wrlvl_sample = 0xf; |
||||
|
||||
/*
|
||||
* Rtt and Rtt_WR override |
||||
*/ |
||||
popts->rtt_override = 0; |
||||
|
||||
/* Enable ZQ calibration */ |
||||
popts->zq_en = 1; |
||||
|
||||
/* DHC_EN =1, ODT = 75 Ohm */ |
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); |
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
phys_size_t dram_size; |
||||
|
||||
puts("Initializing....using SPD\n"); |
||||
|
||||
dram_size = fsl_ddr_sdram(); |
||||
|
||||
dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
||||
dram_size *= 0x100000; |
||||
|
||||
puts(" DDR: "); |
||||
return dram_size; |
||||
} |
||||
@ -0,0 +1,85 @@ |
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __DDR_H__ |
||||
#define __DDR_H__ |
||||
struct board_specific_parameters { |
||||
u32 n_ranks; |
||||
u32 datarate_mhz_high; |
||||
u32 rank_gb; |
||||
u32 clk_adjust; |
||||
u32 wrlvl_start; |
||||
u32 wrlvl_ctl_2; |
||||
u32 wrlvl_ctl_3; |
||||
u32 cpo; |
||||
u32 write_data_delay; |
||||
u32 force_2t; |
||||
}; |
||||
|
||||
/*
|
||||
* These tables contain all valid speeds we want to override with board |
||||
* specific parameters. datarate_mhz_high values need to be in ascending order |
||||
* for each n_ranks group. |
||||
*/ |
||||
|
||||
static const struct board_specific_parameters udimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
||||
*/ |
||||
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
||||
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, |
||||
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, |
||||
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, |
||||
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
||||
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
||||
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
||||
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
||||
{1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0}, |
||||
{1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, |
||||
{1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, |
||||
{1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, |
||||
{1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, |
||||
{} |
||||
}; |
||||
|
||||
static const struct board_specific_parameters rdimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
||||
*/ |
||||
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, |
||||
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, |
||||
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, |
||||
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, |
||||
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, |
||||
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, |
||||
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, |
||||
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, |
||||
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, |
||||
{} |
||||
}; |
||||
|
||||
/*
|
||||
* The three slots have slightly different timing. The center values are good |
||||
* for all slots. We use identical speed tables for them. In future use, if |
||||
* DIMMs require separated tables, make more entries as needed. |
||||
*/ |
||||
static const struct board_specific_parameters *udimms[] = { |
||||
udimm0, |
||||
}; |
||||
|
||||
/*
|
||||
* The three slots have slightly different timing. See comments above. |
||||
*/ |
||||
static const struct board_specific_parameters *rdimms[] = { |
||||
rdimm0, |
||||
}; |
||||
|
||||
|
||||
#endif |
||||
@ -0,0 +1,511 @@ |
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* Shengzhou Liu <Shengzhou.Liu@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <netdev.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
#include <malloc.h> |
||||
#include <fm_eth.h> |
||||
#include <fsl_mdio.h> |
||||
#include <miiphy.h> |
||||
#include <phy.h> |
||||
#include <asm/fsl_dtsec.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include "../common/qixis.h" |
||||
#include "../common/fman.h" |
||||
#include "t2080qds_qixis.h" |
||||
|
||||
#define EMI_NONE 0xFFFFFFFF |
||||
#define EMI1_RGMII1 0 |
||||
#define EMI1_RGMII2 1 |
||||
#define EMI1_SLOT1 2 |
||||
#define EMI1_SLOT2 6 |
||||
#define EMI1_SLOT3 3 |
||||
#define EMI1_SLOT4 4 |
||||
#define EMI1_SLOT5 5 |
||||
#define EMI2 7 |
||||
|
||||
static int mdio_mux[NUM_FM_PORTS]; |
||||
|
||||
static const char * const mdio_names[] = { |
||||
"T2080QDS_MDIO_RGMII1", |
||||
"T2080QDS_MDIO_RGMII2", |
||||
"T2080QDS_MDIO_SLOT1", |
||||
"T2080QDS_MDIO_SLOT3", |
||||
"T2080QDS_MDIO_SLOT4", |
||||
"T2080QDS_MDIO_SLOT5", |
||||
"T2080QDS_MDIO_SLOT2", |
||||
"T2080QDS_MDIO_10GC", |
||||
}; |
||||
|
||||
/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ |
||||
static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; |
||||
|
||||
static const char *T2080qds_mdio_name_for_muxval(u8 muxval) |
||||
{ |
||||
return mdio_names[muxval]; |
||||
} |
||||
|
||||
struct mii_dev *mii_dev_for_muxval(u8 muxval) |
||||
{ |
||||
struct mii_dev *bus; |
||||
const char *name = T2080qds_mdio_name_for_muxval(muxval); |
||||
|
||||
if (!name) { |
||||
printf("No bus for muxval %x\n", muxval); |
||||
return NULL; |
||||
} |
||||
|
||||
bus = miiphy_get_dev_by_name(name); |
||||
|
||||
if (!bus) { |
||||
printf("No bus by name %s\n", name); |
||||
return NULL; |
||||
} |
||||
|
||||
return bus; |
||||
} |
||||
|
||||
struct T2080qds_mdio { |
||||
u8 muxval; |
||||
struct mii_dev *realbus; |
||||
}; |
||||
|
||||
static void T2080qds_mux_mdio(u8 muxval) |
||||
{ |
||||
u8 brdcfg4; |
||||
if (muxval < 7) { |
||||
brdcfg4 = QIXIS_READ(brdcfg[4]); |
||||
brdcfg4 &= ~BRDCFG4_EMISEL_MASK; |
||||
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); |
||||
QIXIS_WRITE(brdcfg[4], brdcfg4); |
||||
} |
||||
} |
||||
|
||||
static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad, |
||||
int regnum) |
||||
{ |
||||
struct T2080qds_mdio *priv = bus->priv; |
||||
|
||||
T2080qds_mux_mdio(priv->muxval); |
||||
|
||||
return priv->realbus->read(priv->realbus, addr, devad, regnum); |
||||
} |
||||
|
||||
static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad, |
||||
int regnum, u16 value) |
||||
{ |
||||
struct T2080qds_mdio *priv = bus->priv; |
||||
|
||||
T2080qds_mux_mdio(priv->muxval); |
||||
|
||||
return priv->realbus->write(priv->realbus, addr, devad, regnum, value); |
||||
} |
||||
|
||||
static int T2080qds_mdio_reset(struct mii_dev *bus) |
||||
{ |
||||
struct T2080qds_mdio *priv = bus->priv; |
||||
|
||||
return priv->realbus->reset(priv->realbus); |
||||
} |
||||
|
||||
static int T2080qds_mdio_init(char *realbusname, u8 muxval) |
||||
{ |
||||
struct T2080qds_mdio *pmdio; |
||||
struct mii_dev *bus = mdio_alloc(); |
||||
|
||||
if (!bus) { |
||||
printf("Failed to allocate T2080QDS MDIO bus\n"); |
||||
return -1; |
||||
} |
||||
|
||||
pmdio = malloc(sizeof(*pmdio)); |
||||
if (!pmdio) { |
||||
printf("Failed to allocate T2080QDS private data\n"); |
||||
free(bus); |
||||
return -1; |
||||
} |
||||
|
||||
bus->read = T2080qds_mdio_read; |
||||
bus->write = T2080qds_mdio_write; |
||||
bus->reset = T2080qds_mdio_reset; |
||||
sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval)); |
||||
|
||||
pmdio->realbus = miiphy_get_dev_by_name(realbusname); |
||||
|
||||
if (!pmdio->realbus) { |
||||
printf("No bus with name %s\n", realbusname); |
||||
free(bus); |
||||
free(pmdio); |
||||
return -1; |
||||
} |
||||
|
||||
pmdio->muxval = muxval; |
||||
bus->priv = pmdio; |
||||
|
||||
return mdio_register(bus); |
||||
} |
||||
|
||||
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, |
||||
enum fm_port port, int offset) |
||||
{ |
||||
int phy; |
||||
char alias[20]; |
||||
struct fixed_link f_link; |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
|
||||
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
|
||||
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { |
||||
phy = fm_info_get_phy_address(port); |
||||
switch (port) { |
||||
case FM1_DTSEC1: |
||||
case FM1_DTSEC2: |
||||
case FM1_DTSEC9: |
||||
case FM1_DTSEC10: |
||||
sprintf(alias, "phy_sgmii_s3_%x", phy); |
||||
fdt_set_phy_handle(fdt, compat, addr, alias); |
||||
fdt_status_okay_by_alias(fdt, "emi1_slot3"); |
||||
break; |
||||
case FM1_DTSEC5: |
||||
case FM1_DTSEC6: |
||||
if (mdio_mux[port] == EMI1_SLOT1) { |
||||
sprintf(alias, "phy_sgmii_s1_%x", phy); |
||||
fdt_set_phy_handle(fdt, compat, addr, alias); |
||||
fdt_status_okay_by_alias(fdt, "emi1_slot1"); |
||||
} else if (mdio_mux[port] == EMI1_SLOT2) { |
||||
sprintf(alias, "phy_sgmii_s2_%x", phy); |
||||
fdt_set_phy_handle(fdt, compat, addr, alias); |
||||
fdt_status_okay_by_alias(fdt, "emi1_slot2"); |
||||
} |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
|
||||
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { |
||||
switch (srds_s1) { |
||||
case 0x66: /* XFI interface */ |
||||
case 0x6b: |
||||
case 0x6c: |
||||
case 0x6d: |
||||
case 0x71: |
||||
f_link.phy_id = port; |
||||
f_link.duplex = 1; |
||||
f_link.link_speed = 10000; |
||||
f_link.pause = 0; |
||||
f_link.asym_pause = 0; |
||||
/* no PHY for XFI */ |
||||
fdt_delprop(fdt, offset, "phy-handle"); |
||||
fdt_setprop(fdt, offset, "fixed-link", &f_link, |
||||
sizeof(f_link)); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
void fdt_fixup_board_enet(void *fdt) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* This function reads RCW to check if Serdes1{E,F,G,H} is configured |
||||
* as slot 1/2/3 and update the lane_to_slot[] array accordingly |
||||
*/ |
||||
static void initialize_lane_to_slot(void) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
|
||||
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
|
||||
switch (srds_s1) { |
||||
case 0x51: |
||||
case 0x5f: |
||||
case 0x65: |
||||
case 0x6b: |
||||
case 0x71: |
||||
lane_to_slot[5] = 2; |
||||
lane_to_slot[6] = 2; |
||||
lane_to_slot[7] = 2; |
||||
break; |
||||
case 0xa6: |
||||
case 0x8e: |
||||
case 0x8f: |
||||
case 0x82: |
||||
case 0x83: |
||||
case 0xd3: |
||||
case 0xd9: |
||||
case 0xcb: |
||||
lane_to_slot[6] = 2; |
||||
lane_to_slot[7] = 2; |
||||
break; |
||||
case 0xda: |
||||
lane_to_slot[4] = 3; |
||||
lane_to_slot[5] = 3; |
||||
lane_to_slot[6] = 3; |
||||
lane_to_slot[7] = 3; |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
#if defined(CONFIG_FMAN_ENET) |
||||
int i, idx, lane, slot, interface; |
||||
struct memac_mdio_info dtsec_mdio_info; |
||||
struct memac_mdio_info tgec_mdio_info; |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 rcwsr13 = in_be32(&gur->rcwsr[13]); |
||||
u32 srds_s1; |
||||
|
||||
srds_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
|
||||
initialize_lane_to_slot(); |
||||
|
||||
/* Initialize the mdio_mux array so we can recognize empty elements */ |
||||
for (i = 0; i < NUM_FM_PORTS; i++) |
||||
mdio_mux[i] = EMI_NONE; |
||||
|
||||
dtsec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; |
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
||||
|
||||
/* Register the 1G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info); |
||||
|
||||
tgec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; |
||||
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; |
||||
|
||||
/* Register the 10G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &tgec_mdio_info); |
||||
|
||||
/* Register the muxing front-ends to the MDIO buses */ |
||||
T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); |
||||
T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); |
||||
T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); |
||||
T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); |
||||
T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); |
||||
T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); |
||||
T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); |
||||
T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); |
||||
|
||||
/* Set the two on-board RGMII PHY address */ |
||||
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); |
||||
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == |
||||
FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) |
||||
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); |
||||
else |
||||
fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); |
||||
|
||||
switch (srds_s1) { |
||||
case 0x1c: |
||||
case 0x95: |
||||
case 0xa2: |
||||
case 0x94: |
||||
/* SGMII in Slot3 */ |
||||
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); |
||||
/* SGMII in Slot2 */ |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); |
||||
break; |
||||
case 0x51: |
||||
case 0x5f: |
||||
case 0x65: |
||||
/* XAUI/HiGig in Slot3 */ |
||||
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); |
||||
/* SGMII in Slot2 */ |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); |
||||
break; |
||||
case 0x66: |
||||
/*
|
||||
* XFI does not need a PHY to work, but to avoid U-boot use |
||||
* default PHY address which is zero to a MAC when it found |
||||
* a MAC has no PHY address, we give a PHY address to XFI |
||||
* MAC, and should not use a real XAUI PHY address, since |
||||
* MDIO can access it successfully, and then MDIO thinks |
||||
* the XAUI card is used for the XFI MAC, which will cause |
||||
* error. |
||||
*/ |
||||
fm_info_set_phy_address(FM1_10GEC1, 4); |
||||
fm_info_set_phy_address(FM1_10GEC2, 5); |
||||
fm_info_set_phy_address(FM1_10GEC3, 6); |
||||
fm_info_set_phy_address(FM1_10GEC4, 7); |
||||
break; |
||||
case 0x6b: |
||||
fm_info_set_phy_address(FM1_10GEC1, 4); |
||||
fm_info_set_phy_address(FM1_10GEC2, 5); |
||||
fm_info_set_phy_address(FM1_10GEC3, 6); |
||||
fm_info_set_phy_address(FM1_10GEC4, 7); |
||||
/* SGMII in Slot2 */ |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); |
||||
break; |
||||
case 0x6c: |
||||
case 0x6d: |
||||
/* SGMII in Slot3 */ |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); |
||||
break; |
||||
case 0x71: |
||||
/* SGMII in Slot3 */ |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); |
||||
/* SGMII in Slot2 */ |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); |
||||
break; |
||||
case 0xa6: |
||||
case 0x8e: |
||||
case 0x8f: |
||||
case 0x82: |
||||
case 0x83: |
||||
/* SGMII in Slot3 */ |
||||
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); |
||||
/* SGMII in Slot2 */ |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); |
||||
break; |
||||
case 0xa4: |
||||
case 0x96: |
||||
case 0x8a: |
||||
/* SGMII in Slot3 */ |
||||
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); |
||||
break; |
||||
case 0xd9: |
||||
case 0xd3: |
||||
case 0xcb: |
||||
/* SGMII in Slot3 */ |
||||
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); |
||||
/* SGMII in Slot2 */ |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); |
||||
break; |
||||
default: |
||||
puts("Invalid SerDes1 protocol for T2080QDS\n"); |
||||
break; |
||||
} |
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
||||
idx = i - FM1_DTSEC1; |
||||
interface = fm_info_get_enet_if(i); |
||||
switch (interface) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
SGMII_FM1_DTSEC1 + idx); |
||||
if (lane < 0) |
||||
break; |
||||
slot = lane_to_slot[lane]; |
||||
debug("FM1@DTSEC%u expects SGMII in slot %u\n", |
||||
idx + 1, slot); |
||||
if (QIXIS_READ(present2) & (1 << (slot - 1))) |
||||
fm_disable_port(i); |
||||
|
||||
switch (slot) { |
||||
case 1: |
||||
mdio_mux[i] = EMI1_SLOT1; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval( |
||||
mdio_mux[i])); |
||||
break; |
||||
case 2: |
||||
mdio_mux[i] = EMI1_SLOT2; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval( |
||||
mdio_mux[i])); |
||||
break; |
||||
}; |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
if (i == FM1_DTSEC3) |
||||
mdio_mux[i] = EMI1_RGMII1; |
||||
else if (i == FM1_DTSEC4 || FM1_DTSEC10) |
||||
mdio_mux[i] = EMI1_RGMII2; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { |
||||
idx = i - FM1_10GEC1; |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_XGMII: |
||||
if (srds_s1 == 0x51) { |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
XAUI_FM1_MAC9 + idx); |
||||
} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
HIGIG_FM1_MAC9 + idx); |
||||
} else { |
||||
if (i == FM1_10GEC1 || i == FM1_10GEC2) |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
XFI_FM1_MAC9 + idx); |
||||
else |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
XFI_FM1_MAC1 + idx); |
||||
} |
||||
|
||||
if (lane < 0) |
||||
break; |
||||
mdio_mux[i] = EMI2; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); |
||||
|
||||
if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || |
||||
(srds_s1 == 0x6c) || (srds_s1 == 0x6d) || |
||||
(srds_s1 == 0x71)) { |
||||
/* As XFI is in cage intead of a slot, so
|
||||
* ensure doesn't disable the corresponding port |
||||
*/ |
||||
break; |
||||
} |
||||
|
||||
slot = lane_to_slot[lane]; |
||||
if (QIXIS_READ(present2) & (1 << (slot - 1))) |
||||
fm_disable_port(i); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
cpu_eth_init(bis); |
||||
#endif /* CONFIG_FMAN_ENET */ |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
||||
@ -0,0 +1,34 @@ |
||||
/*
|
||||
* Copyright 2008-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), |
||||
#endif |
||||
#ifdef QIXIS_BASE_PHYS |
||||
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
/* Limit DCSR to 32M to access NPC Trace Buffer */ |
||||
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS |
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,23 @@ |
||||
/*
|
||||
* Copyright 2007-2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <pci.h> |
||||
#include <asm/fsl_pci.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/fsl_serdes.h> |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
fsl_pcie_init_board(0); |
||||
} |
||||
|
||||
void pci_of_setup(void *blob, bd_t *bd) |
||||
{ |
||||
FT_FSL_PCI_SETUP; |
||||
} |
||||
@ -0,0 +1,41 @@ |
||||
# |
||||
# Copyright 2013 Freescale Semiconductor, Inc. |
||||
# |
||||
# SPDX-License-Identifier: GPL-2.0+ |
||||
# |
||||
# Refer doc/README.pblimage for more details about how-to configure |
||||
# and create PBL boot image |
||||
# |
||||
|
||||
#PBI commands |
||||
#Initialize CPC1 |
||||
09010000 00200400 |
||||
09138000 00000000 |
||||
091380c0 00000100 |
||||
#512KB SRAM |
||||
09010100 00000000 |
||||
09010104 fff80009 |
||||
09010f00 08000000 |
||||
#enable CPC1 |
||||
09010000 80000000 |
||||
#Configure LAW for CPC1 |
||||
09000d00 00000000 |
||||
09000d04 fff80000 |
||||
09000d08 81000012 |
||||
#Initialize eSPI controller, default configuration is slow for eSPI to |
||||
#load data, this configuration comes from u-boot eSPI driver. |
||||
09110000 80000403 |
||||
09110020 2d170008 |
||||
09110024 00100008 |
||||
09110028 00100008 |
||||
0911002c 00100008 |
||||
#Errata for slowing down the MDC clock to make it <= 2.5 MHZ |
||||
094fc030 00008148 |
||||
094fd030 00008148 |
||||
#Configure alternate space |
||||
09000010 00000000 |
||||
09000014 ff000000 |
||||
09000018 81000000 |
||||
#Flush PBL data |
||||
09138000 00000000 |
||||
091380c0 00000000 |
||||
@ -0,0 +1,8 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 010e0100 |
||||
#SerDes Protocol: 0x66_0x16 |
||||
#Core/DDR: 1533Mhz/2133MT/s |
||||
12100017 15000000 00000000 00000000 |
||||
66160002 00008400 e8104000 c1000000 |
||||
00000000 00000000 00000000 000307fc |
||||
00000000 00000000 00000000 00000004 |
||||
@ -0,0 +1,324 @@ |
||||
/*
|
||||
* Copyright 2009-2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <i2c.h> |
||||
#include <netdev.h> |
||||
#include <linux/compiler.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
#include <fm_eth.h> |
||||
|
||||
#include "../common/qixis.h" |
||||
#include "../common/vsc3316_3308.h" |
||||
#include "t2080qds.h" |
||||
#include "t2080qds_qixis.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
char buf[64]; |
||||
u8 sw; |
||||
struct cpu_type *cpu = gd->arch.cpu; |
||||
static const char *freq[4] = { |
||||
"100.00MHZ(from 8T49N222A)", "125.00MHz", |
||||
"156.25MHZ", "100.00MHz" |
||||
}; |
||||
|
||||
printf("Board: %sQDS, ", cpu->name); |
||||
sw = QIXIS_READ(arch); |
||||
printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); |
||||
printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); |
||||
|
||||
sw = QIXIS_READ(brdcfg[0]); |
||||
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
||||
|
||||
if (sw < 0x8) |
||||
printf("vBank%d\n", sw); |
||||
else if (sw == 0x8) |
||||
puts("Promjet\n"); |
||||
else if (sw == 0x9) |
||||
puts("NAND\n"); |
||||
else |
||||
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
||||
|
||||
printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), |
||||
qixis_read_tag(buf), (int)qixis_read_minor()); |
||||
/* the timestamp string contains "\n" at the end */ |
||||
printf(" on %s", qixis_read_time(buf)); |
||||
|
||||
puts("SERDES Reference Clocks:\n"); |
||||
sw = QIXIS_READ(brdcfg[2]); |
||||
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], |
||||
freq[(sw >> 4) & 0x3]); |
||||
printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], |
||||
freq[sw & 0x3]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int select_i2c_ch_pca9547(u8 ch) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
||||
if (ret) { |
||||
puts("PCA: failed to select proper channel\n"); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int brd_mux_lane_to_slot(void) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_prtcl_s1, srds_prtcl_s2; |
||||
|
||||
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS2_PRTCL; |
||||
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; |
||||
|
||||
switch (srds_prtcl_s1) { |
||||
case 0: |
||||
/* SerDes1 is not enabled */ |
||||
break; |
||||
case 0x1c: |
||||
case 0x95: |
||||
case 0xa2: |
||||
case 0x94: |
||||
/* SD1(A:D) => SLOT3 SGMII
|
||||
* SD1(G:H) => SLOT1 SGMII |
||||
*/ |
||||
QIXIS_WRITE(brdcfg[12], 0x58); |
||||
break; |
||||
case 0x51: |
||||
/* SD1(A:D) => SLOT3 XAUI
|
||||
* SD1(E) => SLOT1 PCIe4 |
||||
* SD1(F:H) => SLOT2 SGMII |
||||
*/ |
||||
QIXIS_WRITE(brdcfg[12], 0x15); |
||||
break; |
||||
case 0x66: |
||||
case 0x67: |
||||
/* SD1(A:D) => XFI cage
|
||||
* SD1(E:H) => SLOT1 PCIe4 |
||||
*/ |
||||
QIXIS_WRITE(brdcfg[12], 0xfe); |
||||
break; |
||||
case 0x6b: |
||||
/* SD1(A:D) => XFI cage
|
||||
* SD1(E) => SLOT1 PCIe4 |
||||
* SD1(F:H) => SLOT2 SGMII |
||||
*/ |
||||
QIXIS_WRITE(brdcfg[12], 0xf1); |
||||
break; |
||||
case 0x6c: |
||||
case 0x6d: |
||||
/* SD1(A:B) => XFI cage
|
||||
* SD1(C:D) => SLOT3 SGMII |
||||
* SD1(E:H) => SLOT1 PCIe4 |
||||
*/ |
||||
QIXIS_WRITE(brdcfg[12], 0xda); |
||||
break; |
||||
default: |
||||
printf("WARNING: unsupported for SerDes1 Protocol %d\n", |
||||
srds_prtcl_s1); |
||||
return -1; |
||||
} |
||||
|
||||
switch (srds_prtcl_s2) { |
||||
case 0: |
||||
/* SerDes2 is not enabled */ |
||||
break; |
||||
case 0x01: |
||||
case 0x02: |
||||
/* SD2(A:H) => SLOT4 PCIe1 */ |
||||
QIXIS_WRITE(brdcfg[13], 0x20); |
||||
break; |
||||
case 0x15: |
||||
case 0x16: |
||||
/*
|
||||
* SD2(A:D) => SLOT4 PCIe1 |
||||
* SD2(E:F) => SLOT5 PCIe2 |
||||
* SD2(G:H) => SATA1,SATA2 |
||||
*/ |
||||
QIXIS_WRITE(brdcfg[13], 0xb0); |
||||
break; |
||||
case 0x18: |
||||
/*
|
||||
* SD2(A:D) => SLOT4 PCIe1 |
||||
* SD2(E:F) => SLOT5 Aurora |
||||
* SD2(G:H) => SATA1,SATA2 |
||||
*/ |
||||
QIXIS_WRITE(brdcfg[13], 0x70); |
||||
break; |
||||
case 0x1f: |
||||
/*
|
||||
* SD2(A:D) => SLOT4 PCIe1 |
||||
* SD2(E:H) => SLOT5 PCIe2 |
||||
*/ |
||||
QIXIS_WRITE(brdcfg[13], 0xa0); |
||||
break; |
||||
case 0x29: |
||||
case 0x2d: |
||||
case 0x2e: |
||||
/*
|
||||
* SD2(A:D) => SLOT4 SRIO2 |
||||
* SD2(E:H) => SLOT5 SRIO1 |
||||
*/ |
||||
QIXIS_WRITE(brdcfg[13], 0x50); |
||||
break; |
||||
default: |
||||
printf("WARNING: unsupported for SerDes2 Protocol %d\n", |
||||
srds_prtcl_s2); |
||||
return -1; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
||||
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); |
||||
|
||||
/*
|
||||
* Remap Boot flash + PROMJET region to caching-inhibited |
||||
* so that flash can be erased properly. |
||||
*/ |
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */ |
||||
flush_dcache(); |
||||
invalidate_icache(); |
||||
|
||||
/* invalidate existing TLB entry for flash + promjet */ |
||||
disable_tlb(flash_esel); |
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1); |
||||
|
||||
set_liodns(); |
||||
#ifdef CONFIG_SYS_DPAA_QBMAN |
||||
setup_portals(); |
||||
#endif |
||||
|
||||
/* Disable remote I2C connection to qixis fpga */ |
||||
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); |
||||
|
||||
brd_mux_lane_to_slot(); |
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(void) |
||||
{ |
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
||||
#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT |
||||
/* use accurate clock measurement */ |
||||
int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); |
||||
int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); |
||||
u32 val; |
||||
|
||||
val = freq * base; |
||||
if (val) { |
||||
debug("SYS Clock measurement is: %d\n", val); |
||||
return val; |
||||
} else { |
||||
printf("Warning: SYS clock measurement is invalid, "); |
||||
printf("using value from brdcfg1.\n"); |
||||
} |
||||
#endif |
||||
|
||||
switch (sysclk_conf & 0x0F) { |
||||
case QIXIS_SYSCLK_83: |
||||
return 83333333; |
||||
case QIXIS_SYSCLK_100: |
||||
return 100000000; |
||||
case QIXIS_SYSCLK_125: |
||||
return 125000000; |
||||
case QIXIS_SYSCLK_133: |
||||
return 133333333; |
||||
case QIXIS_SYSCLK_150: |
||||
return 150000000; |
||||
case QIXIS_SYSCLK_160: |
||||
return 160000000; |
||||
case QIXIS_SYSCLK_166: |
||||
return 166666666; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(void) |
||||
{ |
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
||||
#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT |
||||
/* use accurate clock measurement */ |
||||
int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); |
||||
int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); |
||||
u32 val; |
||||
|
||||
val = freq * base; |
||||
if (val) { |
||||
debug("DDR Clock measurement is: %d\n", val); |
||||
return val; |
||||
} else { |
||||
printf("Warning: DDR clock measurement is invalid, "); |
||||
printf("using value from brdcfg1.\n"); |
||||
} |
||||
#endif |
||||
|
||||
switch ((ddrclk_conf & 0x30) >> 4) { |
||||
case QIXIS_DDRCLK_100: |
||||
return 100000000; |
||||
case QIXIS_DDRCLK_125: |
||||
return 125000000; |
||||
case QIXIS_DDRCLK_133: |
||||
return 133333333; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
phys_addr_t base; |
||||
phys_size_t size; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
base = getenv_bootm_low(); |
||||
size = getenv_bootm_size(); |
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||
|
||||
#ifdef CONFIG_PCI |
||||
pci_of_setup(blob, bd); |
||||
#endif |
||||
|
||||
fdt_fixup_liodn(blob); |
||||
fdt_fixup_dr_usb(blob, bd); |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
fdt_fixup_fman_ethernet(blob); |
||||
fdt_fixup_board_enet(blob); |
||||
#endif |
||||
} |
||||
@ -0,0 +1,13 @@ |
||||
/*
|
||||
* Copyright 2011-2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CORENET_DS_H__ |
||||
#define __CORENET_DS_H__ |
||||
|
||||
void fdt_fixup_board_enet(void *blob); |
||||
void pci_of_setup(void *blob, bd_t *bd); |
||||
|
||||
#endif |
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue