Currently we need to build one U-boot image for each of the udoo variants: quad and dual-lite. By switching to SPL we can support all two variants with a single binary. Based on the SPL for wandboard. Tested with OpenELEC (Open Embedded Linux Entertainment Center) on both boards. Signed-off-by: Peter Vicman <peter.vicman@gmail.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Peter Vicman <peter.vicman@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>master
vpeter4
9 years ago
committed by
Stefano Babic
parent
b893c9898c
commit
78506c2f86
@ -1,55 +0,0 @@ |
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 |
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DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 |
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 |
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 |
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB |
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 |
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 |
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|
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DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 |
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 |
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DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 |
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 |
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 |
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DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 |
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 |
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 |
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 |
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F |
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F |
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 |
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|
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 |
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A |
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 |
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 |
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 |
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F |
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 |
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 |
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 |
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 |
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 |
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 |
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@ -1,32 +0,0 @@ |
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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|
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/* set the default clock gate to save power */ |
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DATA 4, CCM_CCGR0, 0x00C03F3F |
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DATA 4, CCM_CCGR1, 0x0030FC03 |
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DATA 4, CCM_CCGR2, 0x0FFFC000 |
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DATA 4, CCM_CCGR3, 0x3FF00000 |
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DATA 4, CCM_CCGR4, 0x00FFF300 |
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DATA 4, CCM_CCGR5, 0x0F0000C3 |
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DATA 4, CCM_CCGR6, 0x000003FF |
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/* enable AXI cache for VDOA/VPU/IPU */ |
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DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF |
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
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DATA 4, MX6_IOMUXC_GPR6, 0x007F007F |
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DATA 4, MX6_IOMUXC_GPR7, 0x007F007F |
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@ -1,87 +0,0 @@ |
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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|
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/* |
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* DDR3 settings |
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* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), |
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* memory bus width: 64 bits x16/x32/x64 |
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* MX6DL ddr is limited to 800 MHz(400 MHz clock) |
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* memory bus width: 64 bits x16/x32/x64 |
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* MX6SOLO ddr is limited to 800 MHz(400 MHz clock) |
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* memory bus width: 32 bits x16/x32 |
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*/ |
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 |
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/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ |
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DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 |
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DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 |
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DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 |
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DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 |
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/* (differential input) */ |
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 |
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/* (differential input) */ |
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 |
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/* disable ddr pullups */ |
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 |
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DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 |
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/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ |
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 |
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/* Read data DQ Byte0-3 delay */ |
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 |
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 |
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 |
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 |
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 |
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 |
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 |
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 |
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@ -1,29 +0,0 @@ |
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer doc/README.imximage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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/* image version */ |
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IMAGE_VERSION 2 |
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/* |
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* Boot Device : one of |
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* spi, sd (the board has no nand neither onenand) |
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*/ |
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BOOT_FROM sd |
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#define __ASSEMBLY__ |
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#include <config.h> |
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#include "asm/arch/mx6-ddr.h" |
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#include "asm/arch/iomux.h" |
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#include "asm/arch/crm_regs.h" |
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#include "ddr-setup.cfg" |
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#include "1066mhz_4x256mx16.cfg" |
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#include "clocks.cfg" |
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@ -0,0 +1,271 @@ |
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/*
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* Copyright (C) 2015 Udoo |
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* Author: Tungyi Lin <tungyilin1127@gmail.com> |
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* Richard Hu <hakahu@gmail.com> |
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* Based on board/wandboard/spl.c |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/errno.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/video.h> |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/io.h> |
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#include <asm/arch/sys_proto.h> |
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#include <spl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#if defined(CONFIG_SPL_BUILD) |
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#include <asm/arch/mx6-ddr.h> |
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/*
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* Driving strength: |
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* 0x30 == 40 Ohm |
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* 0x28 == 48 Ohm |
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*/ |
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#define IMX6DQ_DRIVE_STRENGTH 0x30 |
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#define IMX6SDL_DRIVE_STRENGTH 0x28 |
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/* configure MX6Q/DUAL mmdc DDR io registers */ |
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static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { |
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.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_cas = IMX6DQ_DRIVE_STRENGTH, |
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.dram_ras = IMX6DQ_DRIVE_STRENGTH, |
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.dram_reset = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdba2 = 0x00000000, |
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.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, |
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.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, |
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}; |
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/* configure MX6Q/DUAL mmdc GRP io registers */ |
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static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { |
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.grp_ddr_type = 0x000c0000, |
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.grp_ddrmode_ctl = 0x00020000, |
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.grp_ddrpke = 0x00000000, |
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.grp_addds = IMX6DQ_DRIVE_STRENGTH, |
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.grp_ctlds = IMX6DQ_DRIVE_STRENGTH, |
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.grp_ddrmode = 0x00020000, |
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.grp_b0ds = IMX6DQ_DRIVE_STRENGTH, |
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.grp_b1ds = IMX6DQ_DRIVE_STRENGTH, |
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.grp_b2ds = IMX6DQ_DRIVE_STRENGTH, |
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.grp_b3ds = IMX6DQ_DRIVE_STRENGTH, |
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.grp_b4ds = IMX6DQ_DRIVE_STRENGTH, |
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.grp_b5ds = IMX6DQ_DRIVE_STRENGTH, |
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.grp_b6ds = IMX6DQ_DRIVE_STRENGTH, |
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.grp_b7ds = IMX6DQ_DRIVE_STRENGTH, |
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}; |
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ |
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { |
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.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_cas = IMX6SDL_DRIVE_STRENGTH, |
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.dram_ras = IMX6SDL_DRIVE_STRENGTH, |
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.dram_reset = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdba2 = 0x00000000, |
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.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, |
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.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, |
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}; |
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ |
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
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.grp_ddr_type = 0x000c0000, |
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.grp_ddrmode_ctl = 0x00020000, |
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.grp_ddrpke = 0x00000000, |
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.grp_addds = IMX6SDL_DRIVE_STRENGTH, |
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.grp_ctlds = IMX6SDL_DRIVE_STRENGTH, |
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.grp_ddrmode = 0x00020000, |
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.grp_b0ds = IMX6SDL_DRIVE_STRENGTH, |
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.grp_b1ds = IMX6SDL_DRIVE_STRENGTH, |
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.grp_b2ds = IMX6SDL_DRIVE_STRENGTH, |
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.grp_b3ds = IMX6SDL_DRIVE_STRENGTH, |
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.grp_b4ds = IMX6SDL_DRIVE_STRENGTH, |
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.grp_b5ds = IMX6SDL_DRIVE_STRENGTH, |
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.grp_b6ds = IMX6SDL_DRIVE_STRENGTH, |
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.grp_b7ds = IMX6SDL_DRIVE_STRENGTH, |
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}; |
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/* MT41K128M16JT-125 */ |
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static struct mx6_ddr3_cfg mt41k128m16jt_125 = { |
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/* quad = 1066, duallite = 800 */ |
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.mem_speed = 1066, |
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.density = 2, |
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.width = 16, |
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.banks = 8, |
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.rowaddr = 14, |
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.coladdr = 10, |
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.pagesz = 2, |
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.trcd = 1375, |
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.trcmin = 4875, |
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.trasmin = 3500, |
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.SRT = 0, |
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}; |
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static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = { |
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.p0_mpwldectrl0 = 0x00350035, |
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.p0_mpwldectrl1 = 0x001F001F, |
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.p1_mpwldectrl0 = 0x00010001, |
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.p1_mpwldectrl1 = 0x00010001, |
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.p0_mpdgctrl0 = 0x43510360, |
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.p0_mpdgctrl1 = 0x0342033F, |
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.p1_mpdgctrl0 = 0x033F033F, |
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.p1_mpdgctrl1 = 0x03290266, |
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.p0_mprddlctl = 0x4B3E4141, |
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.p1_mprddlctl = 0x47413B4A, |
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.p0_mpwrdlctl = 0x42404843, |
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.p1_mpwrdlctl = 0x4C3F4C45, |
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}; |
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static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { |
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.p0_mpwldectrl0 = 0x002F0038, |
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.p0_mpwldectrl1 = 0x001F001F, |
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.p1_mpwldectrl0 = 0x001F001F, |
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.p1_mpwldectrl1 = 0x001F001F, |
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.p0_mpdgctrl0 = 0x425C0251, |
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.p0_mpdgctrl1 = 0x021B021E, |
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.p1_mpdgctrl0 = 0x021B021E, |
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.p1_mpdgctrl1 = 0x01730200, |
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.p0_mprddlctl = 0x45474C45, |
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.p1_mprddlctl = 0x44464744, |
||||
.p0_mpwrdlctl = 0x3F3F3336, |
||||
.p1_mpwrdlctl = 0x32383630, |
||||
}; |
||||
|
||||
/* DDR 64bit 1GB */ |
||||
static struct mx6_ddr_sysinfo mem_qdl = { |
||||
.dsize = 2, |
||||
.cs1_mirror = 0, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, |
||||
.ncs = 1, |
||||
.bi_on = 1, |
||||
/* quad = 2, duallite = 1 */ |
||||
.rtt_nom = 2, |
||||
/* quad = 2, duallite = 1 */ |
||||
.rtt_wr = 2, |
||||
.ralat = 5, |
||||
.walat = 0, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
}; |
||||
|
||||
static void ccgr_init(void) |
||||
{ |
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
|
||||
/* set the default clock gate to save power */ |
||||
writel(0x00C03F3F, &ccm->CCGR0); |
||||
writel(0x0030FC03, &ccm->CCGR1); |
||||
writel(0x0FFFC000, &ccm->CCGR2); |
||||
writel(0x3FF00000, &ccm->CCGR3); |
||||
writel(0x00FFF300, &ccm->CCGR4); |
||||
writel(0x0F0000C3, &ccm->CCGR5); |
||||
writel(0x000003FF, &ccm->CCGR6); |
||||
} |
||||
|
||||
static void gpr_init(void) |
||||
{ |
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */ |
||||
writel(0xF00000FF, &iomux->gpr[4]); |
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
||||
writel(0x007F007F, &iomux->gpr[6]); |
||||
writel(0x007F007F, &iomux->gpr[7]); |
||||
} |
||||
|
||||
static void spl_dram_init(void) |
||||
{ |
||||
if (is_cpu_type(MXC_CPU_MX6DL)) { |
||||
mt41k128m16jt_125.mem_speed = 800; |
||||
mem_qdl.rtt_nom = 1; |
||||
mem_qdl.rtt_wr = 1; |
||||
|
||||
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
||||
mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125); |
||||
} else if (is_cpu_type(MXC_CPU_MX6Q)) { |
||||
mt41k128m16jt_125.mem_speed = 1066; |
||||
mem_qdl.rtt_nom = 2; |
||||
mem_qdl.rtt_wr = 2; |
||||
|
||||
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); |
||||
mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125); |
||||
} |
||||
|
||||
udelay(100); |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
ccgr_init(); |
||||
|
||||
/* setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
gpr_init(); |
||||
|
||||
/* iomux */ |
||||
board_early_init_f(); |
||||
|
||||
/* setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
/* DDR initialization */ |
||||
spl_dram_init(); |
||||
|
||||
/* Clear the BSS. */ |
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
|
||||
/* load/boot image from boot device */ |
||||
board_init_r(NULL, 0); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,6 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_ARM=y |
||||
CONFIG_DM=y |
||||
CONFIG_DM_THERMAL=y |
||||
CONFIG_TARGET_UDOO=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" |
||||
@ -1,5 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_UDOO=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024" |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
Loading…
Reference in new issue