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omap4/5: Add support for booting with CH.

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Configuration header(CH) is 512 byte header attached to an OMAP
boot image that will help ROM code to initialize clocks, SDRAM
etc and copy U-Boot directly into SDRAM. CH can help us in
by-passing SPL and directly boot U-boot, hence it's an alternative
for SPL. However, we intend to support both CH and SPL for OMAP4/5.

Initialization done through CH is limited and is not equivalent
to that done by SPL. So U-Boot has to distinguish between the
two cases and handle them accordingly. This patch takes care
of doing this.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
master
Sricharan 13 years ago committed by Albert ARIBAUD
parent bb772a5944
commit 78f455c055
16 changed files with 248 additions and 73 deletions
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  1. 59
      arch/arm/cpu/armv7/omap-common/clocks-common.c
  2. 24
      arch/arm/cpu/armv7/omap-common/hwinit-common.c
  3. 29
      arch/arm/cpu/armv7/omap-common/lowlevel_init.S
  4. 9
      arch/arm/cpu/armv7/omap-common/spl.c
  5. 44
      arch/arm/cpu/armv7/omap4/clocks.c
  6. 40
      arch/arm/cpu/armv7/omap5/clocks.c
  7. 1
      arch/arm/include/asm/arch-omap4/clocks.h
  8. 16
      arch/arm/include/asm/arch-omap4/omap.h
  9. 25
      arch/arm/include/asm/arch-omap4/sys_proto.h
  10. 1
      arch/arm/include/asm/arch-omap5/clocks.h
  11. 16
      arch/arm/include/asm/arch-omap5/omap.h
  12. 18
      arch/arm/include/asm/arch-omap5/sys_proto.h
  13. 1
      arch/arm/include/asm/omap_common.h
  14. 16
      board/ti/omap5_evm/mux_data.h
  15. 17
      board/ti/sdp4430/sdp4430_mux_data.h
  16. 5
      include/configs/omap4_common.h

59
arch/arm/cpu/armv7/omap-common/clocks-common.c
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@ -115,17 +115,46 @@ static inline void wait_for_lock(u32 *const base)
}
}
inline u32 check_for_lock(u32 *const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
return lock;
}
static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
u8 lock)
u8 lock, char *dpll)
{
u32 temp;
u32 temp, M, N;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
temp = readl(&dpll_regs->cm_clksel_dpll);
if (check_for_lock(base)) {
/*
* The Dpll has already been locked by rom code using CH.
* Check if M,N are matching with Ideal nominal opp values.
* If matches, skip the rest otherwise relock.
*/
M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
if ((M != (params->m)) || (N != (params->n))) {
debug("\n %s Dpll locked, but not for ideal M = %d,"
"N = %d values, current values are M = %d,"
"N= %d" , dpll, params->m, params->n,
M, N);
} else {
/* Dpll locked with ideal values for nominal opps. */
debug("\n %s Dpll already locked with ideal"
"nominal opp values", dpll);
goto setup_post_dividers;
}
}
bypass_dpll(base);
/* Set M & N */
temp = readl(&dpll_regs->cm_clksel_dpll);
temp &= ~CM_CLKSEL_DPLL_M_MASK;
temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
@ -138,6 +167,7 @@ static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
if (lock)
do_lock_dpll(base);
setup_post_dividers:
setup_post_dividers(base, params);
/* Wait till the DPLL locks */
@ -216,7 +246,8 @@ void configure_mpu_dpll(void)
}
params = get_mpu_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
debug("MPU DPLL locked\n");
}
@ -235,7 +266,8 @@ static void setup_dplls(void)
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
"core");
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
@ -246,13 +278,14 @@ static void setup_dplls(void)
/* lock PER dpll */
params = get_per_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_per,
params, DPLL_LOCK);
params, DPLL_LOCK, "per");
debug("PER DPLL locked\n");
/* MPU dpll */
configure_mpu_dpll();
}
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
static void setup_non_essential_dplls(void)
{
u32 sys_clk_khz, abe_ref_clk;
@ -267,7 +300,7 @@ static void setup_non_essential_dplls(void)
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
params = get_iva_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK);
do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
/*
* USB:
@ -287,7 +320,7 @@ static void setup_non_essential_dplls(void)
sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
/* Now setup the dpll with the regular function */
do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
/* Configure ABE dpll */
params = get_abe_dpll_params();
@ -315,8 +348,9 @@ static void setup_non_essential_dplls(void)
CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
/* Lock the dpll */
do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
}
#endif
void do_scale_tps62361(u32 reg, u32 volt_mv)
{
@ -561,10 +595,15 @@ void prcm_init(void)
enable_basic_clocks();
scale_vcores();
setup_dplls();
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
setup_non_essential_dplls();
enable_non_essential_clocks();
#endif
break;
default:
break;
}
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
enable_basic_uboot_clocks();
}

24
arch/arm/cpu/armv7/omap-common/hwinit-common.c
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@ -31,9 +31,18 @@
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* This is used to verify if the configuration header
* was executed by rom code prior to control of transfer
* to the bootloader. SPL is responsible for saving and
* passing the boot_params pointer to the u-boot.
*/
struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
@ -41,12 +50,11 @@ DECLARE_GLOBAL_DATA_PTR;
* We would not typically need to save these parameters in regular
* U-Boot. This is needed only in SPL at the moment.
*/
u32 omap_bootdevice = BOOT_DEVICE_MMC1;
u32 omap_bootmode = MMCSD_MODE_FAT;
u32 omap_boot_device(void)
{
return omap_bootdevice;
return (u32) (boot_params.omap_bootdevice);
}
u32 omap_boot_mode(void)
@ -71,12 +79,16 @@ static void set_mux_conf_regs(void)
set_muxconf_regs_essential();
break;
case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
#ifdef CONFIG_SYS_ENABLE_PADS_ALL
set_muxconf_regs_non_essential();
#endif
break;
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
set_muxconf_regs_essential();
#ifdef CONFIG_SYS_ENABLE_PADS_ALL
set_muxconf_regs_non_essential();
#endif
break;
}
}
@ -103,6 +115,13 @@ void omap_rev_string(char *omap_rev_string)
minor_rev);
}
#ifdef CONFIG_SPL_BUILD
static void init_boot_params(void)
{
boot_params_ptr = (u32 *) &boot_params;
}
#endif
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
@ -131,6 +150,7 @@ void s_init(void)
#ifdef CONFIG_SPL_BUILD
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
init_boot_params();
#endif
}

29
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
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@ -27,7 +27,7 @@
*/
#include <asm/arch/omap.h>
#ifdef CONFIG_SPL_BUILD
.global save_boot_params
save_boot_params:
/*
@ -43,21 +43,40 @@ save_boot_params:
cmp r2, r0
blt 1f
/*
* store the boot params passed from rom code or saved
* and passed by SPL
*/
cmp r0, #0
beq 1f
ldr r1, =boot_params
str r0, [r1]
#ifdef CONFIG_SPL_BUILD
/* Store the boot device in omap_boot_device */
ldr r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
and r2, #BOOT_DEVICE_MASK
ldr r3, =omap_bootdevice
str r2, [r3] @ omap_boot_device <- r1
ldr r3, =boot_params
strb r2, [r3, #BOOT_DEVICE_OFFSET] @ omap_boot_device <- r1
/* boot mode is passed only for devices that can raw/fat mode */
cmp r2, #2
blt 2f
cmp r2, #7
bgt 2f
/* Store the boot mode (raw/FAT) in omap_boot_mode */
ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr
ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode
ldr r3, =omap_bootmode
str r2, [r3]
#endif
2:
ldrb r2, [r0, #CH_FLAGS_OFFSET]
ldr r3, =boot_params
strb r2, [r3, #CH_FLAGS_OFFSET]
1:
bx lr
#endif
.globl lowlevel_init
lowlevel_init:

9
arch/arm/cpu/armv7/omap-common/spl.c
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@ -38,6 +38,7 @@
DECLARE_GLOBAL_DATA_PTR;
u32* boot_params_ptr = NULL;
struct spl_image_info spl_image;
/* Define global data structure pointer to it*/
@ -92,12 +93,16 @@ void spl_parse_image_header(const struct image_header *header)
static void jump_to_image_no_args(void)
{
typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn));
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image.entry_point;
debug("image entry point: 0x%X\n", spl_image.entry_point);
image_entry();
/* Pass the saved boot_params from rom code */
#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU)
image_entry = 0x80100000;
#endif
image_entry((u32 *)&boot_params_ptr);
}
void jump_to_image_no_args(void) __attribute__ ((noreturn));

44
arch/arm/cpu/armv7/omap4/clocks.c
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@ -333,30 +333,23 @@ void enable_basic_clocks(void)
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
&prcm->cm_wkup_gpio1_clkctrl,
&prcm->cm_l4per_gpio2_clkctrl,
&prcm->cm_l4per_gpio3_clkctrl,
&prcm->cm_l4per_gpio4_clkctrl,
&prcm->cm_l4per_gpio5_clkctrl,
&prcm->cm_l4per_gpio6_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l3init_hsusbotg_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l3init_hsmmc1_clkctrl,
&prcm->cm_l3init_hsmmc2_clkctrl,
&prcm->cm_l4per_mcspi1_clkctrl,
&prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l4per_i2c1_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
0
@ -386,6 +379,33 @@ void enable_basic_clocks(void)
1);
}
void enable_basic_uboot_clocks(void)
{
u32 *const clk_domains_essential[] = {
0
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_l3init_hsusbotg_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_l4per_mcspi1_clkctrl,
&prcm->cm_l4per_i2c1_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed

40
arch/arm/cpu/armv7/omap5/clocks.c
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@ -273,30 +273,26 @@ void enable_basic_clocks(void)
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
&prcm->cm_wkup_gpio1_clkctrl,
&prcm->cm_l4per_gpio2_clkctrl,
&prcm->cm_l4per_gpio3_clkctrl,
&prcm->cm_l4per_gpio4_clkctrl,
&prcm->cm_l4per_gpio5_clkctrl,
&prcm->cm_l4per_gpio6_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l3init_hsmmc1_clkctrl,
&prcm->cm_l3init_hsmmc2_clkctrl,
&prcm->cm_l4per_mcspi1_clkctrl,
&prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l4per_i2c1_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
&prcm->cm_l4per_i2c1_clkctrl,
0
};
@ -320,6 +316,30 @@ void enable_basic_clocks(void)
1);
}
void enable_basic_uboot_clocks(void)
{
u32 *const clk_domains_essential[] = {
0
};
u32 *const clk_modules_hw_auto_essential[] = {
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_l4per_mcspi1_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed

1
arch/arm/include/asm/arch-omap4/clocks.h
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@ -698,6 +698,7 @@ void setup_sri2c(void);
void setup_post_dividers(u32 *const base, const struct dpll_params *params);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
void enable_non_essential_clocks(void);
void do_enable_clocks(u32 *const *clk_domains,
u32 *const *clk_modules_hw_auto,

16
arch/arm/include/asm/arch-omap4/omap.h
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@ -191,5 +191,21 @@ struct control_lpddr2io_regs {
#define DEV_DESC_PTR_OFFSET 0x4
#define DEV_DATA_PTR_OFFSET 0x18
#define BOOT_MODE_OFFSET 0x8
#define RESET_REASON_OFFSET 0x9
#define CH_FLAGS_OFFSET 0xA
#define CH_FLAGS_CHSETTINGS (0x1 << 0)
#define CH_FLAGS_CHRAM (0x1 << 1)
#define CH_FLAGS_CHFLASH (0x1 << 2)
#define CH_FLAGS_CHMMCSD (0x1 << 3)
#ifndef __ASSEMBLY__
struct omap_boot_parameters {
char *boot_message;
unsigned int mem_boot_descriptor;
unsigned char omap_bootdevice;
unsigned char reset_reason;
unsigned char ch_flags;
};
#endif
#endif

25
arch/arm/include/asm/arch-omap4/sys_proto.h
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@ -55,6 +55,13 @@ u32 omap_sdram_size(void);
u32 cortex_rev(void);
void init_omap_revision(void);
void do_io_settings(void);
/*
* This is used to verify if the configuration header
* was executed by Romcode prior to control of transfer
* to the bootloader. SPL is responsible for saving and
* passing this to the u-boot.
*/
extern struct omap_boot_parameters boot_params;
static inline u32 running_from_sdram(void)
{
@ -67,15 +74,17 @@ static inline u32 running_from_sdram(void)
static inline u8 uboot_loaded_by_spl(void)
{
/*
* Configuration Header is not supported yet, so u-boot init running
* from SDRAM implies that it was loaded by SPL. When this situation
* changes one of these approaches could be taken:
* i. Pass a magic from SPL to U-Boot and U-Boot save it at a known
* location.
* ii. Check the OPP. CH can support only 50% OPP while SPL initializes
* the DPLLs at 100% OPP.
* u-boot can be running from sdram either because of configuration
* Header or by SPL. If because of CH, then the romcode sets the
* CHSETTINGS executed bit to true in the boot parameter structure that
* it passes to the bootloader.This parameter is stored in the ch_flags
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
return running_from_sdram();
if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
}
/*
* The basic hardware init of OMAP(s_init()) can happen in 4

1
arch/arm/include/asm/arch-omap5/clocks.h
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@ -708,6 +708,7 @@ void setup_post_dividers(u32 *const base, const struct dpll_params *params);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_non_essential_clocks(void);
void enable_basic_uboot_clocks(void);
void do_enable_clocks(u32 *const *clk_domains,
u32 *const *clk_modules_hw_auto,
u32 *const *clk_modules_explicit_en,

16
arch/arm/include/asm/arch-omap5/omap.h
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@ -203,5 +203,21 @@ struct control_lpddr2io_regs {
#define DEV_DESC_PTR_OFFSET 0x4
#define DEV_DATA_PTR_OFFSET 0x18
#define BOOT_MODE_OFFSET 0x8
#define RESET_REASON_OFFSET 0x9
#define CH_FLAGS_OFFSET 0xA
#define CH_FLAGS_CHSETTINGS (0x1 << 0)
#define CH_FLAGS_CHRAM (0x1 << 1)
#define CH_FLAGS_CHFLASH (0x1 << 2)
#define CH_FLAGS_CHMMCSD (0x1 << 3)
#ifndef __ASSEMBLY__
struct omap_boot_parameters {
char *boot_message;
unsigned int mem_boot_descriptor;
unsigned char omap_bootdevice;
unsigned char reset_reason;
unsigned char ch_flags;
};
#endif /* __ASSEMBLY__ */
#endif

18
arch/arm/include/asm/arch-omap5/sys_proto.h
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@ -75,15 +75,17 @@ static inline u32 running_from_sdram(void)
static inline u8 uboot_loaded_by_spl(void)
{
/*
* Configuration Header is not supported yet, so u-boot init running
* from SDRAM implies that it was loaded by SPL. When this situation
* changes one of these approaches could be taken:
* i. Pass a magic from SPL to U-Boot and U-Boot save it at a known
* location.
* ii. Check the OPP. CH can support only 50% OPP while SPL initializes
* the DPLLs at 100% OPP.
* u-boot can be running from sdram either because of configuration
* Header or by SPL. If because of CH, then the romcode sets the
* CHSETTINGS executed bit to true in the boot parameter structure that
* it passes to the bootloader.This parameter is stored in the ch_flags
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
return running_from_sdram();
if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
}
/*
* The basic hardware init of OMAP(s_init()) can happen in 4

1
arch/arm/include/asm/omap_common.h
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@ -80,6 +80,7 @@ struct spl_image_info {
extern struct spl_image_info spl_image;
extern u32* boot_params_ptr;
u32 omap_boot_device(void);
u32 omap_boot_mode(void);

16
board/ti/omap5_evm/mux_data.h
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@ -50,14 +50,6 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
@ -245,6 +237,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
{DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */
{DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */
{DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
{I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */
};
const struct pad_conf_entry wkup_padconf_array_non_essential[] = {

17
board/ti/sdp4430/sdp4430_mux_data.h
Unescape View File

@ -50,14 +50,6 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
@ -251,6 +243,15 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
{DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */
{DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */
{DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
{I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */
};
const struct pad_conf_entry wkup_padconf_array_non_essential[] = {

5
include/configs/omap4_common.h
Unescape View File

@ -122,6 +122,9 @@
/* Flash */
#define CONFIG_SYS_NO_FLASH 1
/* clocks */
#define CONFIG_SYS_CLOCKS_ENABLE_ALL
/* commands to include */
#include <config_cmd_default.h>
@ -278,4 +281,6 @@
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_ENABLE_PADS_ALL
#endif /* __CONFIG_OMAP4_COMMON_H */

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