* 'master' of git://git.denx.de/u-boot-ppc4xx: ppc4xx: Add Io64 board support ppc4xx: fix PMC440 painit command ppc4xx: remove invalid access to PCI_BRDGOPT2 register ppc4xx: use CONFIG_PCI_BOOTDELAY instead of private implementationmaster
Wolfgang Denk
14 years ago
commit
797449a16d
@ -0,0 +1,250 @@ |
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#include <common.h> |
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#include <asm/ppc4xx.h> |
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#include <asm/ppc405.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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|
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#include <gdsys_fpga.h> |
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|
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#include "405ex.h" |
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|
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#define REFLECTION_TESTPATTERN 0xdede |
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#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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int get_fpga_state(unsigned dev) |
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{ |
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return gd->fpga_state[dev]; |
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} |
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|
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void print_fpga_state(unsigned dev) |
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{ |
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if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED) |
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puts(" Waiting for FPGA-DONE timed out.\n"); |
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if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) |
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puts(" FPGA reflection test failed.\n"); |
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} |
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|
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int board_early_init_f(void) |
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{ |
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u32 val; |
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|
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/*--------------------------------------------------------------------+
|
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| Interrupt controller setup |
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+--------------------------------------------------------------------+ |
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+---------------------------------------------------------------------+ |
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|Interrupt| Source | Pol. | Sensi.| Crit. | |
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+---------+-----------------------------------+-------+-------+-------+ |
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| IRQ 00 | UART0 | High | Level | Non | |
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| IRQ 01 | UART1 | High | Level | Non | |
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| IRQ 02 | IIC0 | High | Level | Non | |
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| IRQ 03 | TBD | High | Level | Non | |
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| IRQ 04 | TBD | High | Level | Non | |
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| IRQ 05 | EBM | High | Level | Non | |
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| IRQ 06 | BGI | High | Level | Non | |
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| IRQ 07 | IIC1 | Rising| Edge | Non | |
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| IRQ 08 | SPI | High | Lvl/ed| Non | |
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| IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | |
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| IRQ 10 | MAL TX EOB | High | Level | Non | |
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| IRQ 11 | MAL RX EOB | High | Level | Non | |
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| IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | |
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| IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | |
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| IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | |
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| IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | |
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| IRQ 16 | PCIE0 AL | high | Level | Non | |
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| IRQ 17 | PCIE0 VPD access | rising| Edge | Non | |
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| IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | |
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| IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | |
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| IRQ 20 | PCIE0 TCR | High | Level | Non | |
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| IRQ 21 | PCIE0 MSI level0 | High | Level | Non | |
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| IRQ 22 | PCIE0 MSI level1 | High | Level | Non | |
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| IRQ 23 | Security EIP-94 | High | Level | Non | |
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| IRQ 24 | EMAC0 interrupt | High | Level | Non | |
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| IRQ 25 | EMAC1 interrupt | High | Level | Non | |
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| IRQ 26 | PCIE0 MSI level2 | High | Level | Non | |
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| IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | |
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| IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | |
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| IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | |
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| IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | |
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| IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | |
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|---------------------------------------------------------------------- |
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| IRQ 32 | MAL Serr | High | Level | Non | |
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| IRQ 33 | MAL Txde | High | Level | Non | |
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| IRQ 34 | MAL Rxde | High | Level | Non | |
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| IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | |
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| IRQ 36 | PCIE0 DCR Error | High | Level | Non | |
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| IRQ 37 | EBC | High |Lvl Edg| Non | |
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| IRQ 38 | NDFC | High | Level | Non | |
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| IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | |
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| IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | |
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| IRQ 41 | PCIE1 AL | high | Level | Non | |
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| IRQ 42 | PCIE1 VPD access | rising| edge | Non | |
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| IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | |
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| IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | |
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| IRQ 45 | PCIE1 TCR | High | Level | Non | |
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| IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | |
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| IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | |
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| IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | |
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| IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | |
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| IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | |
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| IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | |
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| IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | |
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| IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | |
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| IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | |
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| IRQ 55 | Serial ROM | High | Level | Non | |
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| IRQ 56 | GPT Decrement Pulse | High | Level | Non | |
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| IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | |
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| IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | |
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| IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | |
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| IRQ 60 | EMAC0 Wake-up | High | Level | Non | |
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| IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | |
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| IRQ 62 | EMAC1 Wake-up | High | Level | Non | |
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|---------------------------------------------------------------------- |
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| IRQ 64 | PE0 AL | High | Level | Non | |
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| IRQ 65 | PE0 VPD Access | Risin | Edge | Non | |
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| IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | |
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| IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | |
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| IRQ 68 | PE0 TCR | High | Level | Non | |
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| IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | |
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| IRQ 70 | PE0 DCR Error | High | Level | Non | |
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| IRQ 71 | Reserved | N/A | N/A | Non | |
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| IRQ 72 | PE1 AL | High | Level | Non | |
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| IRQ 73 | PE1 VPD Access | Risin | Edge | Non | |
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| IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | |
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| IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | |
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| IRQ 76 | PE1 TCR | High | Level | Non | |
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| IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | |
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| IRQ 78 | PE1 DCR Error | High | Level | Non | |
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| IRQ 79 | Reserved | N/A | N/A | Non | |
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| IRQ 80 | PE2 AL | High | Level | Non | |
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| IRQ 81 | PE2 VPD Access | Risin | Edge | Non | |
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| IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | |
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| IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | |
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| IRQ 84 | PE2 TCR | High | Level | Non | |
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| IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | |
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| IRQ 86 | PE2 DCR Error | High | Level | Non | |
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| IRQ 87 | Reserved | N/A | N/A | Non | |
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| IRQ 88 | External IRQ(5) | Progr | Progr | Non | |
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| IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | |
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| IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | |
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| IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | |
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| IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | |
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| IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | |
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| IRQ 94 | Reserved | N/A | N/A | Non | |
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| IRQ 95 | Reserved | N/A | N/A | Non | |
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|--------------------------------------------------------------------- |
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+---------+-----------------------------------+-------+-------+------*/ |
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/*--------------------------------------------------------------------+
|
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| Initialise UIC registers. Clear all interrupts. Disable all |
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| interrupts. |
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| Set critical interrupt values. Set interrupt polarities. Set |
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| interrupt trigger levels. Make bit 0 High priority. Clear all |
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| interrupts again. |
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+-------------------------------------------------------------------*/ |
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|
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mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ |
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mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ |
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mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ |
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mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ |
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mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ |
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mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ |
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mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ |
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mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ |
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|
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mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ |
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mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ |
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mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ |
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mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ |
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mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ |
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mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ |
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mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */ |
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mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ |
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|
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mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ |
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mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */ |
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/* Except cascade UIC0 and UIC1 */ |
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mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ |
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mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ |
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mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ |
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mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ |
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mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */ |
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mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ |
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|
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/*
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* Note: Some cores are still in reset when the chip starts, so |
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* take them out of reset |
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*/ |
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mtsdr(SDR0_SRST, 0); |
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|
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/*
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* Configure PFC (Pin Function Control) registers |
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*/ |
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val = SDR0_PFC1_GPT_FREQ; |
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mtsdr(SDR0_PFC1, val); |
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return 0; |
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} |
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int board_early_init_r(void) |
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{ |
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unsigned k; |
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unsigned ctr; |
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) |
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gd->fpga_state[k] = 0; |
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/*
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* reset FPGA |
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*/ |
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gd405ex_init(); |
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gd405ex_set_fpga_reset(1); |
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gd405ex_setup_hw(); |
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { |
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ctr = 0; |
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while (!gd405ex_get_fpga_done(k)) { |
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udelay(100000); |
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if (ctr++ > 5) { |
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gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; |
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break; |
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} |
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} |
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} |
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udelay(10); |
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gd405ex_set_fpga_reset(0); |
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { |
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); |
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#ifdef CONFIG_SYS_FPGA_NO_RFL_HI |
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u16 *reflection_target = &fpga->reflection_low; |
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#else |
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u16 *reflection_target = &fpga->reflection_high; |
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#endif |
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/*
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* wait for fpga out of reset |
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*/ |
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ctr = 0; |
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while (1) { |
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out_le16(&fpga->reflection_low, |
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REFLECTION_TESTPATTERN); |
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|
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if (in_le16(reflection_target) == |
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REFLECTION_TESTPATTERN_INV) |
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break; |
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udelay(100000); |
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if (ctr++ > 5) { |
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gd->fpga_state[k] |= |
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FPGA_STATE_REFLECTION_FAILED; |
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break; |
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} |
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} |
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} |
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|
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return 0; |
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} |
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@ -0,0 +1,10 @@ |
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#ifndef __405EX_H_ |
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#define __405EX_H_ |
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|
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/* functions to be provided by board implementation */ |
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void gd405ex_init(void); |
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void gd405ex_set_fpga_reset(unsigned state); |
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void gd405ex_setup_hw(void); |
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int gd405ex_get_fpga_done(unsigned fpga); |
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#endif /* __405EX_H_ */ |
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@ -0,0 +1,53 @@ |
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#
|
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# (C) Copyright 2007
|
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
|
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#
|
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|
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include $(TOPDIR)/config.mk |
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|
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LIB = $(obj)lib$(BOARD).o
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|
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COBJS-$(CONFIG_IO64) += io64.o
|
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|
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COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
|
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|
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COBJS := $(BOARD).o $(COBJS-y)
|
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|
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
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|
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$(LIB): $(obj).depend $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
|
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|
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clean: |
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rm -f $(OBJS)
|
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|
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
|
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|
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#########################################################################
|
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|
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# defines $(obj).depend target
|
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include $(SRCTREE)/rules.mk |
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|
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sinclude $(obj).depend |
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|
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#########################################################################
|
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@ -0,0 +1,96 @@ |
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/*
|
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* (C) Copyright 2009 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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* |
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*/ |
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|
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#include <common.h> |
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#include <asm/ppc4xx_config.h> |
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|
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/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */ |
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|
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struct ppc4xx_config ppc4xx_config_val[] = { |
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{ |
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"333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", |
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{ |
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0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", |
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{ |
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0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66", |
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{ |
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0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", |
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{ |
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0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", |
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{ |
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0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00, |
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00, |
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", |
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{ |
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0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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}; |
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|
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int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); |
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@ -0,0 +1,384 @@ |
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/*
|
||||
* (C) Copyright 2010 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
||||
* based on kilauea.c |
||||
* by Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/ppc4xx.h> |
||||
#include <asm/ppc405.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/ppc4xx-gpio.h> |
||||
#include <flash.h> |
||||
|
||||
#include <pca9698.h> |
||||
|
||||
#include "405ex.h" |
||||
#include <gdsys_fpga.h> |
||||
|
||||
#include <miiphy.h> |
||||
#include <i2c.h> |
||||
#include <dtt.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define PHYREG_CONTROL 0 |
||||
#define PHYREG_PAGE_ADDRESS 22 |
||||
#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 |
||||
#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 |
||||
#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17 |
||||
#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21 |
||||
|
||||
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) |
||||
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) |
||||
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) |
||||
#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) |
||||
|
||||
enum { |
||||
UNITTYPE_CCD_SWITCH = 1, |
||||
}; |
||||
|
||||
enum { |
||||
HWVER_100 = 0, |
||||
HWVER_110 = 1, |
||||
}; |
||||
|
||||
static inline void blank_string(int size) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < size; i++) |
||||
putc('\b'); |
||||
for (i = 0; i < size; i++) |
||||
putc(' '); |
||||
for (i = 0; i < size; i++) |
||||
putc('\b'); |
||||
} |
||||
|
||||
/*
|
||||
* Board early initialization function |
||||
*/ |
||||
int misc_init_r(void) |
||||
{ |
||||
/* startup fans */ |
||||
dtt_init(); |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH |
||||
/* Monitor protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
-CONFIG_SYS_MONITOR_LEN, |
||||
0xffffffff, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void print_fpga_info(unsigned dev) |
||||
{ |
||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); |
||||
u16 versions = in_le16(&fpga->versions); |
||||
u16 fpga_version = in_le16(&fpga->fpga_version); |
||||
u16 fpga_features = in_le16(&fpga->fpga_features); |
||||
int fpga_state = get_fpga_state(dev); |
||||
|
||||
unsigned unit_type; |
||||
unsigned hardware_version; |
||||
unsigned feature_channels; |
||||
unsigned feature_expansion; |
||||
|
||||
printf("FPGA%d: ", dev); |
||||
if (fpga_state & FPGA_STATE_PLATFORM) |
||||
printf("(legacy) "); |
||||
|
||||
if (fpga_state & FPGA_STATE_DONE_FAILED) { |
||||
printf(" done timed out\n"); |
||||
return; |
||||
} |
||||
|
||||
if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { |
||||
printf(" refelectione test failed\n"); |
||||
return; |
||||
} |
||||
|
||||
unit_type = (versions & 0xf000) >> 12; |
||||
hardware_version = versions & 0x000f; |
||||
feature_channels = fpga_features & 0x007f; |
||||
feature_expansion = fpga_features & (1<<15); |
||||
|
||||
switch (unit_type) { |
||||
case UNITTYPE_CCD_SWITCH: |
||||
printf("CCD-Switch"); |
||||
break; |
||||
|
||||
default: |
||||
printf("UnitType %d(not supported)", unit_type); |
||||
break; |
||||
} |
||||
|
||||
switch (hardware_version) { |
||||
case HWVER_100: |
||||
printf(" HW-Ver 1.00\n"); |
||||
break; |
||||
|
||||
case HWVER_110: |
||||
printf(" HW-Ver 1.10\n"); |
||||
break; |
||||
|
||||
default: |
||||
printf(" HW-Ver %d(not supported)\n", |
||||
hardware_version); |
||||
break; |
||||
} |
||||
|
||||
printf(" FPGA V %d.%02d, features:", |
||||
fpga_version / 100, fpga_version % 100); |
||||
|
||||
printf(" %d channel(s)", feature_channels); |
||||
|
||||
printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
char *s = getenv("serial#"); |
||||
|
||||
printf("Board: CATCenter Io64\n"); |
||||
|
||||
if (s != NULL) { |
||||
puts(", serial# "); |
||||
puts(s); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int configure_gbit_phy(char *bus, unsigned char addr) |
||||
{ |
||||
unsigned short value; |
||||
|
||||
/* select page 0 */ |
||||
if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) |
||||
goto err_out; |
||||
/* switch to powerdown */ |
||||
if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, |
||||
&value)) |
||||
goto err_out; |
||||
if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, |
||||
value | 0x0004)) |
||||
goto err_out; |
||||
/* select page 2 */ |
||||
if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) |
||||
goto err_out; |
||||
/* disable SGMII autonegotiation */ |
||||
if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48)) |
||||
goto err_out; |
||||
/* select page 0 */ |
||||
if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) |
||||
goto err_out; |
||||
/* switch from powerdown to normal operation */ |
||||
if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, |
||||
&value)) |
||||
goto err_out; |
||||
if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, |
||||
value & ~0x0004)) |
||||
goto err_out; |
||||
/* reset phy so settings take effect */ |
||||
if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140)) |
||||
goto err_out; |
||||
|
||||
return 0; |
||||
|
||||
err_out: |
||||
printf("Error writing to the PHY addr=%02x\n", addr); |
||||
return -1; |
||||
} |
||||
|
||||
int verify_gbit_phy(char *bus, unsigned char addr) |
||||
{ |
||||
unsigned short value; |
||||
|
||||
/* select page 2 */ |
||||
if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) |
||||
goto err_out; |
||||
/* verify SGMII link status */ |
||||
if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value)) |
||||
goto err_out; |
||||
if (!(value & (1 << 10))) |
||||
return -2; |
||||
|
||||
return 0; |
||||
|
||||
err_out: |
||||
printf("Error writing to the PHY addr=%02x\n", addr); |
||||
return -1; |
||||
} |
||||
|
||||
int last_stage_init(void) |
||||
{ |
||||
unsigned int k; |
||||
unsigned int fpga; |
||||
ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); |
||||
ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1); |
||||
int failed = 0; |
||||
char str_phys[] = "Setup PHYs -"; |
||||
char str_serdes[] = "Start SERDES blocks"; |
||||
char str_channels[] = "Start FPGA channels"; |
||||
char str_locks[] = "Verify SERDES locks"; |
||||
char str_status[] = "Verify PHY status -"; |
||||
char slash[] = "\\|/-\\|/-"; |
||||
|
||||
print_fpga_info(0); |
||||
print_fpga_info(1); |
||||
|
||||
/* setup Gbit PHYs */ |
||||
puts("TRANS: "); |
||||
puts(str_phys); |
||||
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, |
||||
bb_miiphy_read, bb_miiphy_write); |
||||
|
||||
for (k = 0; k < 32; ++k) { |
||||
configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); |
||||
putc('\b'); |
||||
putc(slash[k % 8]); |
||||
} |
||||
|
||||
miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME, |
||||
bb_miiphy_read, bb_miiphy_write); |
||||
|
||||
for (k = 0; k < 32; ++k) { |
||||
configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); |
||||
putc('\b'); |
||||
putc(slash[k % 8]); |
||||
} |
||||
blank_string(strlen(str_phys)); |
||||
|
||||
/* take fpga serdes blocks out of reset */ |
||||
puts(str_serdes); |
||||
udelay(500000); |
||||
out_le16(&fpga0->quad_serdes_reset, 0); |
||||
out_le16(&fpga1->quad_serdes_reset, 0); |
||||
blank_string(strlen(str_serdes)); |
||||
|
||||
/* take channels out of reset */ |
||||
puts(str_channels); |
||||
udelay(500000); |
||||
for (fpga = 0; fpga < 2; ++fpga) { |
||||
u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int; |
||||
for (k = 0; k < 32; ++k) |
||||
out_le16(ch0_config_int + 4 * k, 0); |
||||
} |
||||
blank_string(strlen(str_channels)); |
||||
|
||||
/* verify channels serdes lock */ |
||||
puts(str_locks); |
||||
udelay(500000); |
||||
for (fpga = 0; fpga < 2; ++fpga) { |
||||
u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int; |
||||
for (k = 0; k < 32; ++k) { |
||||
u16 status = in_le16(ch0_status_int + 4*k); |
||||
if (!(status & (1 << 4))) { |
||||
failed = 1; |
||||
printf("fpga %d channel %d: no serdes lock\n", |
||||
fpga, k); |
||||
} |
||||
/* reset events */ |
||||
out_le16(ch0_status_int + 4*k, status); |
||||
} |
||||
} |
||||
blank_string(strlen(str_locks)); |
||||
|
||||
/* verify phy status */ |
||||
puts(str_status); |
||||
for (k = 0; k < 32; ++k) { |
||||
if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) { |
||||
printf("verify baseboard phy %d failed\n", k); |
||||
failed = 1; |
||||
} |
||||
putc('\b'); |
||||
putc(slash[k % 8]); |
||||
} |
||||
for (k = 0; k < 32; ++k) { |
||||
if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) { |
||||
printf("verify extensionboard phy %d failed\n", k); |
||||
failed = 1; |
||||
} |
||||
putc('\b'); |
||||
putc(slash[k % 8]); |
||||
} |
||||
blank_string(strlen(str_status)); |
||||
|
||||
printf("Starting 64 channels %s\n", failed ? "failed" : "ok"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void gd405ex_init(void) |
||||
{ |
||||
unsigned int k; |
||||
|
||||
if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */ |
||||
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) |
||||
gd->fpga_state[k] |= FPGA_STATE_PLATFORM; |
||||
} else { |
||||
pca9698_direction_output(0x22, 39, 1); |
||||
} |
||||
} |
||||
|
||||
void gd405ex_set_fpga_reset(unsigned state) |
||||
{ |
||||
int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; |
||||
|
||||
if (legacy) { |
||||
if (state) { |
||||
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); |
||||
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); |
||||
} else { |
||||
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); |
||||
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); |
||||
} |
||||
} else { |
||||
pca9698_set_value(0x22, 39, state ? 0 : 1); |
||||
} |
||||
} |
||||
|
||||
void gd405ex_setup_hw(void) |
||||
{ |
||||
gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0); |
||||
gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1); |
||||
} |
||||
|
||||
int gd405ex_get_fpga_done(unsigned fpga) |
||||
{ |
||||
int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; |
||||
|
||||
if (legacy) |
||||
return in_le16((void *)LATCH3_BASE) |
||||
& CONFIG_SYS_FPGA_DONE(fpga); |
||||
else |
||||
return pca9698_get_value(0x22, fpga ? 9 : 8); |
||||
} |
||||
@ -0,0 +1,566 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* based on kilauea.h |
||||
* by Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* and Grant Erickson <gerickson@nuovations.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* io64.h - configuration for Guntermann & Drunck Io64 (405EX) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_IO64 1 /* Board is Io64 */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_405EX 1 /* Specifc 405EX support*/ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ |
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 |
||||
#endif |
||||
|
||||
/*
|
||||
* CHIP_21 errata |
||||
*/ |
||||
#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY |
||||
|
||||
/*
|
||||
* Include common defines/options for all AMCC eval boards |
||||
*/ |
||||
#define CONFIG_HOSTNAME io64 |
||||
#define CONFIG_IDENT_STRING " io64 0.01" |
||||
#include "amcc-common.h" |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_EARLY_INIT_R |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_LAST_STAGE_INIT |
||||
|
||||
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ |
||||
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
||||
#define CONFIG_AUTOBOOT_STOP_STR " " |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0xFC000000 |
||||
#define CONFIG_SYS_NVRAM_BASE 0xF0000000 |
||||
#define CONFIG_SYS_FPGA0_BASE 0xF0100000 |
||||
#define CONFIG_SYS_FPGA1_BASE 0xF0108000 |
||||
#define CONFIG_SYS_LATCH_BASE 0xF0200000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & Stack Pointer Configuration Options |
||||
* |
||||
* There are traditionally three options for the primordial |
||||
* (i.e. initial) stack usage on the 405-series: |
||||
* |
||||
* 1) On-chip Memory (OCM) (i.e. SRAM) |
||||
* 2) Data cache |
||||
* 3) SDRAM |
||||
* |
||||
* For the 405EX(r), there is no OCM, so we are left with (2) or (3) |
||||
* the latter of which is less than desireable since it requires |
||||
* setting up the SDRAM and ECC in assembly code. |
||||
* |
||||
* To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip |
||||
* select on the External Bus Controller (EBC) and then select a |
||||
* value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid, |
||||
* physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and |
||||
* select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid, |
||||
* physical SDRAM to use (3). |
||||
*-----------------------------------------------------------------------*/ |
||||
|
||||
#define CONFIG_SYS_INIT_DCACHE_CS 4 |
||||
|
||||
#if defined(CONFIG_SYS_INIT_DCACHE_CS) |
||||
#define CONFIG_SYS_INIT_RAM_ADDR \ |
||||
(CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */ |
||||
#else |
||||
#define CONFIG_SYS_INIT_RAM_ADDR \ |
||||
(CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */ |
||||
#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
||||
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE \ |
||||
(4 << 10) /* 4 KiB */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* If the data cache is being used for the primordial stack and global |
||||
* data area, the POST word must be placed somewhere else. The General |
||||
* Purpose Timer (GPT) is unused by u-boot and the kernel and preserves |
||||
* its compare and mask register contents across reset, so it is used |
||||
* for the POST word. |
||||
*/ |
||||
|
||||
#if defined(CONFIG_SYS_INIT_DCACHE_CS) |
||||
# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
# define CONFIG_SYS_POST_WORD_ADDR \ |
||||
(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) |
||||
#else |
||||
# define CONFIG_SYS_INIT_EXTRA_SIZE 16 |
||||
# define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE) |
||||
# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR |
||||
#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
||||
#define CONFIG_SYS_BASE_BAUD 691200 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */ |
||||
|
||||
/* Gbit PHYs */ |
||||
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
||||
#define CONFIG_BITBANGMII_MULTI |
||||
|
||||
#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */ |
||||
#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */ |
||||
|
||||
#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0" |
||||
|
||||
#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */ |
||||
#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */ |
||||
|
||||
#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */ |
||||
|
||||
/*
|
||||
* CONFIG_PPC4xx_DDR_AUTOCALIBRATION |
||||
* |
||||
* Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx |
||||
* SDRAM Controller DDR autocalibration values and takes a lot longer |
||||
* to run than Method_B. |
||||
* (See the Method_A and Method_B algorithm discription in the file: |
||||
* arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) |
||||
* Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A |
||||
* |
||||
* DDR Autocalibration Method_B is the default. |
||||
*/ |
||||
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION |
||||
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION |
||||
#undef CONFIG_PPC4xx_DDR_METHOD_A |
||||
|
||||
#define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE) |
||||
|
||||
/* DDR1/2 SDRAM Device Control Register Data Values */ |
||||
#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \ |
||||
SDRAM_RXBAS_SDSZ_128MB | \
|
||||
SDRAM_RXBAS_SDAM_MODE2 | \
|
||||
SDRAM_RXBAS_SDBE_ENABLE) |
||||
#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE |
||||
#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE |
||||
#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE |
||||
#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ |
||||
SDRAM_MCOPT1_4_BANKS | \
|
||||
SDRAM_MCOPT1_DDR2_TYPE | \
|
||||
SDRAM_MCOPT1_QDEP | \
|
||||
SDRAM_MCOPT1_DCOO_DISABLED) |
||||
#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 |
||||
#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ |
||||
SDRAM_MODT_EB0R_ENABLE) |
||||
#define CONFIG_SYS_SDRAM0_MODT1 0x00000000 |
||||
#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ |
||||
SDRAM_CODT_CKLZ_36OHM | \
|
||||
SDRAM_CODT_DQS_1_8_V_DDR2 | \
|
||||
SDRAM_CODT_IO_NMODE) |
||||
#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(80) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(3) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(0)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
|
||||
JEDEC_MA_EMR_RTT_75OHM)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
|
||||
JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
|
||||
JEDEC_MA_MR_BLEN_4 | \
|
||||
JEDEC_MA_MR_DLL_RESET)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(3) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(0x0) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(26) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(26) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(26) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(26) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
|
||||
JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
|
||||
JEDEC_MA_MR_BLEN_4)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
|
||||
JEDEC_MA_EMR_RDQS_DISABLE | \
|
||||
JEDEC_MA_EMR_DQS_DISABLE | \
|
||||
JEDEC_MA_EMR_RTT_DISABLED | \
|
||||
JEDEC_MA_EMR_ODS_NORMAL)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ |
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
|
||||
JEDEC_MA_EMR_RDQS_DISABLE | \
|
||||
JEDEC_MA_EMR_DQS_DISABLE | \
|
||||
JEDEC_MA_EMR_RTT_DISABLED | \
|
||||
JEDEC_MA_EMR_ODS_NORMAL)) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) |
||||
#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) |
||||
#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ |
||||
SDRAM_RQDC_RQFD_ENCODE(56)) |
||||
#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) |
||||
#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) |
||||
#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ |
||||
SDRAM_DLCR_DLCS_CONT_DONE | \
|
||||
SDRAM_DLCR_DLCV_ENCODE(165)) |
||||
#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) |
||||
#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000 |
||||
#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ |
||||
SDRAM_SDTR1_RTW_2_CLK | \
|
||||
SDRAM_SDTR1_WTWO_1_CLK | \
|
||||
SDRAM_SDTR1_RTRO_1_CLK) |
||||
#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ |
||||
SDRAM_SDTR2_WTR_2_CLK | \
|
||||
SDRAM_SDTR2_XSNR_32_CLK | \
|
||||
SDRAM_SDTR2_WPC_4_CLK | \
|
||||
SDRAM_SDTR2_RPC_2_CLK | \
|
||||
SDRAM_SDTR2_RP_3_CLK | \
|
||||
SDRAM_SDTR2_RRD_2_CLK) |
||||
#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \ |
||||
SDRAM_SDTR3_RC_ENCODE(12) | \
|
||||
SDRAM_SDTR3_XCS | \
|
||||
SDRAM_SDTR3_RFC_ENCODE(21)) |
||||
#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ |
||||
SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
|
||||
SDRAM_MMODE_BLEN_4) |
||||
#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ |
||||
SDRAM_MEMODE_RTT_75OHM) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
|
||||
#define CONFIG_PCA9698 1 /* NXP PCA9698 */ |
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
/* I2C bootstrap EEPROM */ |
||||
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54 |
||||
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 |
||||
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 |
||||
|
||||
/* Temp sensor/hwmon/dtt */ |
||||
#define CONFIG_DTT_LM63 1 /* National LM63 */ |
||||
#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */ |
||||
#define CONFIG_DTT_PWM_LOOKUPTABLE \ |
||||
{ { 40, 10 }, { 43, 13 }, { 46, 16 }, \
|
||||
{ 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } |
||||
#define CONFIG_DTT_TACH_LIMIT 0xa10 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Ethernet |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_M88E1111_PHY 1 |
||||
#define CONFIG_IBM_EMAC4_V4 1 |
||||
#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII |
||||
#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */ |
||||
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
|
||||
#define CONFIG_HAS_ETH0 1 |
||||
|
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
||||
#define CONFIG_PHY1_ADDR 0x13 |
||||
|
||||
/* Debug messages for the DDR autocalibration */ |
||||
#define CONFIG_AUTOCALIB "silent\0" |
||||
|
||||
/*
|
||||
* Default environment variables |
||||
*/ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
CONFIG_AMCC_DEF_ENV \
|
||||
CONFIG_AMCC_DEF_ENV_POWERPC \
|
||||
CONFIG_AMCC_DEF_ENV_PPC_OLD \
|
||||
CONFIG_AMCC_DEF_ENV_NOR_UPD \
|
||||
"logversion=2\0" \
|
||||
"kernel_addr=fc000000\0" \
|
||||
"fdt_addr=fc1e0000\0" \
|
||||
"ramdisk_addr=fc200000\0" \
|
||||
"pciconfighost=1\0" \
|
||||
"pcie_mode=RP:RP\0" \
|
||||
"" |
||||
|
||||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h |
||||
*/ |
||||
#define CONFIG_CMD_CHIP_CONFIG |
||||
#define CONFIG_CMD_DTT |
||||
|
||||
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY |
||||
|
||||
/* POST support */ |
||||
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
||||
CONFIG_SYS_POST_CPU | \
|
||||
CONFIG_SYS_POST_ETHER | \
|
||||
CONFIG_SYS_POST_I2C | \
|
||||
CONFIG_SYS_POST_MEMORY_ON | \
|
||||
CONFIG_SYS_POST_UART) |
||||
|
||||
/* Define here the base-addresses of the UARTs to test in POST */ |
||||
#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ |
||||
CONFIG_SYS_NS16550_COM2 } |
||||
|
||||
#define CONFIG_LOGBUFFER |
||||
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ |
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*----------------------------------------------------------------------*/ |
||||
|
||||
/* Memory Bank 0 (NOR-flash) */ |
||||
#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ |
||||
EBC_BXAP_TWT_ENCODE(11) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(0) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(2) | \
|
||||
EBC_BXAP_TH_ENCODE(2) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED) |
||||
#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ |
||||
EBC_BXCR_BS_64MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT) |
||||
|
||||
/* Memory Bank 1 (NVRAM/Uart) */ |
||||
#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \ |
||||
EBC_BXAP_FWT_ENCODE(8) | \
|
||||
EBC_BXAP_BWT_ENCODE(4) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(1) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(2) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED) |
||||
#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \ |
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_8BIT) |
||||
|
||||
/* Memory Bank 2 (FPGA) */ |
||||
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ |
||||
EBC_BXAP_TWT_ENCODE(5) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(2) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(0) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED) |
||||
#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \ |
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT) |
||||
|
||||
/* Memory Bank 3 (Latches) */ |
||||
#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \ |
||||
EBC_BXAP_FWT_ENCODE(8) | \
|
||||
EBC_BXAP_BWT_ENCODE(4) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(1) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(2) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED) |
||||
#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \ |
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT) |
||||
|
||||
/* EBC peripherals */ |
||||
|
||||
#define CONFIG_SYS_FPGA_BASE(k) \ |
||||
(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE) |
||||
|
||||
#define CONFIG_SYS_FPGA_DONE(k) \ |
||||
(k ? 0x0040 : 0x0080) |
||||
|
||||
#define CONFIG_SYS_FPGA_COUNT 2 |
||||
|
||||
#define CONFIG_SYS_LATCH0_RESET 0xffff |
||||
#define CONFIG_SYS_LATCH0_BOOT 0xffff |
||||
#define CONFIG_SYS_LATCH1_RESET 0xffbf |
||||
#define CONFIG_SYS_LATCH1_BOOT 0xffff |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* GPIO Setup |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \ |
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \
|
||||
{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \
|
||||
} \
|
||||
} |
||||
|
||||
#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15 |
||||
#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
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Reference in new issue