dm: pch: Add get_io_base op

On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

drivers/pch/pch-uclass.c

@@ -44,6 +44,17 @@ int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
 	return ops->get_gpio_base(dev, gbasep);
 }
 
+int pch_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+	struct pch_ops *ops = pch_get_ops(dev);
+
+	*iobasep = 0;
+	if (!ops->get_io_base)
+		return -ENOSYS;
+
+	return ops->get_io_base(dev, iobasep);
+}
+
 static int pch_uclass_post_bind(struct udevice *bus)
 {
 	/*

include/pch.h

@@ -41,6 +41,15 @@ struct pch_ops {
 	 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
 	 */
 	int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
+
+	/**
+	 * get_io_base() - get the address of IO base
+	 *
+	 * @dev:	PCH device to check
+	 * @iobasep:	Returns address of IO base if available, else 0
+	 * @return 0 if OK, -ve on error (e.g. there is no IO base)
+	 */
+	int (*get_io_base)(struct udevice *dev, u32 *iobasep);
 };
 
 #define pch_get_ops(dev)        ((struct pch_ops *)(dev)->driver->ops)
@@ -73,4 +82,13 @@ int pch_set_spi_protect(struct udevice *dev, bool protect);
  */
 int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
 
+/**
+ * pch_get_io_base() - get the address of IO base
+ *
+ * @dev:	PCH device to check
+ * @iobasep:	Returns address of IO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
+ */
+int pch_get_io_base(struct udevice *dev, u32 *iobasep);
+
 #endif